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authorAmanShukla1112025-06-01 19:50:33 +0530
committerAmanShukla1112025-06-01 19:50:33 +0530
commitf829712c9540d758fabfe9bef014ade3a6d2c797 (patch)
tree2789d6f298b474b2f7da5d5b372da4784c794e83
parent432154bb698e2a47105af24d6f8dec44b04e06e3 (diff)
downloadeSim-f829712c9540d758fabfe9bef014ade3a6d2c797.tar.gz
eSim-f829712c9540d758fabfe9bef014ade3a6d2c797.tar.bz2
eSim-f829712c9540d758fabfe9bef014ade3a6d2c797.zip
Adding 74HC193-Presettable Synchronous 4-Bit Up/Down Counters
Diffstat
-rw-r--r--library/SubcircuitLibrary/74HC193/74HC193-cache.lib132
-rw-r--r--library/SubcircuitLibrary/74HC193/74HC193.cir28
-rw-r--r--library/SubcircuitLibrary/74HC193/74HC193.cir.out65
-rw-r--r--library/SubcircuitLibrary/74HC193/74HC193.pro73
-rw-r--r--library/SubcircuitLibrary/74HC193/74HC193.sch691
-rw-r--r--library/SubcircuitLibrary/74HC193/74HC193.sub59
-rw-r--r--library/SubcircuitLibrary/74HC193/74HC193_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/74HC193/analysis1
-rw-r--r--library/SubcircuitLibrary/74HC193/esim_library_backup.dcm7
-rw-r--r--library/SubcircuitLibrary/74HC193/esim_library_backup.lib698
-rw-r--r--library/SubcircuitLibrary/74HC193/jk_mux-cache.lib93
-rw-r--r--library/SubcircuitLibrary/74HC193/jk_mux-rescue.lib20
-rw-r--r--library/SubcircuitLibrary/74HC193/jk_mux.cir15
-rw-r--r--library/SubcircuitLibrary/74HC193/jk_mux.cir.out23
-rw-r--r--library/SubcircuitLibrary/74HC193/jk_mux.pro74
-rw-r--r--library/SubcircuitLibrary/74HC193/jk_mux.sch245
-rw-r--r--library/SubcircuitLibrary/74HC193/jk_mux.sub17
-rw-r--r--library/SubcircuitLibrary/74HC193/jk_mux_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/74HC193/mux-cache.lib94
-rw-r--r--library/SubcircuitLibrary/74HC193/mux.cir15
-rw-r--r--library/SubcircuitLibrary/74HC193/mux.cir.out28
-rw-r--r--library/SubcircuitLibrary/74HC193/mux.pro73
-rw-r--r--library/SubcircuitLibrary/74HC193/mux.sch167
-rw-r--r--library/SubcircuitLibrary/74HC193/mux.sub22
-rw-r--r--library/SubcircuitLibrary/74HC193/mux_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/74HC193/mux_and-cache.lib94
-rw-r--r--library/SubcircuitLibrary/74HC193/mux_and.cir15
-rw-r--r--library/SubcircuitLibrary/74HC193/mux_and.cir.out28
-rw-r--r--library/SubcircuitLibrary/74HC193/mux_and.pro73
-rw-r--r--library/SubcircuitLibrary/74HC193/mux_and.sch193
-rw-r--r--library/SubcircuitLibrary/74HC193/mux_and.sub22
-rw-r--r--library/SubcircuitLibrary/74HC193/mux_and_Previous_Values.xml1
32 files changed, 3069 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74HC193/74HC193-cache.lib b/library/SubcircuitLibrary/74HC193/74HC193-cache.lib
new file mode 100644
index 00000000..6ba04b25
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/74HC193-cache.lib
@@ -0,0 +1,132 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# jk_mux
+#
+DEF jk_mux X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "jk_mux" 0 150 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 650 350 -600 0 1 0 N
+X LD 1 -550 500 200 R 50 50 1 1 I
+X K 2 -550 150 200 R 50 50 1 1 I
+X J 3 -550 350 200 R 50 50 1 1 I
+X LD/CNT 4 0 -800 200 U 50 50 1 1 I
+X CLK 5 -550 0 200 R 50 50 1 1 I
+X SET 6 -550 -150 200 R 50 50 1 1 I
+X RESET 7 -550 -400 200 R 50 50 1 1 I
+X Q 8 550 400 200 L 50 50 1 1 O
+X NQ 9 550 -200 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC193/74HC193.cir b/library/SubcircuitLibrary/74HC193/74HC193.cir
new file mode 100644
index 00000000..d1909500
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/74HC193.cir
@@ -0,0 +1,28 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC193\74HC193.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 5/21/2025 2:42:48 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_U4-Pad1_ jk_mux
+X7 Net-_U1-Pad13_ Net-_U11-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_U1-Pad14_ Net-_U13-Pad1_ jk_mux
+X3 Net-_U1-Pad9_ Net-_U5-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_U1-Pad10_ Net-_U7-Pad2_ jk_mux
+X5 Net-_U1-Pad11_ Net-_U8-Pad3_ Net-_U8-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_U1-Pad12_ Net-_U10-Pad1_ jk_mux
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+U3 Net-_U1-Pad1_ Net-_U1-Pad8_ Net-_U3-Pad3_ d_and
+U4 Net-_U4-Pad1_ Net-_U2-Pad2_ Net-_U4-Pad3_ d_and
+U5 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U5-Pad3_ d_or
+U6 Net-_U3-Pad3_ Net-_U1-Pad10_ Net-_U6-Pad3_ d_and
+U7 Net-_U4-Pad3_ Net-_U7-Pad2_ Net-_U10-Pad2_ d_and
+U8 Net-_U6-Pad3_ Net-_U10-Pad2_ Net-_U8-Pad3_ d_or
+U9 Net-_U6-Pad3_ Net-_U1-Pad12_ Net-_U11-Pad1_ d_and
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and
+U11 Net-_U11-Pad1_ Net-_U10-Pad3_ Net-_U11-Pad3_ d_or
+U13 Net-_U13-Pad1_ Net-_U10-Pad3_ Net-_U1-Pad16_ d_nand
+U12 Net-_U11-Pad1_ Net-_U1-Pad14_ Net-_U12-Pad3_ d_and
+U14 Net-_U12-Pad3_ Net-_U1-Pad15_ d_inverter
+
+.end
diff --git a/library/SubcircuitLibrary/74HC193/74HC193.cir.out b/library/SubcircuitLibrary/74HC193/74HC193.cir.out
new file mode 100644
index 00000000..8e47f1f8
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/74HC193.cir.out
@@ -0,0 +1,65 @@
+* c:\fossee\esim\library\subcircuitlibrary\4_bit_updown_counter\4_bit_updown_counter.cir
+
+.include jk_mux.sub
+x1 net-_u1-pad5_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad7_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad8_ net-_u4-pad1_ jk_mux
+x7 net-_u1-pad13_ net-_u11-pad3_ net-_u11-pad3_ net-_u1-pad7_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad14_ net-_u13-pad1_ jk_mux
+x3 net-_u1-pad9_ net-_u5-pad3_ net-_u5-pad3_ net-_u1-pad7_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad10_ net-_u7-pad2_ jk_mux
+x5 net-_u1-pad11_ net-_u8-pad3_ net-_u8-pad3_ net-_u1-pad7_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad12_ net-_u10-pad1_ jk_mux
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ port
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3 net-_u1-pad1_ net-_u1-pad8_ net-_u3-pad3_ d_and
+* u4 net-_u4-pad1_ net-_u2-pad2_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ d_or
+* u6 net-_u3-pad3_ net-_u1-pad10_ net-_u6-pad3_ d_and
+* u7 net-_u4-pad3_ net-_u7-pad2_ net-_u10-pad2_ d_and
+* u8 net-_u6-pad3_ net-_u10-pad2_ net-_u8-pad3_ d_or
+* u9 net-_u6-pad3_ net-_u1-pad12_ net-_u11-pad1_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u11 net-_u11-pad1_ net-_u10-pad3_ net-_u11-pad3_ d_or
+* u12 net-_u11-pad1_ net-_u1-pad14_ net-_u1-pad15_ d_nand
+* u13 net-_u13-pad1_ net-_u10-pad3_ net-_u1-pad16_ d_nand
+a1 net-_u1-pad1_ net-_u2-pad2_ u2
+a2 [net-_u1-pad1_ net-_u1-pad8_ ] net-_u3-pad3_ u3
+a3 [net-_u4-pad1_ net-_u2-pad2_ ] net-_u4-pad3_ u4
+a4 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u5-pad3_ u5
+a5 [net-_u3-pad3_ net-_u1-pad10_ ] net-_u6-pad3_ u6
+a6 [net-_u4-pad3_ net-_u7-pad2_ ] net-_u10-pad2_ u7
+a7 [net-_u6-pad3_ net-_u10-pad2_ ] net-_u8-pad3_ u8
+a8 [net-_u6-pad3_ net-_u1-pad12_ ] net-_u11-pad1_ u9
+a9 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a10 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u11-pad3_ u11
+a11 [net-_u11-pad1_ net-_u1-pad14_ ] net-_u1-pad15_ u12
+a12 [net-_u13-pad1_ net-_u10-pad3_ ] net-_u1-pad16_ u13
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC193/74HC193.pro b/library/SubcircuitLibrary/74HC193/74HC193.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/74HC193.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC193/74HC193.sch b/library/SubcircuitLibrary/74HC193/74HC193.sch
new file mode 100644
index 00000000..53594952
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/74HC193.sch
@@ -0,0 +1,691 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:4_bit_updown_counter-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L jk_mux X1
+U 1 1 67CB2B93
+P 2200 3950
+F 0 "X1" H 2200 3950 60 0000 C CNN
+F 1 "jk_mux" H 2200 4100 60 0000 C CNN
+F 2 "" H 2200 3950 60 0001 C CNN
+F 3 "" H 2200 3950 60 0001 C CNN
+ 1 2200 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L jk_mux X7
+U 1 1 67CB2C1E
+P 10000 3950
+F 0 "X7" H 10000 3950 60 0000 C CNN
+F 1 "jk_mux" H 10000 4100 60 0000 C CNN
+F 2 "" H 10000 3950 60 0001 C CNN
+F 3 "" H 10000 3950 60 0001 C CNN
+ 1 10000 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L jk_mux X3
+U 1 1 67CB2CAB
+P 4750 3950
+F 0 "X3" H 4750 3950 60 0000 C CNN
+F 1 "jk_mux" H 4750 4100 60 0000 C CNN
+F 2 "" H 4750 3950 60 0001 C CNN
+F 3 "" H 4750 3950 60 0001 C CNN
+ 1 4750 3950
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+$Comp
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+ -1 0 0 1
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+$Comp
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+F 2 "" H 9850 1850 60 0000 C CNN
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+ 1 9850 1850
+ 1 0 0 -1
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+$Comp
+L d_inverter U14
+U 1 1 67DEB593
+P 10600 1300
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+F 2 "" H 10650 1250 60 0000 C CNN
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+ 1 0 0 -1
+$EndComp
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diff --git a/library/SubcircuitLibrary/74HC193/74HC193.sub b/library/SubcircuitLibrary/74HC193/74HC193.sub
new file mode 100644
index 00000000..7d294170
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/74HC193.sub
@@ -0,0 +1,59 @@
+* Subcircuit 4_bit_updown_counter
+.subckt 4_bit_updown_counter net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_
+* c:\fossee\esim\library\subcircuitlibrary\4_bit_updown_counter\4_bit_updown_counter.cir
+.include jk_mux.sub
+x1 net-_u1-pad5_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad7_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad8_ net-_u4-pad1_ jk_mux
+x7 net-_u1-pad13_ net-_u11-pad3_ net-_u11-pad3_ net-_u1-pad7_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad14_ net-_u13-pad1_ jk_mux
+x3 net-_u1-pad9_ net-_u5-pad3_ net-_u5-pad3_ net-_u1-pad7_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad10_ net-_u7-pad2_ jk_mux
+x5 net-_u1-pad11_ net-_u8-pad3_ net-_u8-pad3_ net-_u1-pad7_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad12_ net-_u10-pad1_ jk_mux
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3 net-_u1-pad1_ net-_u1-pad8_ net-_u3-pad3_ d_and
+* u4 net-_u4-pad1_ net-_u2-pad2_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ d_or
+* u6 net-_u3-pad3_ net-_u1-pad10_ net-_u6-pad3_ d_and
+* u7 net-_u4-pad3_ net-_u7-pad2_ net-_u10-pad2_ d_and
+* u8 net-_u6-pad3_ net-_u10-pad2_ net-_u8-pad3_ d_or
+* u9 net-_u6-pad3_ net-_u1-pad12_ net-_u11-pad1_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u11 net-_u11-pad1_ net-_u10-pad3_ net-_u11-pad3_ d_or
+* u12 net-_u11-pad1_ net-_u1-pad14_ net-_u1-pad15_ d_nand
+* u13 net-_u13-pad1_ net-_u10-pad3_ net-_u1-pad16_ d_nand
+a1 net-_u1-pad1_ net-_u2-pad2_ u2
+a2 [net-_u1-pad1_ net-_u1-pad8_ ] net-_u3-pad3_ u3
+a3 [net-_u4-pad1_ net-_u2-pad2_ ] net-_u4-pad3_ u4
+a4 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u5-pad3_ u5
+a5 [net-_u3-pad3_ net-_u1-pad10_ ] net-_u6-pad3_ u6
+a6 [net-_u4-pad3_ net-_u7-pad2_ ] net-_u10-pad2_ u7
+a7 [net-_u6-pad3_ net-_u10-pad2_ ] net-_u8-pad3_ u8
+a8 [net-_u6-pad3_ net-_u1-pad12_ ] net-_u11-pad1_ u9
+a9 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a10 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u11-pad3_ u11
+a11 [net-_u11-pad1_ net-_u1-pad14_ ] net-_u1-pad15_ u12
+a12 [net-_u13-pad1_ net-_u10-pad3_ ] net-_u1-pad16_ u13
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 4_bit_updown_counter \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC193/74HC193_Previous_Values.xml b/library/SubcircuitLibrary/74HC193/74HC193_Previous_Values.xml
new file mode 100644
index 00000000..920a36ef
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/74HC193_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u3 name="type">d_tff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)">1.0e-9</field3><field4 name="Enter IC (default=0)" /><field5 name="Enter value for T Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u3><u7 name="type">d_tff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)">1.0e-9</field13><field14 name="Enter IC (default=0)" /><field15 name="Enter value for T Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u7><u11 name="type">d_tff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)">1.0e-9</field23><field24 name="Enter IC (default=0)" /><field25 name="Enter value for T Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u11><u15 name="type">d_tff<field31 name="Enter Clk Delay (default=1.0e-9)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter Reset Delay (default=1.0)">1.0e-9</field33><field34 name="Enter IC (default=0)" /><field35 name="Enter value for T Load (default=1.0e-12)" /><field36 name="Enter value for Clk Load (default=1.0e-12)" /><field37 name="Enter value for Set Load (default=1.0e-12)" /><field38 name="Enter value for Reset Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /></u15><u6 name="type">d_or<field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /><field43 name="Enter Input Load (default=1.0e-12)" /></u6><u10 name="type">d_or<field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /><field46 name="Enter Input Load (default=1.0e-12)" /></u10><u14 name="type">d_or<field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /></u14><u5 name="type">d_and<field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /></u5><u4 name="type">d_and<field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /></u4><u8 name="type">d_and<field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_and<field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /></u9><u12 name="type">d_and<field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_and<field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /></u13><u2 name="type">d_inverter<field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u5 name="type">d_or<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_or<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u10 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_or<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\jk_mux</field></x1><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\jk_mux</field></x7><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\jk_mux</field></x3><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\jk_mux</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC193/analysis b/library/SubcircuitLibrary/74HC193/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC193/esim_library_backup.dcm b/library/SubcircuitLibrary/74HC193/esim_library_backup.dcm
new file mode 100644
index 00000000..763f9bcf
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/esim_library_backup.dcm
@@ -0,0 +1,7 @@
+EESchema-DOCLIB Version 2.0
+#
+$CMP SCR
+D Thyristor
+$ENDCMP
+#
+#End Doc Library
diff --git a/library/SubcircuitLibrary/74HC193/esim_library_backup.lib b/library/SubcircuitLibrary/74HC193/esim_library_backup.lib
new file mode 100644
index 00000000..20fe4fdd
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/esim_library_backup.lib
@@ -0,0 +1,698 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 10bitDAC
+#
+DEF 10bitDAC X 0 40 Y Y 1 F N
+F0 "X" 0 50 60 H V C CNN
+F1 "10bitDAC" -50 -50 60 H V C CNN
+F2 "" 0 50 60 H I C CNN
+F3 "" 0 50 60 H I C CNN
+DRAW
+S -500 500 400 -600 0 1 0 N
+X D0 1 -700 -500 200 R 50 50 1 1 I
+X D1 2 -700 -400 200 R 50 50 1 1 I
+X D2 3 -700 -300 200 R 50 50 1 1 I
+X D3 4 -700 -200 200 R 50 50 1 1 I
+X D4 5 -700 -100 200 R 50 50 1 1 I
+X D5 6 -700 0 200 R 50 50 1 1 I
+X D6 7 -700 100 200 R 50 50 1 1 I
+X D7 8 -700 200 200 R 50 50 1 1 I
+X D8 9 -700 300 200 R 50 50 1 1 I
+X D9 10 -700 400 200 R 50 50 1 1 I
+X AnalogOut 11 600 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 2BITMUL
+#
+DEF 2BITMUL X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "2BITMUL" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 400 300 -400 0 1 0 N
+X A0 1 -500 300 200 R 50 50 1 1 I
+X A1 2 -500 150 200 R 50 50 1 1 I
+X B0 3 -500 -50 200 R 50 50 1 1 I
+X B1 4 -500 -250 200 R 50 50 1 1 I
+X M0 5 500 250 200 L 50 50 1 1 O
+X M1 6 500 100 200 L 50 50 1 1 O
+X M2 7 500 -50 200 L 50 50 1 1 O
+X M3 8 500 -250 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_OR
+#
+DEF 4_OR X 0 40 Y Y 1 F N
+F0 "X" 150 -100 60 H V C CNN
+F1 "4_OR" 150 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
+A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
+A -30 -99 393 627 146 0 1 0 N 150 250 350 0
+P 2 0 1 0 -200 -250 150 -250 N
+P 2 0 1 0 -200 250 150 250 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X in4 4 -350 -150 200 R 50 50 1 1 I
+X out 5 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_bit_updown_counter
+#
+DEF 4_bit_updown_counter X 0 40 Y Y 1 F N
+F0 "X" 0 -200 60 H V C CNN
+F1 "4_bit_updown_counter" 0 -400 60 H V C CNN
+F2 "" 0 -400 60 H I C CNN
+F3 "" 0 -400 60 H I C CNN
+DRAW
+S -650 950 650 -850 0 1 0 N
+X CLK 1 -850 0 200 R 50 50 1 1 I
+X VCC 2 -850 800 200 R 50 50 1 1 I
+X UP/DOWN 3 -850 600 200 R 50 50 1 1 I
+X O1 4 850 600 200 L 50 50 1 1 O
+X O2 5 850 400 200 L 50 50 1 1 O
+X O3 6 850 200 200 L 50 50 1 1 O
+X O4 7 850 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 556
+#
+DEF 556 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "556" 0 0 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 250 -550 0 1 0 N
+X dis1 1 -500 150 200 R 50 50 1 1 I
+X thr1 2 -500 -150 200 R 50 50 1 1 I
+X cv1 3 -150 -750 200 U 50 50 1 1 I
+X rst1 4 -200 600 200 D 50 50 1 1 I
+X out1 5 -500 0 200 R 50 50 1 1 O
+X trig1 6 -500 -300 200 R 50 50 1 1 I
+X gnd 7 0 -750 200 U 50 50 1 1 I
+X trig2 8 450 -300 200 L 50 50 1 1 I
+X out2 9 450 0 200 L 50 50 1 1 O
+X rst2 10 100 600 200 D 50 50 1 1 I
+X cv2 11 150 -750 200 U 50 50 1 1 I
+X thr2 12 450 -150 200 L 50 50 1 1 I
+X dis2 13 450 150 200 L 50 50 1 1 I
+X vcc 14 -50 600 200 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# 5_and
+#
+DEF 5_and X 0 40 Y Y 1 F N
+F0 "X" 50 -100 60 H V C CNN
+F1 "5_and" 100 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
+P 2 0 1 0 -250 250 150 250 N
+P 3 0 1 0 -250 250 -250 -250 150 -250 N
+X in1 1 -450 200 200 R 50 50 1 1 I
+X in2 2 -450 100 200 R 50 50 1 1 I
+X in3 3 -450 0 200 R 50 50 1 1 I
+X in4 4 -450 -100 200 R 50 50 1 1 I
+X in5 5 -450 -200 200 R 50 50 1 1 I
+X out 6 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CMOS_NAND
+#
+DEF CMOS_NAND X 0 40 Y Y 1 F N
+F0 "X" -100 -150 60 H V C CNN
+F1 "CMOS_NAND" 0 -50 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -350 300 300 300 N
+P 3 0 1 0 -350 300 -350 -400 300 -400 N
+X in1 1 -550 250 200 R 50 50 1 1 I
+X in2 2 -550 -300 200 R 50 50 1 1 I
+X out 3 800 0 279 L 79 79 1 1 I
+ENDDRAW
+ENDDEF
+#
+# Clock_pulse_generator
+#
+DEF Clock_pulse_generator X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "Clock_pulse_generator" 0 -100 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -550 200 600 -300 0 1 0 N
+X Vdd 1 -750 100 200 R 50 50 1 1 I
+X R 2 -750 -50 200 R 50 50 1 1 I
+X C 3 -750 -200 200 R 50 50 1 1 I
+X Clkout 4 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_4002
+#
+DEF IC_4002 X 0 40 Y Y 1 F N
+F0 "X" 0 150 60 H V C CNN
+F1 "IC_4002" 0 0 60 H V C CNN
+F2 "" 50 -150 60 H V C CNN
+F3 "" 50 -150 60 H V C CNN
+DRAW
+S -250 350 250 -400 0 1 0 N
+X 1Y 1 -450 250 200 R 50 50 1 1 O
+X 1A 2 -450 150 200 R 50 50 1 1 I
+X 1B 3 -450 50 200 R 50 50 1 1 I
+X 1C 4 -450 -50 200 R 50 50 1 1 I
+X 1D 5 -450 -150 200 R 50 50 1 1 I
+X NC 6 -450 -250 200 R 50 50 1 1 I
+X GND 7 -450 -350 200 R 50 50 1 1 I
+X NC 8 450 -350 200 L 50 50 1 1 I
+X 2A 9 450 -250 200 L 50 50 1 1 I
+X 2B 10 450 -150 200 L 50 50 1 1 I
+X 2C 11 450 -50 200 L 50 50 1 1 I
+X 2D 12 450 50 200 L 50 50 1 1 I
+X 2Y 13 450 150 200 L 50 50 1 1 O
+X VCC 14 450 250 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4012
+#
+DEF IC_4012 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "IC_4012" 0 200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 350 -400 0 1 0 N
+X Q1 1 -500 300 200 R 50 50 1 1 O
+X A1 2 -500 200 200 R 50 50 1 1 I
+X B1 3 -500 100 200 R 50 50 1 1 I
+X C1 4 -500 0 200 R 50 50 1 1 I
+X D1 5 -500 -100 200 R 50 50 1 1 I
+X NC 6 -500 -200 200 R 50 50 1 1 N
+X VSS 7 -500 -300 200 R 50 50 1 1 I
+X NC 8 550 -300 200 L 50 50 1 1 N
+X A2 9 550 -200 200 L 50 50 1 1 I
+X B2 10 550 -100 200 L 50 50 1 1 I
+X C2 11 550 0 200 L 50 50 1 1 I
+X D2 12 550 100 200 L 50 50 1 1 I
+X Q2 13 550 200 200 L 50 50 1 1 O
+X VDD 14 550 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4017
+#
+DEF IC_4017 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "IC_4017" 0 0 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 850 400 -850 0 1 0 N
+X 1 1 600 650 200 L 50 50 1 1 O
+X 2 2 600 500 200 L 50 50 1 1 O
+X 3 3 600 350 200 L 50 50 1 1 O
+X 4 4 600 200 200 L 50 50 1 1 O
+X 5 5 600 50 200 L 50 50 1 1 O
+X 6 6 600 -100 200 L 50 50 1 1 O
+X 7 7 600 -250 200 L 50 50 1 1 O
+X 8 8 600 -400 200 L 50 50 1 1 O
+X 9 9 600 -600 200 L 50 50 1 1 O
+X 10 10 600 -750 200 L 50 50 1 1 O
+X RST 11 -550 -400 200 R 50 50 1 1 I
+X CLK 12 -550 350 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4023
+#
+DEF IC_4023 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "IC_4023" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X A1 1 -500 300 200 R 50 50 1 1 I
+X B1 2 -500 200 200 R 50 50 1 1 I
+X A2 3 -500 100 200 R 50 50 1 1 I
+X B2 4 -500 0 200 R 50 50 1 1 I
+X C2 5 -500 -100 200 R 50 50 1 1 I
+X Q2 6 -500 -200 200 R 50 50 1 1 O
+X Vss 7 -500 -300 200 R 50 50 1 1 I
+X C1 8 500 -300 200 L 50 50 1 1 I
+X Q1 9 500 -200 200 L 50 50 1 1 O
+X Q3 10 500 -100 200 L 50 50 1 1 O
+X C3 11 500 0 200 L 50 50 1 1 I
+X B3 12 500 100 200 L 50 50 1 1 I
+X A3 13 500 200 200 L 50 50 1 1 I
+X Vdd 14 500 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4028
+#
+DEF IC_4028 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "IC_4028" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X Q4 1 -500 350 200 R 50 50 1 1 O
+X Q2 2 -500 250 200 R 50 50 1 1 O
+X Q0 3 -500 150 200 R 50 50 1 1 O
+X Q7 4 -500 50 200 R 50 50 1 1 O
+X Q9 5 -500 -50 200 R 50 50 1 1 O
+X Q5 6 -500 -150 200 R 50 50 1 1 O
+X Q6 7 -500 -250 200 R 50 50 1 1 O
+X Vss 8 -500 -350 200 R 50 50 1 1 I
+X Q8 9 500 -350 200 L 50 50 1 1 O
+X A0 10 500 -250 200 L 50 50 1 1 I
+X A3 11 500 -150 200 L 50 50 1 1 I
+X A2 12 500 -50 200 L 50 50 1 1 I
+X A1 13 500 50 200 L 50 50 1 1 I
+X Q1 14 500 150 200 L 50 50 1 1 O
+X Q3 15 500 250 200 L 50 50 1 1 O
+X Vdd 16 500 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_4073
+#
+DEF IC_4073 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "IC_4073" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 300 -400 0 1 0 N
+X A1 1 -500 300 200 R 50 50 1 1 I
+X B1 2 -500 200 200 R 50 50 1 1 I
+X A2 3 -500 100 200 R 50 50 1 1 I
+X B2 4 -500 0 200 R 50 50 1 1 I
+X C2 5 -500 -100 200 R 50 50 1 1 I
+X Q2 6 -500 -200 200 R 50 50 1 1 O
+X Vss 7 -500 -300 200 R 50 50 1 1 I
+X C1 8 500 -300 200 L 50 50 1 1 I
+X Q1 9 500 -200 200 L 50 50 1 1 O
+X Q3 10 500 -100 200 L 50 50 1 1 O
+X A3 11 500 0 200 L 50 50 1 1 I
+X B3 12 500 100 200 L 50 50 1 1 I
+X C3 13 500 200 200 L 50 50 1 1 I
+X Vdd 14 500 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_74153
+#
+DEF IC_74153 X 0 40 Y Y 1 F N
+F0 "X" 100 50 60 H V C CNN
+F1 "IC_74153" 100 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+T 0 100 -200 60 0 0 0 4:1 Normal 0 C C
+T 0 100 -100 60 0 0 0 DUAL Normal 0 C C
+T 0 100 -300 60 0 0 0 MUX Normal 0 C C
+S -200 500 350 -550 0 1 0 N
+X a0 1 -400 350 200 R 50 50 1 1 I
+X a1 2 -400 250 200 R 50 50 1 1 I
+X a2 3 -400 150 200 R 50 50 1 1 I
+X a3 4 -400 50 200 R 50 50 1 1 I
+X EA 5 0 700 200 D 50 50 1 1 I I
+X b0 6 -400 -150 200 R 50 50 1 1 I
+X b1 7 -400 -250 200 R 50 50 1 1 I
+X b2 8 -400 -350 200 R 50 50 1 1 I
+X b3 9 -400 -450 200 R 50 50 1 1 I
+X EB 10 200 700 200 D 50 50 1 1 I I
+X s1 11 50 -750 200 U 50 50 1 1 I
+X s0 12 150 -750 200 U 50 50 1 1 I
+X ya 13 550 250 200 L 50 50 1 1 O
+X yb 14 550 -300 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_74154
+#
+DEF IC_74154 X 0 40 Y Y 1 F N
+F0 "X" 0 -200 60 H V C CNN
+F1 "IC_74154" 50 -50 60 H V C CNN
+F2 "" 0 50 60 H V C CNN
+F3 "" 0 50 60 H V C CNN
+DRAW
+T 0 0 400 60 0 0 0 4:16~ Normal 0 C C
+T 0 0 250 60 0 0 0 decoder Normal 0 C C
+S -350 700 400 -700 0 0 0 N
+X ~Y0 1 -550 550 200 R 50 50 1 1 O I
+X ~Y1 2 -550 450 200 R 50 50 1 1 O I
+X ~Y2 3 -550 350 200 R 50 50 1 1 O I
+X ~Y3 4 -550 250 200 R 50 50 1 1 O I
+X ~Y4 5 -550 150 200 R 50 50 1 1 O I
+X ~Y5 6 -550 50 200 R 50 50 1 1 O I
+X ~Y6 7 -550 -50 200 R 50 50 1 1 O I
+X ~Y7 8 -550 -150 200 R 50 50 1 1 O I
+X ~Y8 9 -550 -250 200 R 50 50 1 1 O I
+X ~Y9 10 -550 -350 200 R 50 50 1 1 O I
+X A3 20 600 150 200 L 50 50 1 1 I
+X ~Y10 11 -550 -450 200 R 50 50 1 1 O I
+X A2 21 600 250 200 L 50 50 1 1 I
+X GND 12 -550 -550 200 R 50 50 1 1 I
+X A1 22 600 350 200 L 50 50 1 1 I
+X ~Y11 13 600 -550 200 L 50 50 1 1 O I
+X A0 23 600 450 200 L 50 50 1 1 I
+X ~Y12 14 600 -450 200 L 50 50 1 1 O I
+X Vcc 24 600 550 200 L 50 50 1 1 I
+X ~Y13 15 600 -350 200 L 50 50 1 1 O I
+X ~Y14 16 600 -250 200 L 50 50 1 1 O I
+X ~Y15 17 600 -150 200 L 50 50 1 1 O I
+X ~E0 18 600 -50 200 L 50 50 1 1 I I
+X ~E1 19 600 50 200 L 50 50 1 1 I I
+ENDDRAW
+ENDDEF
+#
+# IC_74157
+#
+DEF IC_74157 X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "IC_74157" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+T 0 50 -300 60 0 0 0 2:1 Normal 0 C C
+T 0 50 -400 60 0 0 0 MUX Normal 0 C C
+T 0 50 -200 60 0 0 0 QUAD Normal 0 C C
+S -350 550 400 -650 0 1 0 N
+X a0 1 -550 450 200 R 50 50 1 1 I
+X a1 2 -550 300 200 R 50 50 1 1 I
+X b0 3 -550 200 200 R 50 50 1 1 I
+X b1 4 -550 100 200 R 50 50 1 1 I
+X c0 5 -550 0 200 R 50 50 1 1 I
+X c1 6 -550 -100 200 R 50 50 1 1 I
+X d0 7 -550 -200 200 R 50 50 1 1 I
+X d1 8 -550 -300 200 R 50 50 1 1 I
+X EN 9 -550 -550 200 R 50 50 1 1 I I
+X S 10 -550 -450 200 R 50 50 1 1 I
+X Yd 11 600 0 200 L 50 50 1 1 O
+X Ya 12 600 300 200 L 50 50 1 1 O
+X Yb 13 600 200 200 L 50 50 1 1 O
+X Yc 14 600 100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_7485
+#
+DEF IC_7485 X 0 40 Y Y 1 F N
+F0 "X" -50 -100 60 H V C CNN
+F1 "IC_7485" -50 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C
+S -350 450 400 -400 0 1 0 N
+X A<B(in) 1 600 -100 200 L 50 50 1 1 I
+X A=B(in) 2 600 -200 200 L 50 50 1 1 I
+X A>B(in) 3 600 -300 200 L 50 50 1 1 I
+X A3 4 -550 100 200 R 50 50 1 1 I
+X B3 5 -550 -350 200 R 50 50 1 1 I
+X A2 6 -550 200 200 R 50 50 1 1 I
+X B2 7 -550 -250 200 R 50 50 1 1 I
+X A1 8 -550 300 200 R 50 50 1 1 I
+X B1 9 -550 -150 200 R 50 50 1 1 I
+X A0 10 -550 400 200 R 50 50 1 1 I
+X B0 11 -550 -50 200 R 50 50 1 1 I
+X A>B(out) 12 600 350 200 L 50 50 1 1 O
+X A=B(out) 13 600 250 200 L 50 50 1 1 O
+X A<B(out) 14 600 150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# INVCMOS
+#
+DEF INVCMOS X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "INVCMOS" -450 150 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 400 0 112 0 1 0 N
+S -250 200 -250 -200 0 1 0 N
+P 3 0 1 0 -250 200 300 0 -250 -200 N
+X in 1 -450 0 200 R 50 50 1 1 P
+X out 2 700 0 200 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# LM555N
+#
+DEF LM555N X 0 40 Y Y 1 F N
+F0 "X" 0 -50 60 H V C CNN
+F1 "LM555N" 0 100 60 H V C CNN
+F2 "" -50 0 60 H V C CNN
+F3 "" -50 0 60 H V C CNN
+DRAW
+S 350 -400 -350 400 0 1 0 N
+X GND 1 0 -600 200 U 50 50 1 1 W
+X TR 2 -550 250 200 R 50 50 1 1 I
+X Q 3 550 250 200 L 50 50 1 1 O
+X R 4 -550 -250 200 R 50 50 1 1 I I
+X CV 5 -550 0 200 R 50 50 1 1 I
+X THR 6 550 -250 200 L 50 50 1 1 I
+X DIS 7 550 0 200 L 50 50 1 1 I
+X VCC 8 0 600 200 D 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# LM_7812
+#
+DEF LM_7812 X 0 40 Y Y 1 F N
+F0 "X" 0 50 60 H V C CNN
+F1 "LM_7812" 0 150 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 200 350 -200 0 1 0 N
+X IN 1 -550 0 200 R 50 50 1 1 I
+X GND 2 0 -400 200 U 50 50 1 1 I
+X OUT 3 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Lm_7805
+#
+DEF Lm_7805 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "Lm_7805" 50 150 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 100 350 -200 0 1 0 N
+X Vin 1 -550 0 200 R 50 50 1 1 P
+X GND 2 0 -400 200 U 50 50 1 1 P
+X Vout 3 550 0 200 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# SCR
+#
+DEF SCR X 0 10 Y N 1 F N
+F0 "X" 150 200 50 H V C CNN
+F1 "SCR" 150 -350 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 2 0 0 0 -200 -150 200 -150 N
+P 2 0 1 0 0 -150 -200 -400 N
+P 3 0 1 0 -150 100 150 100 0 -150 F
+X A 1 0 400 300 D 60 60 1 1 I
+X K 2 0 -550 400 U 60 70 1 1 I
+X G 3 -350 -400 150 R 60 60 1 1 I
+ENDDRAW
+ENDDEF
+#
+# UJT
+#
+DEF UJT X 0 40 Y Y 1 F N
+F0 "X" -50 -50 60 H V C CNN
+F1 "UJT" 50 -50 60 H V C CNN
+F2 "" -50 -50 60 H I C CNN
+F3 "" -50 -50 60 H I C CNN
+DRAW
+C -50 -50 206 0 1 0 N
+P 2 0 1 0 -100 100 -100 -200 N
+P 3 0 1 0 -250 0 -200 0 -100 -100 N
+P 3 0 1 0 -200 -50 -150 -50 -150 0 N
+P 3 0 1 0 -100 -150 0 -150 0 -250 N
+P 3 0 1 0 -100 50 0 50 0 150 N
+X E 1 -450 0 200 R 50 50 1 1 I
+X B1 2 0 -450 200 U 50 50 1 1 B
+X B2 3 0 350 200 D 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_74LS04
+#
+DEF eSim_74LS04 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "eSim_74LS04" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S 350 500 -350 -500 0 1 0 N
+X ~ 1 -550 450 200 R 50 50 1 1 P
+X ~ 2 -550 300 200 R 50 50 1 1 P I
+X ~ 3 -550 150 200 R 50 50 1 1 P
+X ~ 4 -550 0 200 R 50 50 1 1 P I
+X ~ 5 -550 -150 200 R 50 50 1 1 P
+X ~ 6 -550 -300 200 R 50 50 1 1 P I
+X GND 7 -550 -450 200 R 50 50 1 1 P
+X ~ 8 550 -450 200 L 50 50 1 1 P I
+X ~ 9 550 -300 200 L 50 50 1 1 P
+X ~ 10 550 -150 200 L 50 50 1 1 P I
+X ~ 11 550 0 200 L 50 50 1 1 P
+X ~ 12 550 150 200 L 50 50 1 1 P I
+X ~ 13 550 300 200 L 50 50 1 1 P
+X VCC 14 550 450 200 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# full_adder
+#
+DEF full_adder X 0 40 Y Y 1 F N
+F0 "X" 1400 700 60 H V C CNN
+F1 "full_adder" 1400 600 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 800 1150 1950 0 0 1 0 N
+X IN1 1 600 950 200 R 50 50 1 1 I
+X IN2 2 600 550 200 R 50 50 1 1 I
+X CIN 3 600 150 200 R 50 50 1 1 I
+X SUM 4 2150 950 200 L 50 50 1 1 O
+X COUT 5 2150 150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# full_sub
+#
+DEF full_sub X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "full_sub" 0 0 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -550 650 450 -600 0 1 0 N
+X A 1 -750 400 200 R 50 50 1 1 I
+X B 2 -750 200 200 R 50 50 1 1 I
+X BIN 3 -750 -200 200 R 50 50 1 1 I
+X DIFF 4 650 450 200 L 50 50 1 1 O
+X BORROW 5 650 150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# half_adder
+#
+DEF half_adder X 0 40 Y Y 1 F N
+F0 "X" 900 500 60 H V C CNN
+F1 "half_adder" 900 400 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 500 800 1250 0 0 1 0 N
+X IN1 1 300 700 200 R 50 50 1 1 I
+X IN2 2 300 100 200 R 50 50 1 1 I
+X SUM 3 1450 700 200 L 50 50 1 1 O
+X COUT 4 1450 100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# half_sub
+#
+DEF half_sub X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "half_sub" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 300 300 -300 0 1 0 N
+X A 1 -500 200 200 R 50 50 1 1 I
+X B 2 -500 -100 200 R 50 50 1 1 I
+X D 3 500 150 200 L 50 50 1 1 O
+X BORROW 4 500 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# lm_741
+#
+DEF lm_741 X 0 40 Y Y 1 F N
+F0 "X" -200 0 60 H V C CNN
+F1 "lm_741" -100 -250 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N
+X off_null 1 -50 400 200 D 50 38 1 1 I
+X inv 2 -550 150 200 R 50 38 1 1 I
+X non_inv 3 -550 -100 200 R 50 38 1 1 I
+X v_neg 4 -150 -450 200 U 50 38 1 1 I
+X off_null 5 50 350 200 D 50 38 1 1 I
+X out 6 550 0 200 L 50 38 1 1 O
+X v_pos 7 -150 450 200 D 50 38 1 1 I
+X NC 8 150 -300 200 U 50 38 1 1 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC193/jk_mux-cache.lib b/library/SubcircuitLibrary/74HC193/jk_mux-cache.lib
new file mode 100644
index 00000000..e122b7fe
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/jk_mux-cache.lib
@@ -0,0 +1,93 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_jkff
+#
+DEF d_jkff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_jkff" 0 -150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 350 -400 -500 0 1 0 N
+X J 1 -600 250 200 R 50 50 1 1 I
+X K 2 -600 -350 200 R 50 50 1 1 I
+X Clk 3 -600 -50 200 R 50 50 1 1 I C
+X Set 4 0 550 200 D 50 50 1 1 I
+X Reset 5 0 -700 200 U 50 50 1 1 I
+X Out 6 550 250 200 L 50 50 1 1 O
+X Nout 7 550 -350 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# mux
+#
+DEF mux X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "mux" 0 150 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -200 350 200 -250 0 1 0 N
+X SEL 1 0 -450 200 U 50 50 1 1 I
+X 0 2 -400 200 200 R 50 50 1 1 I
+X 1 3 -400 -150 200 R 50 50 1 1 I
+X Z 4 400 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC193/jk_mux-rescue.lib b/library/SubcircuitLibrary/74HC193/jk_mux-rescue.lib
new file mode 100644
index 00000000..2002df8f
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/jk_mux-rescue.lib
@@ -0,0 +1,20 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# mux-RESCUE-jk_mux
+#
+DEF mux-RESCUE-jk_mux X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "mux-RESCUE-jk_mux" 0 150 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -200 350 200 -250 0 1 0 N
+X SEL 1 0 -450 200 U 50 50 1 1 I
+X A 2 -400 200 200 R 50 50 1 1 I
+X B 3 -400 -150 200 R 50 50 1 1 I
+X Z 4 400 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC193/jk_mux.cir b/library/SubcircuitLibrary/74HC193/jk_mux.cir
new file mode 100644
index 00000000..81055bf1
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/jk_mux.cir
@@ -0,0 +1,15 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\jk_mux\jk_mux.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 3/7/2025 10:48:37 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ d_jkff
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+X1 Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U3-Pad1_ mux
+X2 Net-_U1-Pad4_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U3-Pad2_ mux
+
+.end
diff --git a/library/SubcircuitLibrary/74HC193/jk_mux.cir.out b/library/SubcircuitLibrary/74HC193/jk_mux.cir.out
new file mode 100644
index 00000000..a0decf4d
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/jk_mux.cir.out
@@ -0,0 +1,23 @@
+* c:\fossee\esim\library\subcircuitlibrary\jk_mux\jk_mux.cir
+
+.include mux.sub
+* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ d_jkff
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+x1 net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad3_ net-_u3-pad1_ mux
+x2 net-_u1-pad4_ net-_u2-pad2_ net-_u1-pad2_ net-_u3-pad2_ mux
+a1 net-_u3-pad1_ net-_u3-pad2_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ u3
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_jkff, NgSpice Name: d_jkff
+.model u3 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC193/jk_mux.pro b/library/SubcircuitLibrary/74HC193/jk_mux.pro
new file mode 100644
index 00000000..f402ef4d
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/jk_mux.pro
@@ -0,0 +1,74 @@
+update=3/7/2025 10:30:26 PM
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=jk_mux-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC193/jk_mux.sch b/library/SubcircuitLibrary/74HC193/jk_mux.sch
new file mode 100644
index 00000000..24617448
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/jk_mux.sch
@@ -0,0 +1,245 @@
+EESchema Schematic File Version 2
+LIBS:jk_mux-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:jk_mux-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+Title ""
+Date ""
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+Comp ""
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+Comment2 ""
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+$Comp
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+$EndComp
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+U 4 1 67CB24B8
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+F 1 "PORT" H 3800 4850 30 0000 C CNN
+F 2 "" H 3800 4850 60 0000 C CNN
+F 3 "" H 3800 4850 60 0000 C CNN
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+ 0 -1 -1 0
+$EndComp
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+Connection ~ 3800 4550
+$Comp
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+U 1 1 67CB252E
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+F 1 "PORT" H 2600 2600 30 0000 C CNN
+F 2 "" H 2600 2600 60 0000 C CNN
+F 3 "" H 2600 2600 60 0000 C CNN
+ 1 2600 2600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
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+$Comp
+L d_inverter U2
+U 1 1 67CB259F
+P 2950 3850
+F 0 "U2" H 2950 3750 60 0000 C CNN
+F 1 "d_inverter" H 2950 4000 60 0000 C CNN
+F 2 "" H 3000 3800 60 0000 C CNN
+F 3 "" H 3000 3800 60 0000 C CNN
+ 1 2950 3850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
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+$Comp
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+F 3 "" H 3100 2950 60 0000 C CNN
+ 3 3100 2950
+ 1 0 0 -1
+$EndComp
+$Comp
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+$EndComp
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+F 1 "PORT" H 5550 2400 30 0000 C CNN
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+$Comp
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+$Comp
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+$Comp
+L mux X1
+U 1 1 67CB272E
+P 3800 2800
+F 0 "X1" H 3800 2800 60 0000 C CNN
+F 1 "mux" H 3800 2950 60 0000 C CNN
+F 2 "" H 3800 2800 60 0001 C CNN
+F 3 "" H 3800 2800 60 0001 C CNN
+ 1 3800 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L mux X2
+U 1 1 67CB276D
+P 3800 4050
+F 0 "X2" H 3800 4050 60 0000 C CNN
+F 1 "mux" H 3800 4200 60 0000 C CNN
+F 2 "" H 3800 4050 60 0001 C CNN
+F 3 "" H 3800 4050 60 0001 C CNN
+ 1 3800 4050
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC193/jk_mux.sub b/library/SubcircuitLibrary/74HC193/jk_mux.sub
new file mode 100644
index 00000000..72276878
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/jk_mux.sub
@@ -0,0 +1,17 @@
+* Subcircuit jk_mux
+.subckt jk_mux net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_
+* c:\fossee\esim\library\subcircuitlibrary\jk_mux\jk_mux.cir
+.include mux.sub
+* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ d_jkff
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+x1 net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad3_ net-_u3-pad1_ mux
+x2 net-_u1-pad4_ net-_u2-pad2_ net-_u1-pad2_ net-_u3-pad2_ mux
+a1 net-_u3-pad1_ net-_u3-pad2_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ u3
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_jkff, NgSpice Name: d_jkff
+.model u3 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends jk_mux \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC193/jk_mux_Previous_Values.xml b/library/SubcircuitLibrary/74HC193/jk_mux_Previous_Values.xml
new file mode 100644
index 00000000..fea1c735
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/jk_mux_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u3 name="type">d_jkff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for JK Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter Input Load (default=1.0e-12)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\mux</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\mux</field></x2></subcircuit></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC193/mux-cache.lib b/library/SubcircuitLibrary/74HC193/mux-cache.lib
new file mode 100644
index 00000000..86b09eb4
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux-cache.lib
@@ -0,0 +1,94 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC193/mux.cir b/library/SubcircuitLibrary/74HC193/mux.cir
new file mode 100644
index 00000000..211b8ef8
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux.cir
@@ -0,0 +1,15 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\mux\mux.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 3/7/2025 10:16:23 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_and
+U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U4-Pad3_ d_and
+U5 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad4_ d_or
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74HC193/mux.cir.out b/library/SubcircuitLibrary/74HC193/mux.cir.out
new file mode 100644
index 00000000..d23ed61f
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux.cir.out
@@ -0,0 +1,28 @@
+* c:\fossee\esim\library\subcircuitlibrary\mux\mux.cir
+
+* u3 net-_u1-pad1_ net-_u1-pad3_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+a2 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u4-pad3_ u4
+a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5
+a4 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC193/mux.pro b/library/SubcircuitLibrary/74HC193/mux.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC193/mux.sch b/library/SubcircuitLibrary/74HC193/mux.sch
new file mode 100644
index 00000000..22288031
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux.sch
@@ -0,0 +1,167 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U3
+U 1 1 67CB20E3
+P 5000 3050
+F 0 "U3" H 5000 3050 60 0000 C CNN
+F 1 "d_and" H 5050 3150 60 0000 C CNN
+F 2 "" H 5000 3050 60 0000 C CNN
+F 3 "" H 5000 3050 60 0000 C CNN
+ 1 5000 3050
+ 1 0 0 -1
+$EndComp
+$Comp
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+U 1 1 67CB217D
+P 5000 3800
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+F 2 "" H 5000 3800 60 0000 C CNN
+F 3 "" H 5000 3800 60 0000 C CNN
+ 1 5000 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U5
+U 1 1 67CB21A2
+P 6600 3400
+F 0 "U5" H 6600 3400 60 0000 C CNN
+F 1 "d_or" H 6600 3500 60 0000 C CNN
+F 2 "" H 6600 3400 60 0000 C CNN
+F 3 "" H 6600 3400 60 0000 C CNN
+ 1 6600 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5450 3000 6150 3000
+Wire Wire Line
+ 6150 3000 6150 3300
+Wire Wire Line
+ 5450 3750 6150 3750
+Wire Wire Line
+ 6150 3750 6150 3400
+$Comp
+L d_inverter U2
+U 1 1 67CB21FF
+P 3050 3800
+F 0 "U2" H 3050 3700 60 0000 C CNN
+F 1 "d_inverter" H 3050 3950 60 0000 C CNN
+F 2 "" H 3100 3750 60 0000 C CNN
+F 3 "" H 3100 3750 60 0000 C CNN
+ 1 3050 3800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3350 3800 4550 3800
+$Comp
+L PORT U1
+U 1 1 67CB22E7
+P 1700 2750
+F 0 "U1" H 1750 2850 30 0000 C CNN
+F 1 "PORT" H 1700 2750 30 0000 C CNN
+F 2 "" H 1700 2750 60 0000 C CNN
+F 3 "" H 1700 2750 60 0000 C CNN
+ 1 1700 2750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1950 2750 4550 2750
+Wire Wire Line
+ 4550 2750 4550 2950
+Wire Wire Line
+ 2750 3800 2750 2750
+Connection ~ 2750 2750
+$Comp
+L PORT U1
+U 3 1 67CB23D9
+P 4100 3050
+F 0 "U1" H 4150 3150 30 0000 C CNN
+F 1 "PORT" H 4100 3050 30 0000 C CNN
+F 2 "" H 4100 3050 60 0000 C CNN
+F 3 "" H 4100 3050 60 0000 C CNN
+ 3 4100 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 67CB2470
+P 4000 3700
+F 0 "U1" H 4050 3800 30 0000 C CNN
+F 1 "PORT" H 4000 3700 30 0000 C CNN
+F 2 "" H 4000 3700 60 0000 C CNN
+F 3 "" H 4000 3700 60 0000 C CNN
+ 2 4000 3700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4350 3050 4550 3050
+Wire Wire Line
+ 4250 3700 4550 3700
+$Comp
+L PORT U1
+U 4 1 67CB24FC
+P 7400 3350
+F 0 "U1" H 7450 3450 30 0000 C CNN
+F 1 "PORT" H 7400 3350 30 0000 C CNN
+F 2 "" H 7400 3350 60 0000 C CNN
+F 3 "" H 7400 3350 60 0000 C CNN
+ 4 7400 3350
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7150 3350 7050 3350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC193/mux.sub b/library/SubcircuitLibrary/74HC193/mux.sub
new file mode 100644
index 00000000..1c44b830
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux.sub
@@ -0,0 +1,22 @@
+* Subcircuit mux
+.subckt mux net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\fossee\esim\library\subcircuitlibrary\mux\mux.cir
+* u3 net-_u1-pad1_ net-_u1-pad3_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+a2 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u4-pad3_ u4
+a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5
+a4 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends mux \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC193/mux_Previous_Values.xml b/library/SubcircuitLibrary/74HC193/mux_Previous_Values.xml
new file mode 100644
index 00000000..5ef4ab5b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u3 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_or<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC193/mux_and-cache.lib b/library/SubcircuitLibrary/74HC193/mux_and-cache.lib
new file mode 100644
index 00000000..86b09eb4
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux_and-cache.lib
@@ -0,0 +1,94 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC193/mux_and.cir b/library/SubcircuitLibrary/74HC193/mux_and.cir
new file mode 100644
index 00000000..ea91ace2
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux_and.cir
@@ -0,0 +1,15 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\mux_and\mux_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 3/8/2025 2:11:42 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad4_ d_and
+U4 Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and
+U5 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+
+.end
diff --git a/library/SubcircuitLibrary/74HC193/mux_and.cir.out b/library/SubcircuitLibrary/74HC193/mux_and.cir.out
new file mode 100644
index 00000000..73616137
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux_and.cir.out
@@ -0,0 +1,28 @@
+* c:\fossee\esim\library\subcircuitlibrary\mux_and\mux_and.cir
+
+* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ d_and
+* u4 net-_u2-pad2_ net-_u1-pad3_ net-_u1-pad5_ d_and
+* u5 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad4_ u3
+a2 [net-_u2-pad2_ net-_u1-pad3_ ] net-_u1-pad5_ u4
+a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u1-pad6_ u5
+a4 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC193/mux_and.pro b/library/SubcircuitLibrary/74HC193/mux_and.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux_and.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC193/mux_and.sch b/library/SubcircuitLibrary/74HC193/mux_and.sch
new file mode 100644
index 00000000..8d98a5e5
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux_and.sch
@@ -0,0 +1,193 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U3
+U 1 1 67CC00D5
+P 4500 3000
+F 0 "U3" H 4500 3000 60 0000 C CNN
+F 1 "d_and" H 4550 3100 60 0000 C CNN
+F 2 "" H 4500 3000 60 0000 C CNN
+F 3 "" H 4500 3000 60 0000 C CNN
+ 1 4500 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 67CC0132
+P 4500 4050
+F 0 "U4" H 4500 4050 60 0000 C CNN
+F 1 "d_and" H 4550 4150 60 0000 C CNN
+F 2 "" H 4500 4050 60 0000 C CNN
+F 3 "" H 4500 4050 60 0000 C CNN
+ 1 4500 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U5
+U 1 1 67CC0167
+P 6400 3450
+F 0 "U5" H 6400 3450 60 0000 C CNN
+F 1 "d_or" H 6400 3550 60 0000 C CNN
+F 2 "" H 6400 3450 60 0000 C CNN
+F 3 "" H 6400 3450 60 0000 C CNN
+ 1 6400 3450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4950 2950 5950 2950
+Wire Wire Line
+ 5950 2950 5950 3350
+Wire Wire Line
+ 4950 4000 6650 4000
+Wire Wire Line
+ 5950 4000 5950 3450
+Wire Wire Line
+ 6850 3400 7200 3400
+$Comp
+L PORT U1
+U 1 1 67CC01A6
+P 2000 2900
+F 0 "U1" H 2050 3000 30 0000 C CNN
+F 1 "PORT" H 2000 2900 30 0000 C CNN
+F 2 "" H 2000 2900 60 0000 C CNN
+F 3 "" H 2000 2900 60 0000 C CNN
+ 1 2000 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 67CC0221
+P 3200 3000
+F 0 "U1" H 3250 3100 30 0000 C CNN
+F 1 "PORT" H 3200 3000 30 0000 C CNN
+F 2 "" H 3200 3000 60 0000 C CNN
+F 3 "" H 3200 3000 60 0000 C CNN
+ 2 3200 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 67CC0296
+P 3350 4050
+F 0 "U1" H 3400 4150 30 0000 C CNN
+F 1 "PORT" H 3350 4050 30 0000 C CNN
+F 2 "" H 3350 4050 60 0000 C CNN
+F 3 "" H 3350 4050 60 0000 C CNN
+ 3 3350 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 67CC0355
+P 7450 3400
+F 0 "U1" H 7500 3500 30 0000 C CNN
+F 1 "PORT" H 7450 3400 30 0000 C CNN
+F 2 "" H 7450 3400 60 0000 C CNN
+F 3 "" H 7450 3400 60 0000 C CNN
+ 6 7450 3400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 67CC03E0
+P 6850 3000
+F 0 "U1" H 6900 3100 30 0000 C CNN
+F 1 "PORT" H 6850 3000 30 0000 C CNN
+F 2 "" H 6850 3000 60 0000 C CNN
+F 3 "" H 6850 3000 60 0000 C CNN
+ 4 6850 3000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 67CC044B
+P 6900 4000
+F 0 "U1" H 6950 4100 30 0000 C CNN
+F 1 "PORT" H 6900 4000 30 0000 C CNN
+F 2 "" H 6900 4000 60 0000 C CNN
+F 3 "" H 6900 4000 60 0000 C CNN
+ 5 6900 4000
+ -1 0 0 1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 67CC04A4
+P 2800 3950
+F 0 "U2" H 2800 3850 60 0000 C CNN
+F 1 "d_inverter" H 2800 4100 60 0000 C CNN
+F 2 "" H 2850 3900 60 0000 C CNN
+F 3 "" H 2850 3900 60 0000 C CNN
+ 1 2800 3950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2250 2900 2250 3950
+Wire Wire Line
+ 2250 3950 2500 3950
+Wire Wire Line
+ 3100 3950 4050 3950
+Wire Wire Line
+ 3600 4050 4050 4050
+Connection ~ 2250 2900
+Wire Wire Line
+ 2250 2900 4050 2900
+Wire Wire Line
+ 3450 3000 4050 3000
+Wire Wire Line
+ 6600 3000 5950 3000
+Connection ~ 5950 3000
+Connection ~ 5950 4000
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC193/mux_and.sub b/library/SubcircuitLibrary/74HC193/mux_and.sub
new file mode 100644
index 00000000..9ef9fc76
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux_and.sub
@@ -0,0 +1,22 @@
+* Subcircuit mux_and
+.subckt mux_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
+* c:\fossee\esim\library\subcircuitlibrary\mux_and\mux_and.cir
+* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ d_and
+* u4 net-_u2-pad2_ net-_u1-pad3_ net-_u1-pad5_ d_and
+* u5 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ d_or
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad4_ u3
+a2 [net-_u2-pad2_ net-_u1-pad3_ ] net-_u1-pad5_ u4
+a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u1-pad6_ u5
+a4 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends mux_and \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC193/mux_and_Previous_Values.xml b/library/SubcircuitLibrary/74HC193/mux_and_Previous_Values.xml
new file mode 100644
index 00000000..5ef4ab5b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/mux_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u3 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_or<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-06-30 17:01:56 +0000