74HC147N as a 10-to-4 Line Priority Encoder

7 files changed, 642 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test-cache.lib b/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test-cache.lib
new file mode 100644
index 00000000..8713095f
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test-cache.lib
@@ -0,0 +1,208 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_OR
+#
+DEF 4_OR X 0 40 Y Y 1 F N
+F0 "X" 150 -100 60 H V C CNN
+F1 "4_OR" 150 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
+A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
+A -30 -99 393 627 146 0 1 0 N 150 250 350 0
+P 2 0 1 0 -200 -250 150 -250 N
+P 2 0 1 0 -200 250 150 250 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X in4 4 -350 -150 200 R 50 50 1 1 I
+X out 5 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test.cir b/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test.cir
new file mode 100644
index 00000000..7c2d3f3b
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test.cir
@@ -0,0 +1,53 @@
+* C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4bitadder_2nd_test\4bitadder_2nd_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/14/25 19:59:00
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  /Cin Net-_U2-Pad2_ d_inverter		
+U4  /b1 /a1 Net-_U10-Pad1_ d_nor		
+U8  /b1 /a1 Net-_U7-Pad1_ d_nand		
+U12  /b2 /a2 Net-_U12-Pad3_ d_nor		
+U15  /b2 /a2 Net-_U14-Pad1_ d_nand		
+U18  /b3 /a3 Net-_U18-Pad3_ d_nor		
+U21  /b3 /a3 Net-_U21-Pad3_ d_nand		
+U25  /b4 /a4 Net-_U25-Pad3_ d_nor		
+U26  /b4 /a4 Net-_U26-Pad3_ d_nand		
+U1  /Cin /a1 /s1 /b1 /s2 /a2 /b2 /a3 /b3 /s3 /a4 /b4 /s4 /cout PORT		
+U3  Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter		
+U6  Net-_U10-Pad1_ Net-_U6-Pad2_ d_inverter		
+U7  Net-_U7-Pad1_ Net-_U6-Pad2_ Net-_U5-Pad1_ d_and		
+U5  Net-_U5-Pad1_ Net-_U3-Pad2_ /s1 d_xor		
+U9  Net-_U7-Pad1_ Net-_U2-Pad2_ Net-_U10-Pad2_ d_and		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor		
+U13  Net-_U12-Pad3_ Net-_U13-Pad2_ d_inverter		
+U14  Net-_U14-Pad1_ Net-_U13-Pad2_ Net-_U11-Pad1_ d_and		
+U11  Net-_U11-Pad1_ Net-_U10-Pad3_ /s2 d_xor		
+X1  Net-_U14-Pad1_ Net-_U7-Pad1_ Net-_U2-Pad2_ Net-_U16-Pad2_ 3_and		
+U17  Net-_U10-Pad1_ Net-_U14-Pad1_ Net-_U16-Pad1_ d_and		
+U16  Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_or		
+U20  Net-_U12-Pad3_ Net-_U16-Pad3_ Net-_U19-Pad1_ d_or		
+U19  Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter		
+U23  Net-_U18-Pad3_ Net-_U23-Pad2_ d_inverter		
+U24  Net-_U21-Pad3_ Net-_U23-Pad2_ Net-_U22-Pad1_ d_and		
+U22  Net-_U22-Pad1_ Net-_U19-Pad2_ /s3 d_xor		
+X2  Net-_U21-Pad3_ Net-_U14-Pad1_ Net-_U7-Pad1_ Net-_U2-Pad2_ Net-_X2-Pad5_ 4_and		
+X3  Net-_U10-Pad1_ Net-_U21-Pad3_ Net-_U14-Pad1_ Net-_X3-Pad4_ 3_and		
+U28  Net-_U12-Pad3_ Net-_U21-Pad3_ Net-_U28-Pad3_ d_and		
+X4  Net-_U18-Pad3_ Net-_U28-Pad3_ Net-_X3-Pad4_ Net-_X2-Pad5_ Net-_U27-Pad1_ 4_OR		
+U27  Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter		
+U29  Net-_U29-Pad1_ Net-_U27-Pad2_ /s4 d_xor		
+U30  Net-_U25-Pad3_ Net-_U30-Pad2_ d_inverter		
+U31  Net-_U26-Pad3_ Net-_U30-Pad2_ Net-_U29-Pad1_ d_and		
+X5  Net-_U14-Pad1_ Net-_U7-Pad1_ Net-_U2-Pad2_ Net-_X5-Pad4_ 3_and		
+X6  Net-_U26-Pad3_ Net-_U21-Pad3_ Net-_X5-Pad4_ Net-_X6-Pad4_ 3_and		
+X7  Net-_U10-Pad1_ Net-_U26-Pad3_ Net-_U21-Pad3_ Net-_U14-Pad1_ Net-_X7-Pad5_ 4_and		
+X8  Net-_U12-Pad3_ Net-_U26-Pad3_ Net-_U21-Pad3_ Net-_X8-Pad4_ 3_and		
+U32  Net-_U18-Pad3_ Net-_U26-Pad3_ Net-_U32-Pad3_ d_and		
+X9  Net-_U32-Pad3_ Net-_X8-Pad4_ Net-_X7-Pad5_ Net-_X6-Pad4_ Net-_U33-Pad2_ 4_OR		
+U33  Net-_U25-Pad3_ Net-_U33-Pad2_ Net-_U33-Pad3_ d_or		
+U34  Net-_U33-Pad3_ /cout d_inverter		
+
+.end
diff --git a/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test.cir.out b/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test.cir.out
new file mode 100644
index 00000000..699ebf24
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test.cir.out
@@ -0,0 +1,156 @@
+* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\4bitadder_2nd_test\4bitadder_2nd_test.cir
+
+.include 4_OR.sub
+.include 3_and.sub
+.include 4_and.sub
+* u2  /cin net-_u2-pad2_ d_inverter
+* u4  /b1 /a1 net-_u10-pad1_ d_nor
+* u8  /b1 /a1 net-_u7-pad1_ d_nand
+* u12  /b2 /a2 net-_u12-pad3_ d_nor
+* u15  /b2 /a2 net-_u14-pad1_ d_nand
+* u18  /b3 /a3 net-_u18-pad3_ d_nor
+* u21  /b3 /a3 net-_u21-pad3_ d_nand
+* u25  /b4 /a4 net-_u25-pad3_ d_nor
+* u26  /b4 /a4 net-_u26-pad3_ d_nand
+* u1  /cin /a1 /s1 /b1 /s2 /a2 /b2 /a3 /b3 /s3 /a4 /b4 /s4 /cout port
+* u3  net-_u2-pad2_ net-_u3-pad2_ d_inverter
+* u6  net-_u10-pad1_ net-_u6-pad2_ d_inverter
+* u7  net-_u7-pad1_ net-_u6-pad2_ net-_u5-pad1_ d_and
+* u5  net-_u5-pad1_ net-_u3-pad2_ /s1 d_xor
+* u9  net-_u7-pad1_ net-_u2-pad2_ net-_u10-pad2_ d_and
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u13  net-_u12-pad3_ net-_u13-pad2_ d_inverter
+* u14  net-_u14-pad1_ net-_u13-pad2_ net-_u11-pad1_ d_and
+* u11  net-_u11-pad1_ net-_u10-pad3_ /s2 d_xor
+x1 net-_u14-pad1_ net-_u7-pad1_ net-_u2-pad2_ net-_u16-pad2_ 3_and
+* u17  net-_u10-pad1_ net-_u14-pad1_ net-_u16-pad1_ d_and
+* u16  net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_or
+* u20  net-_u12-pad3_ net-_u16-pad3_ net-_u19-pad1_ d_or
+* u19  net-_u19-pad1_ net-_u19-pad2_ d_inverter
+* u23  net-_u18-pad3_ net-_u23-pad2_ d_inverter
+* u24  net-_u21-pad3_ net-_u23-pad2_ net-_u22-pad1_ d_and
+* u22  net-_u22-pad1_ net-_u19-pad2_ /s3 d_xor
+x2 net-_u21-pad3_ net-_u14-pad1_ net-_u7-pad1_ net-_u2-pad2_ net-_x2-pad5_ 4_and
+x3 net-_u10-pad1_ net-_u21-pad3_ net-_u14-pad1_ net-_x3-pad4_ 3_and
+* u28  net-_u12-pad3_ net-_u21-pad3_ net-_u28-pad3_ d_and
+x4 net-_u18-pad3_ net-_u28-pad3_ net-_x3-pad4_ net-_x2-pad5_ net-_u27-pad1_ 4_OR
+* u27  net-_u27-pad1_ net-_u27-pad2_ d_inverter
+* u29  net-_u29-pad1_ net-_u27-pad2_ /s4 d_xor
+* u30  net-_u25-pad3_ net-_u30-pad2_ d_inverter
+* u31  net-_u26-pad3_ net-_u30-pad2_ net-_u29-pad1_ d_and
+x5 net-_u14-pad1_ net-_u7-pad1_ net-_u2-pad2_ net-_x5-pad4_ 3_and
+x6 net-_u26-pad3_ net-_u21-pad3_ net-_x5-pad4_ net-_x6-pad4_ 3_and
+x7 net-_u10-pad1_ net-_u26-pad3_ net-_u21-pad3_ net-_u14-pad1_ net-_x7-pad5_ 4_and
+x8 net-_u12-pad3_ net-_u26-pad3_ net-_u21-pad3_ net-_x8-pad4_ 3_and
+* u32  net-_u18-pad3_ net-_u26-pad3_ net-_u32-pad3_ d_and
+x9 net-_u32-pad3_ net-_x8-pad4_ net-_x7-pad5_ net-_x6-pad4_ net-_u33-pad2_ 4_OR
+* u33  net-_u25-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or
+* u34  net-_u33-pad3_ /cout d_inverter
+a1 /cin net-_u2-pad2_ u2
+a2 [/b1 /a1 ] net-_u10-pad1_ u4
+a3 [/b1 /a1 ] net-_u7-pad1_ u8
+a4 [/b2 /a2 ] net-_u12-pad3_ u12
+a5 [/b2 /a2 ] net-_u14-pad1_ u15
+a6 [/b3 /a3 ] net-_u18-pad3_ u18
+a7 [/b3 /a3 ] net-_u21-pad3_ u21
+a8 [/b4 /a4 ] net-_u25-pad3_ u25
+a9 [/b4 /a4 ] net-_u26-pad3_ u26
+a10 net-_u2-pad2_ net-_u3-pad2_ u3
+a11 net-_u10-pad1_ net-_u6-pad2_ u6
+a12 [net-_u7-pad1_ net-_u6-pad2_ ] net-_u5-pad1_ u7
+a13 [net-_u5-pad1_ net-_u3-pad2_ ] /s1 u5
+a14 [net-_u7-pad1_ net-_u2-pad2_ ] net-_u10-pad2_ u9
+a15 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a16 net-_u12-pad3_ net-_u13-pad2_ u13
+a17 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u11-pad1_ u14
+a18 [net-_u11-pad1_ net-_u10-pad3_ ] /s2 u11
+a19 [net-_u10-pad1_ net-_u14-pad1_ ] net-_u16-pad1_ u17
+a20 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a21 [net-_u12-pad3_ net-_u16-pad3_ ] net-_u19-pad1_ u20
+a22 net-_u19-pad1_ net-_u19-pad2_ u19
+a23 net-_u18-pad3_ net-_u23-pad2_ u23
+a24 [net-_u21-pad3_ net-_u23-pad2_ ] net-_u22-pad1_ u24
+a25 [net-_u22-pad1_ net-_u19-pad2_ ] /s3 u22
+a26 [net-_u12-pad3_ net-_u21-pad3_ ] net-_u28-pad3_ u28
+a27 net-_u27-pad1_ net-_u27-pad2_ u27
+a28 [net-_u29-pad1_ net-_u27-pad2_ ] /s4 u29
+a29 net-_u25-pad3_ net-_u30-pad2_ u30
+a30 [net-_u26-pad3_ net-_u30-pad2_ ] net-_u29-pad1_ u31
+a31 [net-_u18-pad3_ net-_u26-pad3_ ] net-_u32-pad3_ u32
+a32 [net-_u25-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33
+a33 net-_u33-pad3_ /cout u34
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u22 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u29 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test.pro b/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test.sub b/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test.sub
new file mode 100644
index 00000000..cea89486
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test.sub
@@ -0,0 +1,150 @@
+* Subcircuit 4bitadder_2nd_test
+.subckt 4bitadder_2nd_test /cin /a1 /s1 /b1 /s2 /a2 /b2 /a3 /b3 /s3 /a4 /b4 /s4 /cout 
+* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\4bitadder_2nd_test\4bitadder_2nd_test.cir
+.include 4_OR.sub
+.include 3_and.sub
+.include 4_and.sub
+* u2  /cin net-_u2-pad2_ d_inverter
+* u4  /b1 /a1 net-_u10-pad1_ d_nor
+* u8  /b1 /a1 net-_u7-pad1_ d_nand
+* u12  /b2 /a2 net-_u12-pad3_ d_nor
+* u15  /b2 /a2 net-_u14-pad1_ d_nand
+* u18  /b3 /a3 net-_u18-pad3_ d_nor
+* u21  /b3 /a3 net-_u21-pad3_ d_nand
+* u25  /b4 /a4 net-_u25-pad3_ d_nor
+* u26  /b4 /a4 net-_u26-pad3_ d_nand
+* u3  net-_u2-pad2_ net-_u3-pad2_ d_inverter
+* u6  net-_u10-pad1_ net-_u6-pad2_ d_inverter
+* u7  net-_u7-pad1_ net-_u6-pad2_ net-_u5-pad1_ d_and
+* u5  net-_u5-pad1_ net-_u3-pad2_ /s1 d_xor
+* u9  net-_u7-pad1_ net-_u2-pad2_ net-_u10-pad2_ d_and
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u13  net-_u12-pad3_ net-_u13-pad2_ d_inverter
+* u14  net-_u14-pad1_ net-_u13-pad2_ net-_u11-pad1_ d_and
+* u11  net-_u11-pad1_ net-_u10-pad3_ /s2 d_xor
+x1 net-_u14-pad1_ net-_u7-pad1_ net-_u2-pad2_ net-_u16-pad2_ 3_and
+* u17  net-_u10-pad1_ net-_u14-pad1_ net-_u16-pad1_ d_and
+* u16  net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_or
+* u20  net-_u12-pad3_ net-_u16-pad3_ net-_u19-pad1_ d_or
+* u19  net-_u19-pad1_ net-_u19-pad2_ d_inverter
+* u23  net-_u18-pad3_ net-_u23-pad2_ d_inverter
+* u24  net-_u21-pad3_ net-_u23-pad2_ net-_u22-pad1_ d_and
+* u22  net-_u22-pad1_ net-_u19-pad2_ /s3 d_xor
+x2 net-_u21-pad3_ net-_u14-pad1_ net-_u7-pad1_ net-_u2-pad2_ net-_x2-pad5_ 4_and
+x3 net-_u10-pad1_ net-_u21-pad3_ net-_u14-pad1_ net-_x3-pad4_ 3_and
+* u28  net-_u12-pad3_ net-_u21-pad3_ net-_u28-pad3_ d_and
+x4 net-_u18-pad3_ net-_u28-pad3_ net-_x3-pad4_ net-_x2-pad5_ net-_u27-pad1_ 4_OR
+* u27  net-_u27-pad1_ net-_u27-pad2_ d_inverter
+* u29  net-_u29-pad1_ net-_u27-pad2_ /s4 d_xor
+* u30  net-_u25-pad3_ net-_u30-pad2_ d_inverter
+* u31  net-_u26-pad3_ net-_u30-pad2_ net-_u29-pad1_ d_and
+x5 net-_u14-pad1_ net-_u7-pad1_ net-_u2-pad2_ net-_x5-pad4_ 3_and
+x6 net-_u26-pad3_ net-_u21-pad3_ net-_x5-pad4_ net-_x6-pad4_ 3_and
+x7 net-_u10-pad1_ net-_u26-pad3_ net-_u21-pad3_ net-_u14-pad1_ net-_x7-pad5_ 4_and
+x8 net-_u12-pad3_ net-_u26-pad3_ net-_u21-pad3_ net-_x8-pad4_ 3_and
+* u32  net-_u18-pad3_ net-_u26-pad3_ net-_u32-pad3_ d_and
+x9 net-_u32-pad3_ net-_x8-pad4_ net-_x7-pad5_ net-_x6-pad4_ net-_u33-pad2_ 4_OR
+* u33  net-_u25-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or
+* u34  net-_u33-pad3_ /cout d_inverter
+a1 /cin net-_u2-pad2_ u2
+a2 [/b1 /a1 ] net-_u10-pad1_ u4
+a3 [/b1 /a1 ] net-_u7-pad1_ u8
+a4 [/b2 /a2 ] net-_u12-pad3_ u12
+a5 [/b2 /a2 ] net-_u14-pad1_ u15
+a6 [/b3 /a3 ] net-_u18-pad3_ u18
+a7 [/b3 /a3 ] net-_u21-pad3_ u21
+a8 [/b4 /a4 ] net-_u25-pad3_ u25
+a9 [/b4 /a4 ] net-_u26-pad3_ u26
+a10 net-_u2-pad2_ net-_u3-pad2_ u3
+a11 net-_u10-pad1_ net-_u6-pad2_ u6
+a12 [net-_u7-pad1_ net-_u6-pad2_ ] net-_u5-pad1_ u7
+a13 [net-_u5-pad1_ net-_u3-pad2_ ] /s1 u5
+a14 [net-_u7-pad1_ net-_u2-pad2_ ] net-_u10-pad2_ u9
+a15 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a16 net-_u12-pad3_ net-_u13-pad2_ u13
+a17 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u11-pad1_ u14
+a18 [net-_u11-pad1_ net-_u10-pad3_ ] /s2 u11
+a19 [net-_u10-pad1_ net-_u14-pad1_ ] net-_u16-pad1_ u17
+a20 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a21 [net-_u12-pad3_ net-_u16-pad3_ ] net-_u19-pad1_ u20
+a22 net-_u19-pad1_ net-_u19-pad2_ u19
+a23 net-_u18-pad3_ net-_u23-pad2_ u23
+a24 [net-_u21-pad3_ net-_u23-pad2_ ] net-_u22-pad1_ u24
+a25 [net-_u22-pad1_ net-_u19-pad2_ ] /s3 u22
+a26 [net-_u12-pad3_ net-_u21-pad3_ ] net-_u28-pad3_ u28
+a27 net-_u27-pad1_ net-_u27-pad2_ u27
+a28 [net-_u29-pad1_ net-_u27-pad2_ ] /s4 u29
+a29 net-_u25-pad3_ net-_u30-pad2_ u30
+a30 [net-_u26-pad3_ net-_u30-pad2_ ] net-_u29-pad1_ u31
+a31 [net-_u18-pad3_ net-_u26-pad3_ ] net-_u32-pad3_ u32
+a32 [net-_u25-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33
+a33 net-_u33-pad3_ /cout u34
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u22 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u29 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 4bitadder_2nd_test
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test_Previous_Values.xml b/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test_Previous_Values.xml
new file mode 100644
index 00000000..a7970f60
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS283/4bitadder_2nd_test_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u4 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u8 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u8><u12 name="type">d_nor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u12><u15 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u15><u18 name="type">d_nor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u18><u21 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u21><u25 name="type">d_nor<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u26><u3 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u3><u6 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u7><u5 name="type">d_xor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u5><u9 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_nor<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u10><u13 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u14><u11 name="type">d_xor<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u11><u17 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u17><u16 name="type">d_or<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u16><u20 name="type">d_or<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u20><u19 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u19><u23 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_and<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u24><u22 name="type">d_xor<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u22><u28 name="type">d_and<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u28><u27 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u27><u29 name="type">d_xor<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_and<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_and<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u32><u33 name="type">d_or<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u33><u34 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u34></model><devicemodel /><subcircuit><x1><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x3><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x4><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x4><x5><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x6><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x7><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x7><x8><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x9><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x9></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LS283/analysis b/library/SubcircuitLibrary/74LS283/analysis
new file mode 100644
index 00000000..2aa74f3d
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS283/analysis
@@ -0,0 +1 @@
+.tran 0.001e-00 16e-00 0e-00
\ No newline at end of file