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| author | fahim | 2015-08-05 13:52:57 +0530 |
|---|---|---|
| committer | fahim | 2015-08-05 13:52:57 +0530 |
| commit | df569f79a7ee495291324e07d99af990104e3db2 (patch) | |
| tree | a005c682aa78b58b7dd5bb693c415eff9c04d04b | |
| parent | c4971ed867af4a970a3cd1c23825adee5073372e (diff) | |
| download | eSim-df569f79a7ee495291324e07d99af990104e3db2.tar.gz eSim-df569f79a7ee495291324e07d99af990104e3db2.tar.bz2 eSim-df569f79a7ee495291324e07d99af990104e3db2.zip | |
Subject: Added eSim Examples
Description: Added eSim Examples
178 files changed, 18589 insertions, 0 deletions
diff --git a/Examples/4_bit_JK_ff/4_bit_JK_ff-cache.lib b/Examples/4_bit_JK_ff/4_bit_JK_ff-cache.lib new file mode 100644 index 00000000..e6d499b3 --- /dev/null +++ b/Examples/4_bit_JK_ff/4_bit_JK_ff-cache.lib @@ -0,0 +1,169 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_jkff +# +DEF d_jkff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_jkff" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X J 1 -800 400 200 R 50 50 1 1 I +X K 2 -800 -450 200 R 50 50 1 1 I +X Clk 3 -800 0 200 R 50 50 1 1 I C +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_4 +# +DEF dac_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/4_bit_JK_ff/4_bit_JK_ff.bak b/Examples/4_bit_JK_ff/4_bit_JK_ff.bak new file mode 100644 index 00000000..23fb77ae --- /dev/null +++ b/Examples/4_bit_JK_ff/4_bit_JK_ff.bak @@ -0,0 +1,687 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:measurementSpice +LIBS:sourcesSpice +LIBS:4_bit_JK_ff-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_jkff U3 +U 1 1 5548DDEE +P 2750 3650 +F 0 "U3" H 2750 3650 60 0000 C CNN +F 1 "d_jkff" H 2800 3800 60 0000 C CNN +F 2 "" H 2750 3650 60 0000 C CNN +F 3 "" H 2750 3650 60 0000 C CNN + 1 2750 3650 + 1 0 0 -1 +$EndComp +$Comp +L dc v1 +U 1 1 5548DFB1 +P 1100 5600 +F 0 "v1" H 900 5700 60 0000 C CNN +F 1 "dc" H 900 5550 60 0000 C CNN +F 2 "R1" H 800 5600 60 0000 C CNN +F 3 "" H 1100 5600 60 0000 C CNN + 1 1100 5600 + 0 1 1 0 +$EndComp +$Comp +L dc v3 +U 1 1 5548E056 +P 1100 6800 +F 0 "v3" H 900 6900 60 0000 C CNN +F 1 "dc" H 900 6750 60 0000 C CNN +F 2 "R1" H 800 6800 60 0000 C CNN +F 3 "" H 1100 6800 60 0000 C CNN + 1 1100 6800 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 5548E561 +P 650 7300 +F 0 "#PWR01" H 650 7050 50 0001 C CNN +F 1 "GND" H 650 7150 50 0000 C CNN +F 2 "" H 650 7300 60 0000 C CNN +F 3 "" H 650 7300 60 0000 C CNN + 1 650 7300 + 1 0 0 -1 +$EndComp +$Comp +L dc v4 +U 1 1 554A0BE0 +P 3550 5950 +F 0 "v4" H 3350 6050 60 0000 C CNN +F 1 "0" H 3350 5900 60 0000 C CNN +F 2 "R1" H 3250 5950 60 0000 C CNN +F 3 "" H 3550 5950 60 0000 C CNN + 1 3550 5950 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 554A0D14 +P 1250 5400 +F 0 "#PWR02" H 1250 5150 50 0001 C CNN +F 1 "GND" H 1250 5250 50 0000 C CNN +F 2 "" H 1250 5400 60 0000 C CNN +F 3 "" H 1250 5400 60 0000 C CNN + 1 1250 5400 + 1 0 0 -1 +$EndComp +$Comp +L pulse v2 +U 1 1 554B519B +P 1100 6300 +F 0 "v2" H 900 6400 60 0000 C CNN +F 1 "pulse" H 900 6250 60 0000 C CNN +F 2 "R1" H 800 6300 60 0000 C CNN +F 3 "" H 1100 6300 60 0000 C CNN + 1 1100 6300 + 0 1 1 0 +$EndComp +$Comp +L d_jkff U5 +U 1 1 554B6244 +P 5150 3650 +F 0 "U5" H 5150 3650 60 0000 C CNN +F 1 "d_jkff" H 5200 3800 60 0000 C CNN +F 2 "" H 5150 3650 60 0000 C CNN +F 3 "" H 5150 3650 60 0000 C CNN + 1 5150 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_jkff U7 +U 1 1 554B6332 +P 7450 3650 +F 0 "U7" H 7450 3650 60 0000 C CNN +F 1 "d_jkff" H 7500 3800 60 0000 C CNN +F 2 "" H 7450 3650 60 0000 C CNN +F 3 "" H 7450 3650 60 0000 C CNN + 1 7450 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_jkff U10 +U 1 1 554B6384 +P 9650 3650 +F 0 "U10" H 9650 3650 60 0000 C CNN +F 1 "d_jkff" H 9700 3800 60 0000 C CNN +F 2 "" H 9650 3650 60 0000 C CNN +F 3 "" H 9650 3650 60 0000 C CNN + 1 9650 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 554B66D8 +P 6550 4750 +F 0 "U6" H 6550 4750 60 0000 C CNN +F 1 "d_and" H 6600 4850 60 0000 C CNN +F 2 "" H 6550 4750 60 0000 C CNN +F 3 "" H 6550 4750 60 0000 C CNN + 1 6550 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 554B6711 +P 8500 4800 +F 0 "U8" H 8500 4800 60 0000 C CNN +F 1 "d_and" H 8550 4900 60 0000 C CNN +F 2 "" H 8500 4800 60 0000 C CNN +F 3 "" H 8500 4800 60 0000 C CNN + 1 8500 4800 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_4 U4 +U 1 1 554B701C +P 4900 6150 +F 0 "U4" H 4900 6150 60 0000 C CNN +F 1 "adc_bridge_4" H 4900 6450 60 0000 C CNN +F 2 "" H 4900 6150 60 0000 C CNN +F 3 "" H 4900 6150 60 0000 C CNN + 1 4900 6150 + 1 0 0 -1 +$EndComp +$Comp +L dc v10 +U 1 1 554B724D +P 3500 6400 +F 0 "v10" H 3300 6500 60 0000 C CNN +F 1 "0" H 3300 6350 60 0000 C CNN +F 2 "R1" H 3200 6400 60 0000 C CNN +F 3 "" H 3500 6400 60 0000 C CNN + 1 3500 6400 + 0 1 1 0 +$EndComp +$Comp +L dc v11 +U 1 1 554B72DB +P 3500 6700 +F 0 "v11" H 3300 6800 60 0000 C CNN +F 1 "0" H 3300 6650 60 0000 C CNN +F 2 "R1" H 3200 6700 60 0000 C CNN +F 3 "" H 3500 6700 60 0000 C CNN + 1 3500 6700 + 0 1 1 0 +$EndComp +$Comp +L dc v9 +U 1 1 554B7321 +P 3500 5450 +F 0 "v9" H 3300 5550 60 0000 C CNN +F 1 "0" H 3300 5400 60 0000 C CNN +F 2 "R1" H 3200 5450 60 0000 C CNN +F 3 "" H 3500 5450 60 0000 C CNN + 1 3500 5450 + 0 1 1 0 +$EndComp +$Comp +L dc v8 +U 1 1 554B79B1 +P 2200 1200 +F 0 "v8" H 2000 1300 60 0000 C CNN +F 1 "0" H 2000 1150 60 0000 C CNN +F 2 "R1" H 1900 1200 60 0000 C CNN +F 3 "" H 2200 1200 60 0000 C CNN + 1 2200 1200 + 0 1 1 0 +$EndComp +$Comp +L adc_bridge_4 U2 +U 1 1 554B79B7 +P 3550 1400 +F 0 "U2" H 3550 1400 60 0000 C CNN +F 1 "adc_bridge_4" H 3550 1700 60 0000 C CNN +F 2 "" H 3550 1400 60 0000 C CNN +F 3 "" H 3550 1400 60 0000 C CNN + 1 3550 1400 + 1 0 0 -1 +$EndComp +$Comp +L dc v6 +U 1 1 554B79BD +P 2150 1650 +F 0 "v6" H 1950 1750 60 0000 C CNN +F 1 "0" H 1950 1600 60 0000 C CNN +F 2 "R1" H 1850 1650 60 0000 C CNN +F 3 "" H 2150 1650 60 0000 C CNN + 1 2150 1650 + 0 1 1 0 +$EndComp +$Comp +L dc v7 +U 1 1 554B79C3 +P 2150 1950 +F 0 "v7" H 1950 2050 60 0000 C CNN +F 1 "0" H 1950 1900 60 0000 C CNN +F 2 "R1" H 1850 1950 60 0000 C CNN +F 3 "" H 2150 1950 60 0000 C CNN + 1 2150 1950 + 0 1 1 0 +$EndComp +$Comp +L dc v5 +U 1 1 554B79C9 +P 2150 700 +F 0 "v5" H 1950 800 60 0000 C CNN +F 1 "0" H 1950 650 60 0000 C CNN +F 2 "R1" H 1850 700 60 0000 C CNN +F 3 "" H 2150 700 60 0000 C CNN + 1 2150 700 + 0 1 1 0 +$EndComp +Wire Wire Line + 650 5600 550 5600 +Wire Wire Line + 550 5600 550 7150 +Wire Wire Line + 550 7150 650 7150 +Wire Wire Line + 650 7150 650 7300 +Wire Wire Line + 650 6300 550 6300 +Connection ~ 550 6300 +Wire Wire Line + 650 6800 550 6800 +Connection ~ 550 6800 +Wire Wire Line + 1250 5300 1250 5400 +Wire Wire Line + 5950 4100 6050 4100 +Wire Wire Line + 6050 4100 6050 4650 +Wire Wire Line + 6050 4650 6100 4650 +Wire Wire Line + 8250 4100 8300 4100 +Wire Wire Line + 8300 4100 8300 4500 +Wire Wire Line + 8300 4500 8050 4500 +Wire Wire Line + 8050 4500 8050 4700 +Wire Wire Line + 7000 4700 7850 4700 +Wire Wire Line + 7850 4700 7850 4800 +Wire Wire Line + 7850 4800 8050 4800 +Wire Wire Line + 6550 3250 6550 4500 +Wire Wire Line + 6550 4500 7300 4500 +Wire Wire Line + 7300 4500 7300 4700 +Connection ~ 7300 4700 +Wire Wire Line + 4200 3250 4200 4750 +Wire Wire Line + 4200 4750 6100 4750 +Wire Wire Line + 8650 3250 8650 4500 +Wire Wire Line + 8650 4500 8950 4500 +Wire Wire Line + 8950 4500 8950 4750 +Wire Wire Line + 8850 4100 8650 4100 +Connection ~ 8650 4100 +Wire Wire Line + 6650 4100 6550 4100 +Connection ~ 6550 4100 +Wire Wire Line + 3550 4100 4350 4100 +Connection ~ 4200 4100 +Wire Wire Line + 4350 3250 4200 3250 +Wire Wire Line + 6650 3250 6550 3250 +Wire Wire Line + 8850 3250 8650 3250 +Wire Wire Line + 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1400 +Wire Wire Line + 2600 1950 3000 1950 +Wire Wire Line + 3000 1950 3000 1500 +Wire Wire Line + 4100 1500 4100 1750 +Wire Wire Line + 4100 1750 3100 1750 +Wire Wire Line + 3100 1750 3100 2750 +Wire Wire Line + 3100 2750 2750 2750 +Wire Wire Line + 2750 2750 2750 2900 +Wire Wire Line + 4100 1400 5150 1400 +Wire Wire Line + 5150 1400 5150 2900 +Wire Wire Line + 4100 1300 7450 1300 +Wire Wire Line + 7450 1300 7450 2900 +Wire Wire Line + 4100 1200 9650 1200 +Wire Wire Line + 9650 1200 9650 2900 +$Comp +L adc_bridge_3 U1 +U 1 1 554B96E5 +P 2050 5150 +F 0 "U1" H 2050 5150 60 0000 C CNN +F 1 "adc_bridge_3" H 2050 5300 60 0000 C CNN +F 2 "" H 2050 5150 60 0000 C CNN +F 3 "" H 2050 5150 60 0000 C CNN + 1 2050 5150 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 2100 4600 2100 4450 +Wire Wire Line + 1650 4450 2500 4450 +Wire Wire Line + 2500 4450 2500 5150 +Wire Wire Line + 2500 5150 8500 5150 +Wire Wire Line + 8500 5150 8500 3650 +Wire Wire Line + 8500 3650 8850 3650 +Wire Wire Line + 1950 3650 1650 3650 +Wire Wire Line + 1650 3650 1650 4450 +Connection ~ 2100 4450 +Wire Wire Line + 4350 3650 4100 3650 +Wire Wire Line + 4100 3650 4100 5150 +Connection ~ 4100 5150 +Wire Wire Line + 6650 3650 6400 3650 +Wire Wire Line + 6400 3650 6400 5150 +Connection ~ 6400 5150 +Wire Wire Line + 1550 6300 2100 6300 +Wire Wire Line + 2100 6300 2100 5750 +Wire Wire Line + 1550 5600 1550 5850 +Wire Wire Line + 1550 5850 2000 5850 +Wire Wire Line + 2000 5850 2000 5750 +Wire Wire Line + 1550 6800 2200 6800 +Wire Wire Line + 2200 6800 2200 5750 +Wire Wire Line + 2000 4600 1550 4600 +Wire Wire Line + 1550 4600 1550 3250 +Wire Wire Line + 1550 3250 1950 3250 +Wire Wire Line + 2200 4600 2200 4350 +Wire Wire Line + 2200 4350 1800 4350 +Wire Wire Line + 1800 4350 1800 4100 +Wire Wire Line + 1800 4100 1950 4100 +$Comp +L dac_bridge_4 U9 +U 1 1 554BA2AA +P 8550 2150 +F 0 "U9" H 8550 2150 60 0000 C CNN +F 1 "dac_bridge_4" H 8550 2450 60 0000 C CNN +F 2 "" H 8550 2150 60 0000 C CNN +F 3 "" H 8550 2150 60 0000 C CNN + 1 8550 2150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3550 3250 3850 3250 +Wire Wire Line + 3850 3250 3850 1950 +Wire Wire Line + 3850 1950 8000 1950 +Wire Wire Line + 6300 3250 5950 3250 +Wire Wire Line + 6300 2050 6300 3250 +Wire Wire Line + 6300 2050 8000 2050 +Wire Wire Line + 8250 3250 8250 2500 +Wire Wire Line + 8250 2500 6600 2500 +Wire Wire Line + 6600 2500 6600 2150 +Wire Wire Line + 6600 2150 8000 2150 +Wire Wire Line + 10450 3250 10450 2650 +Wire Wire Line + 10450 2650 7800 2650 +Wire Wire Line + 7800 2650 7800 2250 +Wire Wire Line + 7800 2250 8000 2250 +$Comp +L R R2 +U 1 1 554B8B2B +P 9950 1950 +F 0 "R2" V 10030 1950 50 0000 C CNN +F 1 "1k" V 9950 1950 50 0000 C CNN +F 2 "" V 9880 1950 30 0000 C CNN +F 3 "" H 9950 1950 30 0000 C CNN + 1 9950 1950 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 554B8C79 +P 9950 2100 +F 0 "R3" V 10030 2100 50 0000 C CNN +F 1 "1k" V 9950 2100 50 0000 C CNN +F 2 "" V 9880 2100 30 0000 C CNN +F 3 "" H 9950 2100 30 0000 C CNN + 1 9950 2100 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 554B8CE6 +P 9950 2250 +F 0 "R4" V 10030 2250 50 0000 C CNN +F 1 "1k" V 9950 2250 50 0000 C CNN +F 2 "" V 9880 2250 30 0000 C CNN +F 3 "" H 9950 2250 30 0000 C CNN + 1 9950 2250 + 0 1 1 0 +$EndComp +$Comp +L R R1 +U 1 1 554B8D36 +P 9950 1800 +F 0 "R1" V 10030 1800 50 0000 C CNN +F 1 "1k" V 9950 1800 50 0000 C CNN +F 2 "" V 9880 1800 30 0000 C CNN +F 3 "" H 9950 1800 30 0000 C CNN + 1 9950 1800 + 0 1 1 0 +$EndComp +Wire Wire Line + 9100 1950 9300 1950 +Wire Wire Line + 9300 1950 9300 1800 +Wire Wire Line + 9300 1800 9800 1800 +Wire Wire Line + 9100 2050 9500 2050 +Wire Wire Line + 9500 2050 9500 1950 +Wire Wire Line + 9500 1950 9800 1950 +Wire Wire Line + 9100 2150 9700 2150 +Wire Wire Line + 9700 2150 9700 2100 +Wire Wire Line + 9700 2100 9800 2100 +Wire Wire Line + 9100 2250 9800 2250 +$Comp +L GND #PWR03 +U 1 1 554B90FC +P 10450 2400 +F 0 "#PWR03" H 10450 2150 50 0001 C CNN +F 1 "GND" H 10450 2250 50 0000 C CNN +F 2 "" H 10450 2400 60 0000 C CNN +F 3 "" H 10450 2400 60 0000 C CNN + 1 10450 2400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10100 1800 10450 1800 +Wire Wire Line + 10450 1800 10450 2400 +Wire Wire Line + 10100 1950 10450 1950 +Connection ~ 10450 1950 +Wire Wire Line + 10100 2100 10450 2100 +Connection ~ 10450 2100 +Wire Wire Line + 10100 2250 10450 2250 +Connection ~ 10450 2250 +$Comp +L GND #PWR04 +U 1 1 554B95B8 +P 2800 7050 +F 0 "#PWR04" H 2800 6800 50 0001 C CNN +F 1 "GND" H 2800 6900 50 0000 C CNN +F 2 "" H 2800 7050 60 0000 C CNN +F 3 "" H 2800 7050 60 0000 C CNN + 1 2800 7050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3050 5450 2800 5450 +Wire Wire Line + 2800 5450 2800 7050 +Wire Wire Line + 3100 5950 2800 5950 +Connection ~ 2800 5950 +Wire Wire Line + 3050 6400 2800 6400 +Connection ~ 2800 6400 +Wire Wire Line + 3050 6700 2800 6700 +Connection ~ 2800 6700 +$Comp +L GND #PWR05 +U 1 1 554B9C35 +P 1400 2200 +F 0 "#PWR05" H 1400 1950 50 0001 C CNN +F 1 "GND" H 1400 2050 50 0000 C CNN +F 2 "" H 1400 2200 60 0000 C CNN +F 3 "" H 1400 2200 60 0000 C CNN + 1 1400 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1700 700 1400 700 +Wire Wire Line + 1400 700 1400 2200 +Wire Wire Line + 1700 1950 1400 1950 +Connection ~ 1400 1950 +Wire Wire Line + 1700 1650 1400 1650 +Connection ~ 1400 1650 +Wire Wire Line + 1750 1200 1400 1200 +Connection ~ 1400 1200 +$Comp +L GND #PWR06 +U 1 1 554BA1F1 +P 10650 4200 +F 0 "#PWR06" H 10650 3950 50 0001 C CNN +F 1 "GND" H 10650 4050 50 0000 C CNN +F 2 "" H 10650 4200 60 0000 C CNN +F 3 "" H 10650 4200 60 0000 C CNN + 1 10650 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10450 4100 10650 4100 +Wire Wire Line + 10650 4100 10650 4200 +$EndSCHEMATC diff --git a/Examples/4_bit_JK_ff/4_bit_JK_ff.cir b/Examples/4_bit_JK_ff/4_bit_JK_ff.cir new file mode 100644 index 00000000..5b31b134 --- /dev/null +++ b/Examples/4_bit_JK_ff/4_bit_JK_ff.cir @@ -0,0 +1,33 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thu May 7 15:36:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U3 4 5 19 12 28 9 25 d_jkff +v1 2 20 dc +v3 1 20 dc +v4 33 20 0 +v2 3 20 pulse +U5 25 25 19 11 29 21 34 d_jkff +U7 35 35 19 17 30 22 36 d_jkff +U10 27 27 19 18 16 23 20 d_jkff +U6 34 25 35 d_and +U8 36 35 27 d_and +U4 26 33 31 32 28 29 30 16 adc_bridge_4 +v10 31 20 0 +v11 32 20 0 +v9 26 20 0 +v8 14 20 0 +U2 15 14 10 13 18 17 11 12 adc_bridge_4 +v6 10 20 0 +v7 13 20 0 +v5 15 20 0 +U1 2 3 1 4 19 5 adc_bridge_3 +U9 9 21 22 23 6 7 8 24 dac_bridge_4 +R2 20 7 1k +R3 20 8 1k +R4 20 24 1k +R1 20 6 1k + +.end diff --git a/Examples/4_bit_JK_ff/4_bit_JK_ff.cir.out b/Examples/4_bit_JK_ff/4_bit_JK_ff.cir.out new file mode 100644 index 00000000..d0a9d2f5 --- /dev/null +++ b/Examples/4_bit_JK_ff/4_bit_JK_ff.cir.out @@ -0,0 +1,71 @@ +* eeschema netlist version 1.1 (spice format) creation date: thu may 7 15:36:48 2015 + +* u3 4 5 19 12 28 9 25 d_jkff +v1 2 0 dc 5 +v3 1 0 dc 5 +v4 33 0 0 +v2 3 0 pulse(0 5 0.1m 0.1m 0.1m 20m 40m) +* u5 25 25 19 11 29 21 34 d_jkff +* u7 35 35 19 17 30 22 36 d_jkff +* u10 27 27 19 18 16 23 0 d_jkff +* u6 34 25 35 d_and +* u8 36 35 27 d_and +* u4 26 33 31 32 28 29 30 16 adc_bridge_4 +v10 31 0 0 +v11 32 0 0 +v9 26 0 0 +v8 14 0 0 +* u2 15 14 10 13 18 17 11 12 adc_bridge_4 +v6 10 0 0 +v7 13 0 0 +v5 15 0 0 +* u1 2 3 1 4 19 5 adc_bridge_3 +* u9 9 21 22 23 6 7 8 24 dac_bridge_4 +r2 0 7 1k +r3 0 8 1k +r4 0 24 1k +r1 0 6 1k +a1 4 5 19 12 28 9 25 u3 +a2 25 25 19 11 29 21 34 u5 +a3 35 35 19 17 30 22 36 u7 +a4 27 27 19 18 16 23 100 u10 +a5 [34 25 ] 35 u6 +a6 [36 35 ] 27 u8 +a7 [26 33 31 32 ] [28 29 30 16 ] u4 +a8 [15 14 10 13 ] [18 17 11 12 ] u2 +a9 [2 3 1 ] [4 19 5 ] u1 +a10 [9 21 22 23 ] [6 7 8 24 ] u9 +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u3 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u5 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u7 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u10 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u4 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u2 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u9 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +plot v(3) +plot v(6) +plot v(7) +plot v(8) +plot v(24) +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/4_bit_JK_ff/4_bit_JK_ff.pro b/Examples/4_bit_JK_ff/4_bit_JK_ff.pro new file mode 100644 index 00000000..250e6e68 --- /dev/null +++ b/Examples/4_bit_JK_ff/4_bit_JK_ff.pro @@ -0,0 +1,68 @@ +update=Tue May 5 15:14:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName34=/home/gaurav/Desktop/FreeEDA/library/measurementSpice +LibName35=/home/gaurav/Desktop/FreeEDA/library/sourcesSpice diff --git a/Examples/4_bit_JK_ff/4_bit_JK_ff.proj b/Examples/4_bit_JK_ff/4_bit_JK_ff.proj new file mode 100644 index 00000000..8f9f9a1b --- /dev/null +++ b/Examples/4_bit_JK_ff/4_bit_JK_ff.proj @@ -0,0 +1 @@ +schematicFile 4_bit_JK_ff.sch diff --git a/Examples/4_bit_JK_ff/4_bit_JK_ff.sch b/Examples/4_bit_JK_ff/4_bit_JK_ff.sch new file mode 100644 index 00000000..23fb77ae --- /dev/null +++ b/Examples/4_bit_JK_ff/4_bit_JK_ff.sch @@ -0,0 +1,687 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:measurementSpice +LIBS:sourcesSpice +LIBS:4_bit_JK_ff-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_jkff U3 +U 1 1 5548DDEE +P 2750 3650 +F 0 "U3" H 2750 3650 60 0000 C CNN +F 1 "d_jkff" H 2800 3800 60 0000 C CNN +F 2 "" H 2750 3650 60 0000 C CNN +F 3 "" H 2750 3650 60 0000 C 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+Wire Wire Line + 1700 1950 1400 1950 +Connection ~ 1400 1950 +Wire Wire Line + 1700 1650 1400 1650 +Connection ~ 1400 1650 +Wire Wire Line + 1750 1200 1400 1200 +Connection ~ 1400 1200 +$Comp +L GND #PWR06 +U 1 1 554BA1F1 +P 10650 4200 +F 0 "#PWR06" H 10650 3950 50 0001 C CNN +F 1 "GND" H 10650 4050 50 0000 C CNN +F 2 "" H 10650 4200 60 0000 C CNN +F 3 "" H 10650 4200 60 0000 C CNN + 1 10650 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10450 4100 10650 4100 +Wire Wire Line + 10650 4100 10650 4200 +$EndSCHEMATC diff --git a/Examples/4_bit_JK_ff/analysis b/Examples/4_bit_JK_ff/analysis new file mode 100644 index 00000000..b37befd5 --- /dev/null +++ b/Examples/4_bit_JK_ff/analysis @@ -0,0 +1 @@ +.tran Nonee-03 Nonee-03 Nonee-03
\ No newline at end of file diff --git a/Examples/4_bit_JK_ff/plot_data_i.txt b/Examples/4_bit_JK_ff/plot_data_i.txt new file mode 100644 index 00000000..3a3e47b6 --- /dev/null +++ b/Examples/4_bit_JK_ff/plot_data_i.txt @@ -0,0 +1,1019 @@ +* eeschema netlist version 1.1 (spice format) creation date: thu may 7 15:36:48 2015 +Transient Analysis Tue Jun 30 14:46:32 2015 +-------------------------------------------------------------------------------- +Index time a10#branch_1_0 a10#branch_1_1 a10#branch_1_2 +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.000000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +9 1.064000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +10 1.192000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +11 1.448000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +12 1.448030e-04 0.000000e+00 0.000000e+00 0.000000e+00 +13 1.448031e-04 -5.00000e-04 -5.00000e-04 -5.00000e-04 +14 1.448033e-04 -1.50000e-03 -1.50000e-03 -1.50000e-03 +15 1.448037e-04 -3.50000e-03 -3.50000e-03 -3.50000e-03 +16 1.448040e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +17 1.448041e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +18 1.448042e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +19 1.448046e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +20 1.448052e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +21 1.448065e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +22 1.448090e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +23 1.448142e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +24 1.448244e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +25 1.448449e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +26 1.448858e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +27 1.449678e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +28 1.451316e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +29 1.454593e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +30 1.461146e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +31 1.474254e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +32 1.500468e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +33 1.552897e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +34 1.657754e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +35 1.867470e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +36 2.000000e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +37 2.041943e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +38 2.125829e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +39 2.293601e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +40 2.629146e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +41 3.300234e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +42 4.642412e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +43 7.326766e-04 -5.00000e-03 -5.00000e-03 -5.00000e-03 +44 1.269548e-03 -5.00000e-03 -5.00000e-03 -5.00000e-03 +45 2.343289e-03 -5.00000e-03 -5.00000e-03 -5.00000e-03 +46 4.343289e-03 -5.00000e-03 -5.00000e-03 -5.00000e-03 +47 6.343289e-03 -5.00000e-03 -5.00000e-03 -5.00000e-03 +48 8.343289e-03 -5.00000e-03 -5.00000e-03 -5.00000e-03 +49 1.034329e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +50 1.234329e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +51 1.434329e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +52 1.634329e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +53 1.834329e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +54 2.020000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 + +Index time a10#branch_1_0 a10#branch_1_1 a10#branch_1_2 +-------------------------------------------------------------------------------- +55 2.021000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +56 2.023000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +57 2.027000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +58 2.030000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +59 2.030800e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +60 2.032400e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +61 2.035600e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +62 2.042000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +63 2.054800e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +64 2.080400e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +65 2.131600e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +66 2.234000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +67 2.434000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +68 2.634000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +69 2.834000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +70 3.034000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +71 3.234000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +72 3.434000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +73 3.634000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +74 3.834000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +75 4.010000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +76 4.011000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +77 4.013000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +78 4.017000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +79 4.017000e-02 -5.00000e-03 -5.00000e-03 -5.00000e-03 +80 4.017000e-02 -4.50000e-03 -5.00000e-03 -5.00000e-03 +81 4.017000e-02 -3.50000e-03 -5.00000e-03 -5.00000e-03 +82 4.017000e-02 -1.50000e-03 -5.00000e-03 -5.00000e-03 +83 4.017000e-02 -2.63178e-12 -5.00000e-03 -5.00000e-03 +84 4.017000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +85 4.017000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +86 4.017000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +87 4.017001e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +88 4.017001e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +89 4.017001e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +90 4.017001e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +91 4.017002e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +92 4.017004e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +93 4.017009e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +94 4.017017e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +95 4.017033e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +96 4.017066e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +97 4.017131e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +98 4.017263e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +99 4.017525e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +100 4.018049e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +101 4.019098e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +102 4.020000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +103 4.020210e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +104 4.020629e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +105 4.021468e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +106 4.023146e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +107 4.026501e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +108 4.033212e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +109 4.046634e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +110 4.073477e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +111 4.127164e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +112 4.234539e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 + +Index time a10#branch_1_0 a10#branch_1_1 a10#branch_1_2 +-------------------------------------------------------------------------------- +113 4.434539e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +114 4.634539e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +115 4.834539e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +116 5.034539e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +117 5.234539e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +118 5.434539e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +119 5.634539e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +120 5.834539e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +121 6.020000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +122 6.021000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +123 6.023000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +124 6.027000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +125 6.030000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +126 6.030800e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +127 6.032400e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +128 6.035600e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +129 6.042000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +130 6.054800e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +131 6.080400e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +132 6.131600e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +133 6.234000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +134 6.434000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +135 6.634000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +136 6.834000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +137 7.034000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +138 7.234000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +139 7.434000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +140 7.634000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +141 7.834000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +142 8.010000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +143 8.011000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +144 8.013000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +145 8.017000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +146 8.017000e-02 0.000000e+00 -5.00000e-03 -5.00000e-03 +147 8.017000e-02 -5.00000e-04 -4.50000e-03 -5.00000e-03 +148 8.017000e-02 -1.50000e-03 -3.50000e-03 -5.00000e-03 +149 8.017000e-02 -3.50000e-03 -1.50000e-03 -5.00000e-03 +150 8.017000e-02 -5.00000e-03 -2.63178e-12 -5.00000e-03 +151 8.017000e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +152 8.017000e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +153 8.017000e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +154 8.017001e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +155 8.017001e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +156 8.017001e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +157 8.017001e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +158 8.017002e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +159 8.017004e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +160 8.017009e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +161 8.017017e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +162 8.017033e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +163 8.017066e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +164 8.017131e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +165 8.017263e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +166 8.017525e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +167 8.018049e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +168 8.019098e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +169 8.020000e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +170 8.020210e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 + +Index time a10#branch_1_0 a10#branch_1_1 a10#branch_1_2 +-------------------------------------------------------------------------------- +171 8.020629e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +172 8.021468e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +173 8.023146e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +174 8.026501e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +175 8.033212e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +176 8.046634e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +177 8.073477e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +178 8.127164e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +179 8.234539e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +180 8.434539e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +181 8.634539e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +182 8.834539e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +183 9.034539e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +184 9.234539e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +185 9.434539e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +186 9.634539e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +187 9.834539e-02 -5.00000e-03 0.000000e+00 -5.00000e-03 +188 1.000000e-01 -5.00000e-03 0.000000e+00 -5.00000e-03 + +* eeschema netlist version 1.1 (spice format) creation date: thu may 7 15:36:48 2015 +Transient Analysis Tue Jun 30 14:46:32 2015 +-------------------------------------------------------------------------------- +Index time a10#branch_1_3 v1#branch v2#branch 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0.000000e+00 0.000000e+00 +17 1.448041e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +18 1.448042e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +19 1.448046e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +20 1.448052e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +21 1.448065e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +22 1.448090e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +23 1.448142e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +24 1.448244e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +25 1.448449e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +26 1.448858e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +27 1.449678e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +28 1.451316e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +29 1.454593e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +30 1.461146e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +31 1.474254e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +32 1.500468e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +33 1.552897e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +34 1.657754e-04 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0.000000e+00 + +Index time a10#branch_1_3 v1#branch v2#branch +-------------------------------------------------------------------------------- +171 8.020629e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +172 8.021468e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +173 8.023146e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +174 8.026501e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +175 8.033212e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +176 8.046634e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +177 8.073477e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +178 8.127164e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +179 8.234539e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +180 8.434539e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +181 8.634539e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +182 8.834539e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +183 9.034539e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +184 9.234539e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +185 9.434539e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +186 9.634539e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +187 9.834539e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +188 1.000000e-01 -5.00000e-03 0.000000e+00 0.000000e+00 + +* eeschema netlist version 1.1 (spice format) creation date: thu may 7 15:36:48 2015 +Transient Analysis Tue Jun 30 14:46:32 2015 +-------------------------------------------------------------------------------- +Index time v3#branch v4#branch v5#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.000000e-04 0.000000e+00 0.000000e+00 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9.834539e-02 0.000000e+00 0.000000e+00 0.000000e+00 +188 1.000000e-01 0.000000e+00 0.000000e+00 0.000000e+00 + +* eeschema netlist version 1.1 (spice format) creation date: thu may 7 15:36:48 2015 +Transient Analysis Tue Jun 30 14:46:32 2015 +-------------------------------------------------------------------------------- +Index time v9#branch v10#branch v11#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.000000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +9 1.064000e-04 0.000000e+00 0.000000e+00 0.000000e+00 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8.017131e-02 0.000000e+00 0.000000e+00 0.000000e+00 +165 8.017263e-02 0.000000e+00 0.000000e+00 0.000000e+00 +166 8.017525e-02 0.000000e+00 0.000000e+00 0.000000e+00 +167 8.018049e-02 0.000000e+00 0.000000e+00 0.000000e+00 +168 8.019098e-02 0.000000e+00 0.000000e+00 0.000000e+00 +169 8.020000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +170 8.020210e-02 0.000000e+00 0.000000e+00 0.000000e+00 + +Index time v9#branch v10#branch v11#branch +-------------------------------------------------------------------------------- +171 8.020629e-02 0.000000e+00 0.000000e+00 0.000000e+00 +172 8.021468e-02 0.000000e+00 0.000000e+00 0.000000e+00 +173 8.023146e-02 0.000000e+00 0.000000e+00 0.000000e+00 +174 8.026501e-02 0.000000e+00 0.000000e+00 0.000000e+00 +175 8.033212e-02 0.000000e+00 0.000000e+00 0.000000e+00 +176 8.046634e-02 0.000000e+00 0.000000e+00 0.000000e+00 +177 8.073477e-02 0.000000e+00 0.000000e+00 0.000000e+00 +178 8.127164e-02 0.000000e+00 0.000000e+00 0.000000e+00 +179 8.234539e-02 0.000000e+00 0.000000e+00 0.000000e+00 +180 8.434539e-02 0.000000e+00 0.000000e+00 0.000000e+00 +181 8.634539e-02 0.000000e+00 0.000000e+00 0.000000e+00 +182 8.834539e-02 0.000000e+00 0.000000e+00 0.000000e+00 +183 9.034539e-02 0.000000e+00 0.000000e+00 0.000000e+00 +184 9.234539e-02 0.000000e+00 0.000000e+00 0.000000e+00 +185 9.434539e-02 0.000000e+00 0.000000e+00 0.000000e+00 +186 9.634539e-02 0.000000e+00 0.000000e+00 0.000000e+00 +187 9.834539e-02 0.000000e+00 0.000000e+00 0.000000e+00 +188 1.000000e-01 0.000000e+00 0.000000e+00 0.000000e+00 diff --git a/Examples/4_bit_JK_ff/plot_data_v.txt b/Examples/4_bit_JK_ff/plot_data_v.txt new file mode 100644 index 00000000..80b73cfb --- /dev/null +++ b/Examples/4_bit_JK_ff/plot_data_v.txt @@ -0,0 +1,1019 @@ +* eeschema netlist version 1.1 (spice format) creation date: thu may 7 15:36:48 2015 +Transient Analysis Tue Jun 30 14:46:32 2015 +-------------------------------------------------------------------------------- +Index time V(1) V(2) V(3) +-------------------------------------------------------------------------------- +0 0.000000e+00 5.000000e+00 5.000000e+00 0.000000e+00 +1 1.000000e-06 5.000000e+00 5.000000e+00 0.000000e+00 +2 2.000000e-06 5.000000e+00 5.000000e+00 0.000000e+00 +3 4.000000e-06 5.000000e+00 5.000000e+00 0.000000e+00 +4 8.000000e-06 5.000000e+00 5.000000e+00 0.000000e+00 +5 1.600000e-05 5.000000e+00 5.000000e+00 0.000000e+00 +6 3.200000e-05 5.000000e+00 5.000000e+00 0.000000e+00 +7 6.400000e-05 5.000000e+00 5.000000e+00 0.000000e+00 +8 1.000000e-04 5.000000e+00 5.000000e+00 0.000000e+00 +9 1.064000e-04 5.000000e+00 5.000000e+00 3.200000e-01 +10 1.192000e-04 5.000000e+00 5.000000e+00 9.600000e-01 +11 1.448000e-04 5.000000e+00 5.000000e+00 2.240000e+00 +12 1.448030e-04 5.000000e+00 5.000000e+00 2.240150e+00 +13 1.448031e-04 5.000000e+00 5.000000e+00 2.240155e+00 +14 1.448033e-04 5.000000e+00 5.000000e+00 2.240165e+00 +15 1.448037e-04 5.000000e+00 5.000000e+00 2.240185e+00 +16 1.448040e-04 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5.000000e+00 5.000000e+00 +187 9.834539e-02 5.000000e+00 5.000000e+00 5.000000e+00 +188 1.000000e-01 5.000000e+00 5.000000e+00 5.000000e+00 + +* eeschema netlist version 1.1 (spice format) creation date: thu may 7 15:36:48 2015 +Transient Analysis Tue Jun 30 14:46:32 2015 +-------------------------------------------------------------------------------- +Index time V(6) V(7) V(8) +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.000000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +9 1.064000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +10 1.192000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +11 1.448000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +12 1.448030e-04 0.000000e+00 0.000000e+00 0.000000e+00 +13 1.448031e-04 5.000000e-01 5.000000e-01 5.000000e-01 +14 1.448033e-04 1.500000e+00 1.500000e+00 1.500000e+00 +15 1.448037e-04 3.500000e+00 3.500000e+00 3.500000e+00 +16 1.448040e-04 5.000000e+00 5.000000e+00 5.000000e+00 +17 1.448041e-04 5.000000e+00 5.000000e+00 5.000000e+00 +18 1.448042e-04 5.000000e+00 5.000000e+00 5.000000e+00 +19 1.448046e-04 5.000000e+00 5.000000e+00 5.000000e+00 +20 1.448052e-04 5.000000e+00 5.000000e+00 5.000000e+00 +21 1.448065e-04 5.000000e+00 5.000000e+00 5.000000e+00 +22 1.448090e-04 5.000000e+00 5.000000e+00 5.000000e+00 +23 1.448142e-04 5.000000e+00 5.000000e+00 5.000000e+00 +24 1.448244e-04 5.000000e+00 5.000000e+00 5.000000e+00 +25 1.448449e-04 5.000000e+00 5.000000e+00 5.000000e+00 +26 1.448858e-04 5.000000e+00 5.000000e+00 5.000000e+00 +27 1.449678e-04 5.000000e+00 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+$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/BJT_amplifier/BJT_amplifier-cache.lib b/Examples/BJT_amplifier/BJT_amplifier-cache.lib new file mode 100644 index 00000000..2fb6cca9 --- /dev/null +++ b/Examples/BJT_amplifier/BJT_amplifier-cache.lib @@ -0,0 +1,125 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# AC +# +DEF AC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/BJT_amplifier/BJT_amplifier.bak b/Examples/BJT_amplifier/BJT_amplifier.bak new file mode 100644 index 00000000..c6030cbd --- /dev/null +++ b/Examples/BJT_amplifier/BJT_amplifier.bak @@ -0,0 +1,263 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:BJT_amplifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "6 jun 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 7050 4450 +Wire Wire Line + 7600 4450 5100 4450 +Wire Wire Line + 7600 4450 7600 4050 +Wire Wire Line + 5100 4350 5100 4500 +Wire Wire Line + 5100 4500 3700 4500 +Connection ~ 6300 4450 +Wire Wire Line + 3700 3600 3900 3600 +Wire Wire Line + 7050 3300 7050 4050 +Wire Wire Line + 6650 3300 7050 3300 +Connection ~ 5100 3600 +Connection ~ 6100 3300 +Wire Wire Line + 5850 3300 6350 3300 +Wire Wire Line + 5850 3800 5850 4050 +Wire Wire Line + 5850 3300 5850 3400 +Wire Wire Line + 5100 3200 5100 4050 +Wire Wire Line + 4900 3600 5550 3600 +Wire Wire Line + 6300 3900 6300 4100 +Wire Wire Line + 6300 3900 5850 3900 +Connection ~ 5850 3900 +Connection ~ 5850 4450 +Wire Wire Line + 4200 3600 4600 3600 +Connection ~ 5100 4450 +Wire Wire Line + 5650 4450 5650 4850 +Connection ~ 5650 4450 +Wire Wire Line + 5100 2800 7600 2800 +Wire Wire Line + 7600 2800 7600 3150 +Connection ~ 6100 2800 +$Comp +L DC v1 +U 1 1 51A5D97E +P 7600 3600 +F 0 "v1" H 7400 3700 60 0000 C CNN +F 1 "DC" H 7400 3550 60 0000 C CNN +F 2 "R1" H 7300 3600 60 0000 C CNN +F 3 "" H 7600 3600 60 0001 C CNN + 1 7600 3600 + 1 0 0 -1 +$EndComp +$Comp +L AC v2 +U 1 1 51A486A5 +P 3700 4050 +F 0 "v2" H 3500 4150 60 0000 C CNN +F 1 "AC" H 3500 4000 60 0000 C CNN +F 2 "R1" H 3400 4050 60 0000 C CNN +F 3 "" H 3700 4050 60 0001 C CNN + 1 3700 4050 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 51A48298 +P 5650 4450 +F 0 "#FLG01" H 5650 4720 30 0001 C CNN +F 1 "PWR_FLAG" H 5650 4680 30 0000 C CNN +F 2 "" H 5650 4450 60 0001 C CNN +F 3 "" H 5650 4450 60 0001 C CNN + 1 5650 4450 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 51A47FCD +P 5650 4850 +F 0 "#PWR02" H 5650 4850 30 0001 C CNN +F 1 "GND" H 5650 4780 30 0001 C CNN +F 2 "" H 5650 4850 60 0001 C CNN +F 3 "" H 5650 4850 60 0001 C CNN + 1 5650 4850 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 51A47FBC +P 4050 3600 +F 0 "R1" V 4130 3600 50 0000 C CNN +F 1 "50" V 4050 3600 50 0000 C CNN +F 2 "" H 4050 3600 60 0001 C CNN +F 3 "" H 4050 3600 60 0001 C CNN + 1 4050 3600 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 51A47FAB +P 5100 3050 +F 0 "R2" V 5180 3050 50 0000 C CNN +F 1 "200k" V 5100 3050 50 0000 C CNN +F 2 "" H 5100 3050 60 0001 C CNN +F 3 "" H 5100 3050 60 0001 C CNN + 1 5100 3050 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 51A47FA0 +P 4750 3600 +F 0 "C1" H 4800 3700 50 0000 L CNN +F 1 "40u" H 4800 3500 50 0000 L CNN +F 2 "" H 4750 3600 60 0001 C CNN +F 3 "" H 4750 3600 60 0001 C CNN + 1 4750 3600 + 0 -1 -1 0 +$EndComp +$Comp +L R R3 +U 1 1 51A47F97 +P 5100 4200 +F 0 "R3" V 5180 4200 50 0000 C CNN +F 1 "50k" V 5100 4200 50 0000 C CNN +F 2 "" H 5100 4200 60 0001 C CNN +F 3 "" H 5100 4200 60 0001 C CNN + 1 5100 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 51A47F8B +P 7050 4200 +F 0 "R6" V 7130 4200 50 0000 C CNN +F 1 "1k" V 7050 4200 50 0000 C CNN +F 2 "" H 7050 4200 60 0001 C CNN +F 3 "" H 7050 4200 60 0001 C CNN + 1 7050 4200 + 1 0 0 -1 +$EndComp +$Comp +L C C2 +U 1 1 51A47F80 +P 6300 4250 +F 0 "C2" H 6350 4350 50 0000 L CNN +F 1 "100u" H 6350 4150 50 0000 L CNN +F 2 "" H 6300 4250 60 0001 C CNN +F 3 "" H 6300 4250 60 0001 C CNN + 1 6300 4250 + -1 0 0 1 +$EndComp +$Comp +L C C3 +U 1 1 51A47F75 +P 6500 3300 +F 0 "C3" H 6550 3400 50 0000 L CNN +F 1 "40u" H 6550 3200 50 0000 L CNN +F 2 "" H 6500 3300 60 0001 C CNN +F 3 "" H 6500 3300 60 0001 C CNN + 1 6500 3300 + 0 1 1 0 +$EndComp +$Comp +L R R5 +U 1 1 51A47F5C +P 6100 3050 +F 0 "R5" V 6180 3050 50 0000 C CNN +F 1 "2k" V 6100 3050 50 0000 C CNN +F 2 "" H 6100 3050 60 0001 C CNN +F 3 "" H 6100 3050 60 0001 C CNN + 1 6100 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 51A47F50 +P 5850 4200 +F 0 "R4" V 5930 4200 50 0000 C CNN +F 1 "1.5k" V 5850 4200 50 0000 C CNN +F 2 "" H 5850 4200 60 0001 C CNN +F 3 "" H 5850 4200 60 0001 C CNN + 1 5850 4200 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 557583B4 +P 5750 3600 +F 0 "Q1" H 5650 3650 50 0000 R CNN +F 1 "NPN" H 5700 3750 50 0000 R CNN +F 2 "" H 5950 3700 29 0000 C CNN +F 3 "" H 5750 3600 60 0000 C CNN + 1 5750 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 2900 6100 2800 +Wire Wire Line + 6100 3200 6100 3300 +Wire Wire Line + 5850 4350 5850 4450 +Wire Wire Line + 6300 4400 6300 4450 +Wire Wire Line + 7050 4350 7050 4450 +Wire Wire Line + 5100 2900 5100 2800 +$EndSCHEMATC diff --git a/Examples/BJT_amplifier/BJT_amplifier.cir b/Examples/BJT_amplifier/BJT_amplifier.cir new file mode 100644 index 00000000..615a623d --- /dev/null +++ b/Examples/BJT_amplifier/BJT_amplifier.cir @@ -0,0 +1,20 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 8 12:02:52 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 6 0 DC +v2 2 0 AC +R1 3 2 50 +R2 6 8 200k +C1 3 8 40u +R3 8 0 50k +R6 4 0 1k +C2 0 5 100u +C3 4 7 40u +R5 6 7 2k +R4 5 0 1.5k +Q1 7 8 5 NPN + +.end diff --git a/Examples/BJT_amplifier/BJT_amplifier.cir (copy).out b/Examples/BJT_amplifier/BJT_amplifier.cir (copy).out new file mode 100644 index 00000000..13bbb551 --- /dev/null +++ b/Examples/BJT_amplifier/BJT_amplifier.cir (copy).out @@ -0,0 +1,25 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 29 may 2013 04:04:50 pm ist
+.include npn.lib
+
+v1 6 0 dc 10
+* Plotting option vplot8_1
+v2 2 0 ac 0.5
+r1 3 2 50
+r2 6 8 200k
+c1 3 8 40u
+r3 8 0 50k
+r6 4 0 1k
+c2 0 5 100u
+c3 4 7 40u
+r5 6 7 2k
+r4 5 0 1.5k
+q1 7 8 5 npn
+
+.ac dec 100 100Hz 10KHz
+
+* Control Statements
+.control
+run
+plot v(4)
+.endc
+.end
diff --git a/Examples/BJT_amplifier/BJT_amplifier.cir.ckt b/Examples/BJT_amplifier/BJT_amplifier.cir.ckt new file mode 100644 index 00000000..281db0e7 --- /dev/null +++ b/Examples/BJT_amplifier/BJT_amplifier.cir.ckt @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 29 may 2013 04:04:50 pm ist
+.include npn.lib
+
+v1 6 0 dc 10
+* Plotting option vplot8_1
+v2 2 0 ac 0.5
+r1 3 2 50
+r2 6 8 200k
+c1 3 8 40u
+r3 8 0 50k
+r6 4 0 1k
+c2 0 5 100u
+c3 4 7 40u
+r5 6 7 2k
+r4 5 0 1.5k
+q1 7 8 5 npn
+
+.ac dec 100 100Hz 10KHz
+.plot v(4)
+.end
diff --git a/Examples/BJT_amplifier/BJT_amplifier.cir.out b/Examples/BJT_amplifier/BJT_amplifier.cir.out new file mode 100644 index 00000000..c7f0b896 --- /dev/null +++ b/Examples/BJT_amplifier/BJT_amplifier.cir.out @@ -0,0 +1,24 @@ +* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 12:02:52 2015 + +.include NPN.lib +v1 6 0 dc 10 +v2 2 0 ac 0.5 +r1 3 2 50 +r2 6 8 200k +c1 3 8 40u +r3 8 0 50k +r6 4 0 1k +c2 0 5 100u +c3 4 7 40u +r5 6 7 2k +r4 5 0 1.5k +q1 7 8 5 Q2N2222 +.ac dec 100 100Hz 10KHz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/BJT_amplifier/BJT_amplifier.pro b/Examples/BJT_amplifier/BJT_amplifier.pro new file mode 100644 index 00000000..af127052 --- /dev/null +++ b/Examples/BJT_amplifier/BJT_amplifier.pro @@ -0,0 +1,41 @@ +update=Mon Jun 8 11:49:01 2015 +last_client=eeschema +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources diff --git a/Examples/BJT_amplifier/BJT_amplifier.proj b/Examples/BJT_amplifier/BJT_amplifier.proj new file mode 100644 index 00000000..79be1da2 --- /dev/null +++ b/Examples/BJT_amplifier/BJT_amplifier.proj @@ -0,0 +1 @@ +schematicFile tp.sch diff --git a/Examples/BJT_amplifier/BJT_amplifier.sch b/Examples/BJT_amplifier/BJT_amplifier.sch new file mode 100644 index 00000000..c6030cbd --- /dev/null +++ b/Examples/BJT_amplifier/BJT_amplifier.sch @@ -0,0 +1,263 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:BJT_amplifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "6 jun 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 7050 4450 +Wire Wire Line + 7600 4450 5100 4450 +Wire Wire Line + 7600 4450 7600 4050 +Wire Wire Line + 5100 4350 5100 4500 +Wire Wire Line + 5100 4500 3700 4500 +Connection ~ 6300 4450 +Wire Wire Line + 3700 3600 3900 3600 +Wire Wire Line + 7050 3300 7050 4050 +Wire Wire Line + 6650 3300 7050 3300 +Connection ~ 5100 3600 +Connection ~ 6100 3300 +Wire Wire Line + 5850 3300 6350 3300 +Wire Wire Line + 5850 3800 5850 4050 +Wire Wire Line + 5850 3300 5850 3400 +Wire Wire Line + 5100 3200 5100 4050 +Wire Wire Line + 4900 3600 5550 3600 +Wire Wire Line + 6300 3900 6300 4100 +Wire Wire Line + 6300 3900 5850 3900 +Connection ~ 5850 3900 +Connection ~ 5850 4450 +Wire Wire Line + 4200 3600 4600 3600 +Connection ~ 5100 4450 +Wire Wire Line + 5650 4450 5650 4850 +Connection ~ 5650 4450 +Wire Wire Line + 5100 2800 7600 2800 +Wire Wire Line + 7600 2800 7600 3150 +Connection ~ 6100 2800 +$Comp +L DC v1 +U 1 1 51A5D97E +P 7600 3600 +F 0 "v1" H 7400 3700 60 0000 C CNN +F 1 "DC" H 7400 3550 60 0000 C CNN +F 2 "R1" H 7300 3600 60 0000 C CNN +F 3 "" H 7600 3600 60 0001 C CNN + 1 7600 3600 + 1 0 0 -1 +$EndComp +$Comp +L AC v2 +U 1 1 51A486A5 +P 3700 4050 +F 0 "v2" H 3500 4150 60 0000 C CNN +F 1 "AC" H 3500 4000 60 0000 C CNN +F 2 "R1" H 3400 4050 60 0000 C CNN +F 3 "" H 3700 4050 60 0001 C CNN + 1 3700 4050 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 51A48298 +P 5650 4450 +F 0 "#FLG01" H 5650 4720 30 0001 C CNN +F 1 "PWR_FLAG" H 5650 4680 30 0000 C CNN +F 2 "" H 5650 4450 60 0001 C CNN +F 3 "" H 5650 4450 60 0001 C CNN + 1 5650 4450 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 51A47FCD +P 5650 4850 +F 0 "#PWR02" H 5650 4850 30 0001 C CNN +F 1 "GND" H 5650 4780 30 0001 C CNN +F 2 "" H 5650 4850 60 0001 C CNN +F 3 "" H 5650 4850 60 0001 C CNN + 1 5650 4850 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 51A47FBC +P 4050 3600 +F 0 "R1" V 4130 3600 50 0000 C CNN +F 1 "50" V 4050 3600 50 0000 C CNN +F 2 "" H 4050 3600 60 0001 C CNN +F 3 "" H 4050 3600 60 0001 C CNN + 1 4050 3600 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 51A47FAB +P 5100 3050 +F 0 "R2" V 5180 3050 50 0000 C CNN +F 1 "200k" V 5100 3050 50 0000 C CNN +F 2 "" H 5100 3050 60 0001 C CNN +F 3 "" H 5100 3050 60 0001 C CNN + 1 5100 3050 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 51A47FA0 +P 4750 3600 +F 0 "C1" H 4800 3700 50 0000 L CNN +F 1 "40u" H 4800 3500 50 0000 L CNN +F 2 "" H 4750 3600 60 0001 C CNN +F 3 "" H 4750 3600 60 0001 C CNN + 1 4750 3600 + 0 -1 -1 0 +$EndComp +$Comp +L R R3 +U 1 1 51A47F97 +P 5100 4200 +F 0 "R3" V 5180 4200 50 0000 C CNN +F 1 "50k" V 5100 4200 50 0000 C CNN +F 2 "" H 5100 4200 60 0001 C CNN +F 3 "" H 5100 4200 60 0001 C CNN + 1 5100 4200 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 51A47F8B +P 7050 4200 +F 0 "R6" V 7130 4200 50 0000 C CNN +F 1 "1k" V 7050 4200 50 0000 C CNN +F 2 "" H 7050 4200 60 0001 C CNN +F 3 "" H 7050 4200 60 0001 C CNN + 1 7050 4200 + 1 0 0 -1 +$EndComp +$Comp +L C C2 +U 1 1 51A47F80 +P 6300 4250 +F 0 "C2" H 6350 4350 50 0000 L CNN +F 1 "100u" H 6350 4150 50 0000 L CNN +F 2 "" H 6300 4250 60 0001 C CNN +F 3 "" H 6300 4250 60 0001 C CNN + 1 6300 4250 + -1 0 0 1 +$EndComp +$Comp +L C C3 +U 1 1 51A47F75 +P 6500 3300 +F 0 "C3" H 6550 3400 50 0000 L CNN +F 1 "40u" H 6550 3200 50 0000 L CNN +F 2 "" H 6500 3300 60 0001 C CNN +F 3 "" H 6500 3300 60 0001 C CNN + 1 6500 3300 + 0 1 1 0 +$EndComp +$Comp +L R R5 +U 1 1 51A47F5C +P 6100 3050 +F 0 "R5" V 6180 3050 50 0000 C CNN +F 1 "2k" V 6100 3050 50 0000 C CNN +F 2 "" H 6100 3050 60 0001 C CNN +F 3 "" H 6100 3050 60 0001 C CNN + 1 6100 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 51A47F50 +P 5850 4200 +F 0 "R4" V 5930 4200 50 0000 C CNN +F 1 "1.5k" V 5850 4200 50 0000 C CNN +F 2 "" H 5850 4200 60 0001 C CNN +F 3 "" H 5850 4200 60 0001 C CNN + 1 5850 4200 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 557583B4 +P 5750 3600 +F 0 "Q1" H 5650 3650 50 0000 R CNN +F 1 "NPN" H 5700 3750 50 0000 R CNN +F 2 "" H 5950 3700 29 0000 C CNN +F 3 "" H 5750 3600 60 0000 C CNN + 1 5750 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 2900 6100 2800 +Wire Wire Line + 6100 3200 6100 3300 +Wire Wire Line + 5850 4350 5850 4450 +Wire Wire Line + 6300 4400 6300 4450 +Wire Wire Line + 7050 4350 7050 4450 +Wire Wire Line + 5100 2900 5100 2800 +$EndSCHEMATC diff --git a/Examples/BJT_amplifier/NPN.lib b/Examples/BJT_amplifier/NPN.lib new file mode 100755 index 00000000..6509fe7a --- /dev/null +++ b/Examples/BJT_amplifier/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/Examples/BJT_amplifier/analysis b/Examples/BJT_amplifier/analysis new file mode 100644 index 00000000..8fcad93a --- /dev/null +++ b/Examples/BJT_amplifier/analysis @@ -0,0 +1 @@ +.ac dec 100 100Hz 10KHz
\ No newline at end of file diff --git a/Examples/BJT_amplifier/npn.lib b/Examples/BJT_amplifier/npn.lib new file mode 100644 index 00000000..8609d520 --- /dev/null +++ b/Examples/BJT_amplifier/npn.lib @@ -0,0 +1,6 @@ +.model npn NPN( Vtf=4 Cjc=3.638p Nc=2 Tr=239.5n Ne=1.259 ++ Cje=4.493p Vjc=.75 Xtb=1.5 Rb=10 Rc=1 ++ Tf=301.2p Xti=3 Ikr=0 Bf=416.4 Fc=.5 ++ Ikf=66.78m Br=.7371 Mje=.2593 Mjc=.3085 Vaf=74.03 ++ Isc=0 Ise=6.734f Xtf=2 Vje=.75 Is=6.734f ++ Itf=.4 Eg=1.11 ) diff --git a/Examples/BJT_amplifier/plot_data_i.txt b/Examples/BJT_amplifier/plot_data_i.txt new file mode 100644 index 00000000..fd3f6360 --- /dev/null +++ b/Examples/BJT_amplifier/plot_data_i.txt @@ -0,0 +1,431 @@ +* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 12:02:52 2015 +AC Analysis Wed Jul 1 14:20:43 2015 +-------------------------------------------------------------------------------- +Index frequency v1#branch +-------------------------------------------------------------------------------- +0 1.000000e+02 -4.09710e-03, -1.86604e-03 +1 1.023293e+02 -4.13095e-03, -1.84008e-03 +2 1.047129e+02 -4.16386e-03, -1.81389e-03 +3 1.071519e+02 -4.19583e-03, -1.78750e-03 +4 1.096478e+02 -4.22687e-03, -1.76095e-03 +5 1.122018e+02 -4.25698e-03, -1.73426e-03 +6 1.148154e+02 -4.28618e-03, -1.70748e-03 +7 1.174898e+02 -4.31447e-03, -1.68064e-03 +8 1.202264e+02 -4.34188e-03, -1.65377e-03 +9 1.230269e+02 -4.36841e-03, -1.62689e-03 +10 1.258925e+02 -4.39408e-03, -1.60004e-03 +11 1.288250e+02 -4.41890e-03, -1.57324e-03 +12 1.318257e+02 -4.44289e-03, -1.54652e-03 +13 1.348963e+02 -4.46607e-03, -1.51989e-03 +14 1.380384e+02 -4.48845e-03, -1.49339e-03 +15 1.412538e+02 -4.51006e-03, -1.46703e-03 +16 1.445440e+02 -4.53090e-03, -1.44084e-03 +17 1.479108e+02 -4.55101e-03, -1.41483e-03 +18 1.513561e+02 -4.57039e-03, -1.38901e-03 +19 1.548817e+02 -4.58906e-03, -1.36342e-03 +20 1.584893e+02 -4.60705e-03, -1.33805e-03 +21 1.621810e+02 -4.62438e-03, -1.31292e-03 +22 1.659587e+02 -4.64105e-03, -1.28805e-03 +23 1.698244e+02 -4.65710e-03, -1.26345e-03 +24 1.737801e+02 -4.67254e-03, -1.23913e-03 +25 1.778279e+02 -4.68739e-03, -1.21509e-03 +26 1.819701e+02 -4.70167e-03, -1.19134e-03 +27 1.862087e+02 -4.71539e-03, -1.16790e-03 +28 1.905461e+02 -4.72857e-03, -1.14477e-03 +29 1.949845e+02 -4.74124e-03, -1.12196e-03 +30 1.995262e+02 -4.75340e-03, -1.09946e-03 +31 2.041738e+02 -4.76509e-03, -1.07729e-03 +32 2.089296e+02 -4.77630e-03, -1.05544e-03 +33 2.137962e+02 -4.78706e-03, -1.03393e-03 +34 2.187762e+02 -4.79739e-03, -1.01275e-03 +35 2.238721e+02 -4.80730e-03, -9.91902e-04 +36 2.290868e+02 -4.81680e-03, -9.71392e-04 +37 2.344229e+02 -4.82591e-03, -9.51218e-04 +38 2.398833e+02 -4.83465e-03, -9.31382e-04 +39 2.454709e+02 -4.84303e-03, -9.11882e-04 +40 2.511886e+02 -4.85106e-03, -8.92718e-04 +41 2.570396e+02 -4.85875e-03, -8.73889e-04 +42 2.630268e+02 -4.86612e-03, -8.55393e-04 +43 2.691535e+02 -4.87319e-03, -8.37229e-04 +44 2.754229e+02 -4.87995e-03, -8.19394e-04 +45 2.818383e+02 -4.88643e-03, -8.01887e-04 +46 2.884032e+02 -4.89264e-03, -7.84705e-04 +47 2.951209e+02 -4.89858e-03, -7.67844e-04 +48 3.019952e+02 -4.90427e-03, -7.51303e-04 +49 3.090295e+02 -4.90972e-03, -7.35077e-04 +50 3.162278e+02 -4.91494e-03, -7.19164e-04 +51 3.235937e+02 -4.91993e-03, -7.03560e-04 +52 3.311311e+02 -4.92470e-03, -6.88261e-04 +53 3.388442e+02 -4.92928e-03, -6.73263e-04 +54 3.467369e+02 -4.93365e-03, -6.58563e-04 + +Index frequency v1#branch +-------------------------------------------------------------------------------- +55 3.548134e+02 -4.93783e-03, -6.44157e-04 +56 3.630781e+02 -4.94184e-03, -6.30040e-04 +57 3.715352e+02 -4.94567e-03, -6.16208e-04 +58 3.801894e+02 -4.94933e-03, -6.02658e-04 +59 3.890451e+02 -4.95284e-03, -5.89384e-04 +60 3.981072e+02 -4.95619e-03, -5.76383e-04 +61 4.073803e+02 -4.95939e-03, -5.63650e-04 +62 4.168694e+02 -4.96246e-03, -5.51182e-04 +63 4.265795e+02 -4.96539e-03, -5.38973e-04 +64 4.365158e+02 -4.96819e-03, -5.27019e-04 +65 4.466836e+02 -4.97087e-03, -5.15316e-04 +66 4.570882e+02 -4.97343e-03, -5.03860e-04 +67 4.677351e+02 -4.97588e-03, -4.92646e-04 +68 4.786301e+02 -4.97822e-03, -4.81670e-04 +69 4.897788e+02 -4.98046e-03, -4.70927e-04 +70 5.011872e+02 -4.98260e-03, -4.60414e-04 +71 5.128614e+02 -4.98465e-03, -4.50126e-04 +72 5.248075e+02 -4.98660e-03, -4.40059e-04 +73 5.370318e+02 -4.98847e-03, -4.30208e-04 +74 5.495409e+02 -4.99025e-03, -4.20570e-04 +75 5.623413e+02 -4.99196e-03, -4.11141e-04 +76 5.754399e+02 -4.99359e-03, -4.01916e-04 +77 5.888437e+02 -4.99515e-03, -3.92892e-04 +78 6.025596e+02 -4.99664e-03, -3.84064e-04 +79 6.165950e+02 -4.99806e-03, -3.75428e-04 +80 6.309573e+02 -4.99942e-03, -3.66981e-04 +81 6.456542e+02 -5.00072e-03, -3.58720e-04 +82 6.606934e+02 -5.00196e-03, -3.50639e-04 +83 6.760830e+02 -5.00315e-03, -3.42736e-04 +84 6.918310e+02 -5.00428e-03, -3.35007e-04 +85 7.079458e+02 -5.00537e-03, -3.27448e-04 +86 7.244360e+02 -5.00640e-03, -3.20056e-04 +87 7.413102e+02 -5.00739e-03, -3.12827e-04 +88 7.585776e+02 -5.00834e-03, -3.05759e-04 +89 7.762471e+02 -5.00924e-03, -2.98846e-04 +90 7.943282e+02 -5.01010e-03, -2.92087e-04 +91 8.128305e+02 -5.01092e-03, -2.85478e-04 +92 8.317638e+02 -5.01171e-03, -2.79016e-04 +93 8.511380e+02 -5.01246e-03, -2.72697e-04 +94 8.709636e+02 -5.01318e-03, -2.66519e-04 +95 8.912509e+02 -5.01387e-03, -2.60479e-04 +96 9.120108e+02 -5.01452e-03, -2.54573e-04 +97 9.332543e+02 -5.01515e-03, -2.48800e-04 +98 9.549926e+02 -5.01575e-03, -2.43155e-04 +99 9.772372e+02 -5.01632e-03, -2.37636e-04 +100 1.000000e+03 -5.01686e-03, -2.32240e-04 +101 1.023293e+03 -5.01738e-03, -2.26965e-04 +102 1.047129e+03 -5.01788e-03, -2.21809e-04 +103 1.071519e+03 -5.01836e-03, -2.16767e-04 +104 1.096478e+03 -5.01881e-03, -2.11839e-04 +105 1.122018e+03 -5.01925e-03, -2.07021e-04 +106 1.148154e+03 -5.01966e-03, -2.02311e-04 +107 1.174898e+03 -5.02006e-03, -1.97707e-04 +108 1.202264e+03 -5.02043e-03, -1.93206e-04 +109 1.230269e+03 -5.02080e-03, -1.88806e-04 +110 1.258925e+03 -5.02114e-03, -1.84505e-04 +111 1.288250e+03 -5.02147e-03, -1.80301e-04 +112 1.318257e+03 -5.02178e-03, -1.76191e-04 + +Index frequency v1#branch +-------------------------------------------------------------------------------- +113 1.348963e+03 -5.02209e-03, -1.72173e-04 +114 1.380384e+03 -5.02237e-03, -1.68246e-04 +115 1.412538e+03 -5.02265e-03, -1.64407e-04 +116 1.445440e+03 -5.02291e-03, -1.60654e-04 +117 1.479108e+03 -5.02316e-03, -1.56986e-04 +118 1.513561e+03 -5.02340e-03, -1.53400e-04 +119 1.548817e+03 -5.02363e-03, -1.49894e-04 +120 1.584893e+03 -5.02384e-03, -1.46468e-04 +121 1.621810e+03 -5.02405e-03, -1.43118e-04 +122 1.659587e+03 -5.02425e-03, -1.39844e-04 +123 1.698244e+03 -5.02444e-03, -1.36643e-04 +124 1.737801e+03 -5.02462e-03, -1.33515e-04 +125 1.778279e+03 -5.02479e-03, -1.30457e-04 +126 1.819701e+03 -5.02496e-03, -1.27467e-04 +127 1.862087e+03 -5.02512e-03, -1.24545e-04 +128 1.905461e+03 -5.02527e-03, -1.21688e-04 +129 1.949845e+03 -5.02541e-03, -1.18895e-04 +130 1.995262e+03 -5.02555e-03, -1.16165e-04 +131 2.041738e+03 -5.02568e-03, -1.13497e-04 +132 2.089296e+03 -5.02581e-03, -1.10888e-04 +133 2.137962e+03 -5.02593e-03, -1.08338e-04 +134 2.187762e+03 -5.02604e-03, -1.05845e-04 +135 2.238721e+03 -5.02615e-03, -1.03408e-04 +136 2.290868e+03 -5.02625e-03, -1.01025e-04 +137 2.344229e+03 -5.02635e-03, -9.86964e-05 +138 2.398833e+03 -5.02645e-03, -9.64194e-05 +139 2.454709e+03 -5.02654e-03, -9.41934e-05 +140 2.511886e+03 -5.02663e-03, -9.20171e-05 +141 2.570396e+03 -5.02671e-03, -8.98895e-05 +142 2.630268e+03 -5.02679e-03, -8.78094e-05 +143 2.691535e+03 -5.02687e-03, -8.57757e-05 +144 2.754229e+03 -5.02694e-03, -8.37873e-05 +145 2.818383e+03 -5.02701e-03, -8.18433e-05 +146 2.884032e+03 -5.02707e-03, -7.99426e-05 +147 2.951209e+03 -5.02714e-03, -7.80841e-05 +148 3.019952e+03 -5.02720e-03, -7.62670e-05 +149 3.090295e+03 -5.02725e-03, -7.44901e-05 +150 3.162278e+03 -5.02731e-03, -7.27528e-05 +151 3.235937e+03 -5.02736e-03, -7.10539e-05 +152 3.311311e+03 -5.02741e-03, -6.93926e-05 +153 3.388442e+03 -5.02746e-03, -6.77680e-05 +154 3.467369e+03 -5.02750e-03, -6.61793e-05 +155 3.548134e+03 -5.02755e-03, -6.46256e-05 +156 3.630781e+03 -5.02759e-03, -6.31061e-05 +157 3.715352e+03 -5.02763e-03, -6.16201e-05 +158 3.801894e+03 -5.02767e-03, -6.01667e-05 +159 3.890451e+03 -5.02770e-03, -5.87451e-05 +160 3.981072e+03 -5.02774e-03, -5.73546e-05 +161 4.073803e+03 -5.02777e-03, -5.59945e-05 +162 4.168694e+03 -5.02780e-03, -5.46641e-05 +163 4.265795e+03 -5.02783e-03, -5.33626e-05 +164 4.365158e+03 -5.02786e-03, -5.20893e-05 +165 4.466836e+03 -5.02789e-03, -5.08437e-05 +166 4.570882e+03 -5.02791e-03, -4.96250e-05 +167 4.677351e+03 -5.02794e-03, -4.84326e-05 +168 4.786301e+03 -5.02796e-03, -4.72658e-05 +169 4.897788e+03 -5.02799e-03, -4.61240e-05 +170 5.011872e+03 -5.02801e-03, -4.50067e-05 + +Index frequency v1#branch +-------------------------------------------------------------------------------- +171 5.128614e+03 -5.02803e-03, -4.39133e-05 +172 5.248075e+03 -5.02805e-03, -4.28431e-05 +173 5.370318e+03 -5.02807e-03, -4.17956e-05 +174 5.495409e+03 -5.02809e-03, -4.07703e-05 +175 5.623413e+03 -5.02810e-03, -3.97665e-05 +176 5.754399e+03 -5.02812e-03, -3.87838e-05 +177 5.888437e+03 -5.02814e-03, -3.78217e-05 +178 6.025596e+03 -5.02815e-03, -3.68796e-05 +179 6.165950e+03 -5.02816e-03, -3.59571e-05 +180 6.309573e+03 -5.02818e-03, -3.50536e-05 +181 6.456542e+03 -5.02819e-03, -3.41687e-05 +182 6.606934e+03 -5.02820e-03, -3.33019e-05 +183 6.760830e+03 -5.02822e-03, -3.24527e-05 +184 6.918310e+03 -5.02823e-03, -3.16208e-05 +185 7.079458e+03 -5.02824e-03, -3.08056e-05 +186 7.244360e+03 -5.02825e-03, -3.00067e-05 +187 7.413102e+03 -5.02826e-03, -2.92237e-05 +188 7.585776e+03 -5.02827e-03, -2.84563e-05 +189 7.762471e+03 -5.02828e-03, -2.77039e-05 +190 7.943282e+03 -5.02829e-03, -2.69662e-05 +191 8.128305e+03 -5.02829e-03, -2.62427e-05 +192 8.317638e+03 -5.02830e-03, -2.55332e-05 +193 8.511380e+03 -5.02831e-03, -2.48373e-05 +194 8.709636e+03 -5.02832e-03, -2.41544e-05 +195 8.912509e+03 -5.02832e-03, -2.34844e-05 +196 9.120108e+03 -5.02833e-03, -2.28269e-05 +197 9.332543e+03 -5.02834e-03, -2.21814e-05 +198 9.549926e+03 -5.02834e-03, -2.15477e-05 +199 9.772372e+03 -5.02835e-03, -2.09254e-05 +200 1.000000e+04 -5.02835e-03, -2.03142e-05 + +* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 12:02:52 2015 +AC Analysis Wed Jul 1 14:20:43 2015 +-------------------------------------------------------------------------------- +Index frequency v2#branch +-------------------------------------------------------------------------------- +0 1.000000e+02 -6.69472e-05, -2.66492e-05 +1 1.023293e+02 -6.74300e-05, -2.62799e-05 +2 1.047129e+02 -6.78993e-05, -2.59073e-05 +3 1.071519e+02 -6.83553e-05, -2.55319e-05 +4 1.096478e+02 -6.87979e-05, -2.51541e-05 +5 1.122018e+02 -6.92273e-05, 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+190 7.943282e+03 4.959886e-01, -1.68185e-04 +191 8.128305e+03 4.959886e-01, -1.71138e-04 +192 8.317638e+03 4.959886e-01, -1.74183e-04 +193 8.511380e+03 4.959885e-01, -1.77320e-04 +194 8.709636e+03 4.959885e-01, -1.80551e-04 +195 8.912509e+03 4.959885e-01, -1.83877e-04 +196 9.120108e+03 4.959885e-01, -1.87302e-04 +197 9.332543e+03 4.959885e-01, -1.90825e-04 +198 9.549926e+03 4.959885e-01, -1.94450e-04 +199 9.772372e+03 4.959885e-01, -1.98177e-04 +200 1.000000e+04 4.959885e-01, -2.02010e-04 + +* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 12:02:52 2015 +AC Analysis Wed Jul 1 14:20:43 2015 +-------------------------------------------------------------------------------- +Index frequency V(4) +-------------------------------------------------------------------------------- +0 1.000000e+02 -8.03793e+00, -4.05191e+00 +1 1.023293e+02 -8.11150e+00, -3.99558e+00 +2 1.047129e+02 -8.18302e+00, -3.93873e+00 +3 1.071519e+02 -8.25249e+00, -3.88145e+00 +4 1.096478e+02 -8.31993e+00, -3.82382e+00 +5 1.122018e+02 -8.38537e+00, -3.76590e+00 +6 1.148154e+02 -8.44882e+00, -3.70777e+00 +7 1.174898e+02 -8.51031e+00, -3.64951e+00 +8 1.202264e+02 -8.56987e+00, -3.59117e+00 +9 1.230269e+02 -8.62752e+00, -3.53282e+00 +10 1.258925e+02 -8.68330e+00, -3.47453e+00 +11 1.288250e+02 -8.73724e+00, -3.41635e+00 +12 1.318257e+02 -8.78938e+00, -3.35833e+00 +13 1.348963e+02 -8.83975e+00, -3.30053e+00 +14 1.380384e+02 -8.88839e+00, -3.24300e+00 +15 1.412538e+02 -8.93534e+00, -3.18577e+00 +16 1.445440e+02 -8.98063e+00, -3.12890e+00 +17 1.479108e+02 -9.02432e+00, -3.07242e+00 +18 1.513561e+02 -9.06643e+00, -3.01638e+00 +19 1.548817e+02 -9.10702e+00, -2.96080e+00 +20 1.584893e+02 -9.14611e+00, -2.90572e+00 +21 1.621810e+02 -9.18376e+00, -2.85116e+00 +22 1.659587e+02 -9.22000e+00, -2.79717e+00 +23 1.698244e+02 -9.25488e+00, -2.74375e+00 +24 1.737801e+02 -9.28843e+00, -2.69093e+00 +25 1.778279e+02 -9.32070e+00, -2.63873e+00 +26 1.819701e+02 -9.35172e+00, -2.58718e+00 +27 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-1.59639e+00 +50 3.162278e+02 -9.81518e+00, -1.56183e+00 +51 3.235937e+02 -9.82603e+00, -1.52794e+00 +52 3.311311e+02 -9.83641e+00, -1.49472e+00 +53 3.388442e+02 -9.84634e+00, -1.46215e+00 +54 3.467369e+02 -9.85585e+00, -1.43023e+00 + +Index frequency V(4) +-------------------------------------------------------------------------------- +55 3.548134e+02 -9.86494e+00, -1.39894e+00 +56 3.630781e+02 -9.87364e+00, -1.36829e+00 +57 3.715352e+02 -9.88196e+00, -1.33825e+00 +58 3.801894e+02 -9.88992e+00, -1.30882e+00 +59 3.890451e+02 -9.89754e+00, -1.28000e+00 +60 3.981072e+02 -9.90482e+00, -1.25176e+00 +61 4.073803e+02 -9.91179e+00, -1.22411e+00 +62 4.168694e+02 -9.91845e+00, -1.19704e+00 +63 4.265795e+02 -9.92482e+00, -1.17052e+00 +64 4.365158e+02 -9.93091e+00, -1.14456e+00 +65 4.466836e+02 -9.93673e+00, -1.11915e+00 +66 4.570882e+02 -9.94230e+00, -1.09427e+00 +67 4.677351e+02 -9.94762e+00, -1.06992e+00 +68 4.786301e+02 -9.95271e+00, -1.04608e+00 +69 4.897788e+02 -9.95757e+00, -1.02275e+00 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-1.00599e+01, -1.40532e-01 +156 3.630781e+03 -1.00600e+01, -1.37237e-01 +157 3.715352e+03 -1.00601e+01, -1.34014e-01 +158 3.801894e+03 -1.00602e+01, -1.30861e-01 +159 3.890451e+03 -1.00602e+01, -1.27779e-01 +160 3.981072e+03 -1.00603e+01, -1.24764e-01 +161 4.073803e+03 -1.00604e+01, -1.21815e-01 +162 4.168694e+03 -1.00604e+01, -1.18930e-01 +163 4.265795e+03 -1.00605e+01, -1.16109e-01 +164 4.365158e+03 -1.00606e+01, -1.13349e-01 +165 4.466836e+03 -1.00606e+01, -1.10649e-01 +166 4.570882e+03 -1.00607e+01, -1.08007e-01 +167 4.677351e+03 -1.00607e+01, -1.05423e-01 +168 4.786301e+03 -1.00608e+01, -1.02895e-01 +169 4.897788e+03 -1.00608e+01, -1.00421e-01 +170 5.011872e+03 -1.00609e+01, -9.80001e-02 + +Index frequency V(4) +-------------------------------------------------------------------------------- +171 5.128614e+03 -1.00609e+01, -9.56314e-02 +172 5.248075e+03 -1.00610e+01, -9.33133e-02 +173 5.370318e+03 -1.00610e+01, -9.10447e-02 +174 5.495409e+03 -1.00611e+01, -8.88243e-02 +175 5.623413e+03 -1.00611e+01, -8.66510e-02 +176 5.754399e+03 -1.00611e+01, -8.45236e-02 +177 5.888437e+03 -1.00612e+01, -8.24410e-02 +178 6.025596e+03 -1.00612e+01, -8.04021e-02 +179 6.165950e+03 -1.00612e+01, -7.84058e-02 +180 6.309573e+03 -1.00613e+01, -7.64510e-02 +181 6.456542e+03 -1.00613e+01, -7.45367e-02 +182 6.606934e+03 -1.00613e+01, -7.26620e-02 +183 6.760830e+03 -1.00613e+01, -7.08257e-02 +184 6.918310e+03 -1.00614e+01, -6.90270e-02 +185 7.079458e+03 -1.00614e+01, -6.72649e-02 +186 7.244360e+03 -1.00614e+01, -6.55384e-02 +187 7.413102e+03 -1.00614e+01, -6.38466e-02 +188 7.585776e+03 -1.00615e+01, -6.21887e-02 +189 7.762471e+03 -1.00615e+01, -6.05638e-02 +190 7.943282e+03 -1.00615e+01, -5.89709e-02 +191 8.128305e+03 -1.00615e+01, -5.74093e-02 +192 8.317638e+03 -1.00615e+01, -5.58782e-02 +193 8.511380e+03 -1.00616e+01, -5.43766e-02 +194 8.709636e+03 -1.00616e+01, -5.29039e-02 +195 8.912509e+03 -1.00616e+01, -5.14592e-02 +196 9.120108e+03 -1.00616e+01, -5.00418e-02 +197 9.332543e+03 -1.00616e+01, -4.86510e-02 +198 9.549926e+03 -1.00616e+01, -4.72859e-02 +199 9.772372e+03 -1.00616e+01, -4.59459e-02 +200 1.000000e+04 -1.00616e+01, -4.46302e-02 + +* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 12:02:52 2015 +AC Analysis Wed Jul 1 14:20:43 2015 +-------------------------------------------------------------------------------- +Index frequency V(5) +-------------------------------------------------------------------------------- +0 1.000000e+02 9.665868e-02, -1.93017e-01 +1 1.023293e+02 9.314515e-02, -1.90338e-01 +2 1.047129e+02 8.972977e-02, -1.87635e-01 +3 1.071519e+02 8.641194e-02, -1.84910e-01 +4 1.096478e+02 8.319092e-02, -1.82168e-01 +5 1.122018e+02 8.006580e-02, -1.79412e-01 +6 1.148154e+02 7.703553e-02, -1.76646e-01 +7 1.174898e+02 7.409891e-02, -1.73874e-01 +8 1.202264e+02 7.125465e-02, -1.71097e-01 +9 1.230269e+02 6.850132e-02, -1.68320e-01 +10 1.258925e+02 6.583742e-02, -1.65546e-01 +11 1.288250e+02 6.326135e-02, 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4.168694e+03 6.864370e-05, -5.78731e-03 +163 4.265795e+03 6.551682e-05, -5.65561e-03 +164 4.365158e+03 6.253063e-05, -5.52691e-03 +165 4.466836e+03 5.967881e-05, -5.40113e-03 +166 4.570882e+03 5.695531e-05, -5.27821e-03 +167 4.677351e+03 5.435436e-05, -5.15810e-03 +168 4.786301e+03 5.187045e-05, -5.04071e-03 +169 4.897788e+03 4.949831e-05, -4.92599e-03 +170 5.011872e+03 4.723291e-05, -4.81389e-03 + +Index frequency V(5) +-------------------------------------------------------------------------------- +171 5.128614e+03 4.506945e-05, -4.70433e-03 +172 5.248075e+03 4.300334e-05, -4.59727e-03 +173 5.370318e+03 4.103021e-05, -4.49264e-03 +174 5.495409e+03 3.914587e-05, -4.39039e-03 +175 5.623413e+03 3.734632e-05, -4.29047e-03 +176 5.754399e+03 3.562775e-05, -4.19282e-03 +177 5.888437e+03 3.398652e-05, -4.09739e-03 +178 6.025596e+03 3.241915e-05, -4.00414e-03 +179 6.165950e+03 3.092231e-05, -3.91301e-03 +180 6.309573e+03 2.949284e-05, -3.82395e-03 +181 6.456542e+03 2.812769e-05, -3.73691e-03 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-1.00601e+01, -1.29251e-01 +156 3.630781e+03 -1.00601e+01, -1.26212e-01 +157 3.715352e+03 -1.00602e+01, -1.23240e-01 +158 3.801894e+03 -1.00603e+01, -1.20333e-01 +159 3.890451e+03 -1.00604e+01, -1.17490e-01 +160 3.981072e+03 -1.00604e+01, -1.14709e-01 +161 4.073803e+03 -1.00605e+01, -1.11989e-01 +162 4.168694e+03 -1.00606e+01, -1.09328e-01 +163 4.265795e+03 -1.00606e+01, -1.06725e-01 +164 4.365158e+03 -1.00607e+01, -1.04178e-01 +165 4.466836e+03 -1.00607e+01, -1.01687e-01 +166 4.570882e+03 -1.00608e+01, -9.92494e-02 +167 4.677351e+03 -1.00608e+01, -9.68646e-02 +168 4.786301e+03 -1.00609e+01, -9.45310e-02 +169 4.897788e+03 -1.00609e+01, -9.22475e-02 +170 5.011872e+03 -1.00610e+01, -9.00129e-02 + +Index frequency V(7) +-------------------------------------------------------------------------------- +171 5.128614e+03 -1.00610e+01, -8.78259e-02 +172 5.248075e+03 -1.00611e+01, -8.56855e-02 +173 5.370318e+03 -1.00611e+01, -8.35905e-02 +174 5.495409e+03 -1.00611e+01, -8.15398e-02 +175 5.623413e+03 -1.00612e+01, -7.95322e-02 +176 5.754399e+03 -1.00612e+01, -7.75669e-02 +177 5.888437e+03 -1.00612e+01, -7.56426e-02 +178 6.025596e+03 -1.00613e+01, -7.37584e-02 +179 6.165950e+03 -1.00613e+01, -7.19133e-02 +180 6.309573e+03 -1.00613e+01, -7.01063e-02 +181 6.456542e+03 -1.00613e+01, -6.83364e-02 +182 6.606934e+03 -1.00614e+01, -6.66028e-02 +183 6.760830e+03 -1.00614e+01, -6.49044e-02 +184 6.918310e+03 -1.00614e+01, -6.32405e-02 +185 7.079458e+03 -1.00614e+01, -6.16101e-02 +186 7.244360e+03 -1.00615e+01, -6.00123e-02 +187 7.413102e+03 -1.00615e+01, -5.84463e-02 +188 7.585776e+03 -1.00615e+01, -5.69113e-02 +189 7.762471e+03 -1.00615e+01, -5.54065e-02 +190 7.943282e+03 -1.00615e+01, -5.39310e-02 +191 8.128305e+03 -1.00615e+01, -5.24842e-02 +192 8.317638e+03 -1.00616e+01, -5.10651e-02 +193 8.511380e+03 -1.00616e+01, -4.96731e-02 +194 8.709636e+03 -1.00616e+01, -4.83074e-02 +195 8.912509e+03 -1.00616e+01, -4.69674e-02 +196 9.120108e+03 -1.00616e+01, -4.56522e-02 +197 9.332543e+03 -1.00616e+01, -4.43613e-02 +198 9.549926e+03 -1.00616e+01, -4.30938e-02 +199 9.772372e+03 -1.00617e+01, -4.18492e-02 +200 1.000000e+04 -1.00617e+01, -4.06268e-02 + +* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 12:02:52 2015 +AC Analysis Wed Jul 1 14:20:43 2015 +-------------------------------------------------------------------------------- +Index frequency V(8) +-------------------------------------------------------------------------------- +0 1.000000e+02 4.955923e-01, 1.331284e-03 +1 1.023293e+02 4.956067e-01, 1.307887e-03 +2 1.047129e+02 4.956206e-01, 1.284670e-03 +3 1.071519e+02 4.956342e-01, 1.261643e-03 +4 1.096478e+02 4.956473e-01, 1.238815e-03 +5 1.122018e+02 4.956601e-01, 1.216194e-03 +6 1.148154e+02 4.956725e-01, 1.193789e-03 +7 1.174898e+02 4.956845e-01, 1.171606e-03 +8 1.202264e+02 4.956961e-01, 1.149654e-03 +9 1.230269e+02 4.957073e-01, 1.127940e-03 +10 1.258925e+02 4.957182e-01, 1.106469e-03 +11 1.288250e+02 4.957287e-01, 1.085247e-03 +12 1.318257e+02 4.957389e-01, 1.064280e-03 +13 1.348963e+02 4.957487e-01, 1.043572e-03 +14 1.380384e+02 4.957582e-01, 1.023129e-03 +15 1.412538e+02 4.957674e-01, 1.002954e-03 +16 1.445440e+02 4.957762e-01, 9.830513e-04 +17 1.479108e+02 4.957847e-01, 9.634231e-04 +18 1.513561e+02 4.957929e-01, 9.440725e-04 +19 1.548817e+02 4.958008e-01, 9.250018e-04 +20 1.584893e+02 4.958085e-01, 9.062128e-04 +21 1.621810e+02 4.958158e-01, 8.877070e-04 +22 1.659587e+02 4.958229e-01, 8.694856e-04 +23 1.698244e+02 4.958297e-01, 8.515491e-04 +24 1.737801e+02 4.958362e-01, 8.338980e-04 +25 1.778279e+02 4.958425e-01, 8.165324e-04 +26 1.819701e+02 4.958486e-01, 7.994520e-04 +27 1.862087e+02 4.958544e-01, 7.826562e-04 +28 1.905461e+02 4.958600e-01, 7.661441e-04 +29 1.949845e+02 4.958653e-01, 7.499147e-04 +30 1.995262e+02 4.958705e-01, 7.339666e-04 +31 2.041738e+02 4.958754e-01, 7.182982e-04 +32 2.089296e+02 4.958802e-01, 7.029077e-04 +33 2.137962e+02 4.958847e-01, 6.877930e-04 +34 2.187762e+02 4.958891e-01, 6.729520e-04 +35 2.238721e+02 4.958933e-01, 6.583822e-04 +36 2.290868e+02 4.958973e-01, 6.440810e-04 +37 2.344229e+02 4.959012e-01, 6.300459e-04 +38 2.398833e+02 4.959049e-01, 6.162740e-04 +39 2.454709e+02 4.959085e-01, 6.027622e-04 +40 2.511886e+02 4.959119e-01, 5.895076e-04 +41 2.570396e+02 4.959151e-01, 5.765069e-04 +42 2.630268e+02 4.959182e-01, 5.637569e-04 +43 2.691535e+02 4.959212e-01, 5.512543e-04 +44 2.754229e+02 4.959241e-01, 5.389956e-04 +45 2.818383e+02 4.959268e-01, 5.269774e-04 +46 2.884032e+02 4.959295e-01, 5.151961e-04 +47 2.951209e+02 4.959320e-01, 5.036481e-04 +48 3.019952e+02 4.959344e-01, 4.923299e-04 +49 3.090295e+02 4.959367e-01, 4.812378e-04 +50 3.162278e+02 4.959389e-01, 4.703681e-04 +51 3.235937e+02 4.959410e-01, 4.597172e-04 +52 3.311311e+02 4.959431e-01, 4.492813e-04 +53 3.388442e+02 4.959450e-01, 4.390568e-04 +54 3.467369e+02 4.959469e-01, 4.290399e-04 + +Index frequency V(8) +-------------------------------------------------------------------------------- +55 3.548134e+02 4.959486e-01, 4.192270e-04 +56 3.630781e+02 4.959503e-01, 4.096143e-04 +57 3.715352e+02 4.959519e-01, 4.001982e-04 +58 3.801894e+02 4.959535e-01, 3.909750e-04 +59 3.890451e+02 4.959550e-01, 3.819410e-04 +60 3.981072e+02 4.959564e-01, 3.730927e-04 +61 4.073803e+02 4.959578e-01, 3.644265e-04 +62 4.168694e+02 4.959591e-01, 3.559387e-04 +63 4.265795e+02 4.959603e-01, 3.476258e-04 +64 4.365158e+02 4.959615e-01, 3.394843e-04 +65 4.466836e+02 4.959626e-01, 3.315108e-04 +66 4.570882e+02 4.959637e-01, 3.237017e-04 +67 4.677351e+02 4.959647e-01, 3.160538e-04 +68 4.786301e+02 4.959657e-01, 3.085635e-04 +69 4.897788e+02 4.959667e-01, 3.012277e-04 +70 5.011872e+02 4.959676e-01, 2.940430e-04 +71 5.128614e+02 4.959685e-01, 2.870061e-04 +72 5.248075e+02 4.959693e-01, 2.801138e-04 +73 5.370318e+02 4.959701e-01, 2.733631e-04 +74 5.495409e+02 4.959708e-01, 2.667507e-04 +75 5.623413e+02 4.959716e-01, 2.602737e-04 +76 5.754399e+02 4.959723e-01, 2.539289e-04 +77 5.888437e+02 4.959729e-01, 2.477134e-04 +78 6.025596e+02 4.959735e-01, 2.416242e-04 +79 6.165950e+02 4.959741e-01, 2.356585e-04 +80 6.309573e+02 4.959747e-01, 2.298133e-04 +81 6.456542e+02 4.959753e-01, 2.240860e-04 +82 6.606934e+02 4.959758e-01, 2.184736e-04 +83 6.760830e+02 4.959763e-01, 2.129735e-04 +84 6.918310e+02 4.959768e-01, 2.075830e-04 +85 7.079458e+02 4.959772e-01, 2.022995e-04 +86 7.244360e+02 4.959777e-01, 1.971203e-04 +87 7.413102e+02 4.959781e-01, 1.920430e-04 +88 7.585776e+02 4.959785e-01, 1.870649e-04 +89 7.762471e+02 4.959789e-01, 1.821837e-04 +90 7.943282e+02 4.959792e-01, 1.773969e-04 +91 8.128305e+02 4.959796e-01, 1.727020e-04 +92 8.317638e+02 4.959799e-01, 1.680968e-04 +93 8.511380e+02 4.959802e-01, 1.635790e-04 +94 8.709636e+02 4.959806e-01, 1.591462e-04 +95 8.912509e+02 4.959808e-01, 1.547962e-04 +96 9.120108e+02 4.959811e-01, 1.505268e-04 +97 9.332543e+02 4.959814e-01, 1.463359e-04 +98 9.549926e+02 4.959816e-01, 1.422213e-04 +99 9.772372e+02 4.959819e-01, 1.381809e-04 +100 1.000000e+03 4.959821e-01, 1.342127e-04 +101 1.023293e+03 4.959823e-01, 1.303146e-04 +102 1.047129e+03 4.959825e-01, 1.264846e-04 +103 1.071519e+03 4.959827e-01, 1.227208e-04 +104 1.096478e+03 4.959829e-01, 1.190212e-04 +105 1.122018e+03 4.959831e-01, 1.153839e-04 +106 1.148154e+03 4.959833e-01, 1.118071e-04 +107 1.174898e+03 4.959835e-01, 1.082889e-04 +108 1.202264e+03 4.959836e-01, 1.048274e-04 +109 1.230269e+03 4.959838e-01, 1.014209e-04 +110 1.258925e+03 4.959839e-01, 9.806769e-05 +111 1.288250e+03 4.959841e-01, 9.476592e-05 +112 1.318257e+03 4.959842e-01, 9.151390e-05 + +Index frequency V(8) +-------------------------------------------------------------------------------- +113 1.348963e+03 4.959843e-01, 8.830995e-05 +114 1.380384e+03 4.959844e-01, 8.515240e-05 +115 1.412538e+03 4.959846e-01, 8.203961e-05 +116 1.445440e+03 4.959847e-01, 7.896994e-05 +117 1.479108e+03 4.959848e-01, 7.594180e-05 +118 1.513561e+03 4.959849e-01, 7.295361e-05 +119 1.548817e+03 4.959850e-01, 7.000380e-05 +120 1.584893e+03 4.959851e-01, 6.709082e-05 +121 1.621810e+03 4.959852e-01, 6.421315e-05 +122 1.659587e+03 4.959852e-01, 6.136929e-05 +123 1.698244e+03 4.959853e-01, 5.855774e-05 +124 1.737801e+03 4.959854e-01, 5.577702e-05 +125 1.778279e+03 4.959855e-01, 5.302568e-05 +126 1.819701e+03 4.959855e-01, 5.030227e-05 +127 1.862087e+03 4.959856e-01, 4.760536e-05 +128 1.905461e+03 4.959857e-01, 4.493353e-05 +129 1.949845e+03 4.959857e-01, 4.228537e-05 +130 1.995262e+03 4.959858e-01, 3.965949e-05 +131 2.041738e+03 4.959858e-01, 3.705450e-05 +132 2.089296e+03 4.959859e-01, 3.446905e-05 +133 2.137962e+03 4.959859e-01, 3.190175e-05 +134 2.187762e+03 4.959860e-01, 2.935126e-05 +135 2.238721e+03 4.959860e-01, 2.681624e-05 +136 2.290868e+03 4.959861e-01, 2.429534e-05 +137 2.344229e+03 4.959861e-01, 2.178723e-05 +138 2.398833e+03 4.959862e-01, 1.929060e-05 +139 2.454709e+03 4.959862e-01, 1.680412e-05 +140 2.511886e+03 4.959862e-01, 1.432647e-05 +141 2.570396e+03 4.959863e-01, 1.185636e-05 +142 2.630268e+03 4.959863e-01, 9.392476e-06 +143 2.691535e+03 4.959863e-01, 6.933512e-06 +144 2.754229e+03 4.959864e-01, 4.478170e-06 +145 2.818383e+03 4.959864e-01, 2.025154e-06 +146 2.884032e+03 4.959864e-01, -4.26836e-07 +147 2.951209e+03 4.959865e-01, -2.87909e-06 +148 3.019952e+03 4.959865e-01, -5.33292e-06 +149 3.090295e+03 4.959865e-01, -7.78961e-06 +150 3.162278e+03 4.959865e-01, -1.02505e-05 +151 3.235937e+03 4.959865e-01, -1.27168e-05 +152 3.311311e+03 4.959866e-01, -1.51899e-05 +153 3.388442e+03 4.959866e-01, -1.76711e-05 +154 3.467369e+03 4.959866e-01, -2.01617e-05 +155 3.548134e+03 4.959866e-01, -2.26629e-05 +156 3.630781e+03 4.959866e-01, -2.51763e-05 +157 3.715352e+03 4.959867e-01, -2.77030e-05 +158 3.801894e+03 4.959867e-01, -3.02444e-05 +159 3.890451e+03 4.959867e-01, -3.28019e-05 +160 3.981072e+03 4.959867e-01, -3.53767e-05 +161 4.073803e+03 4.959867e-01, -3.79704e-05 +162 4.168694e+03 4.959867e-01, -4.05842e-05 +163 4.265795e+03 4.959867e-01, -4.32195e-05 +164 4.365158e+03 4.959868e-01, -4.58778e-05 +165 4.466836e+03 4.959868e-01, -4.85604e-05 +166 4.570882e+03 4.959868e-01, -5.12687e-05 +167 4.677351e+03 4.959868e-01, -5.40043e-05 +168 4.786301e+03 4.959868e-01, -5.67685e-05 +169 4.897788e+03 4.959868e-01, -5.95628e-05 +170 5.011872e+03 4.959868e-01, -6.23887e-05 + +Index frequency V(8) +-------------------------------------------------------------------------------- +171 5.128614e+03 4.959868e-01, -6.52476e-05 +172 5.248075e+03 4.959868e-01, -6.81412e-05 +173 5.370318e+03 4.959868e-01, -7.10709e-05 +174 5.495409e+03 4.959868e-01, -7.40384e-05 +175 5.623413e+03 4.959868e-01, -7.70450e-05 +176 5.754399e+03 4.959868e-01, -8.00925e-05 +177 5.888437e+03 4.959869e-01, -8.31825e-05 +178 6.025596e+03 4.959869e-01, -8.63167e-05 +179 6.165950e+03 4.959869e-01, -8.94965e-05 +180 6.309573e+03 4.959869e-01, -9.27239e-05 +181 6.456542e+03 4.959869e-01, -9.60004e-05 +182 6.606934e+03 4.959869e-01, -9.93278e-05 +183 6.760830e+03 4.959869e-01, -1.02708e-04 +184 6.918310e+03 4.959869e-01, -1.06142e-04 +185 7.079458e+03 4.959869e-01, -1.09633e-04 +186 7.244360e+03 4.959869e-01, -1.13182e-04 +187 7.413102e+03 4.959869e-01, -1.16791e-04 +188 7.585776e+03 4.959869e-01, -1.20462e-04 +189 7.762471e+03 4.959869e-01, -1.24197e-04 +190 7.943282e+03 4.959869e-01, -1.27997e-04 +191 8.128305e+03 4.959869e-01, -1.31866e-04 +192 8.317638e+03 4.959869e-01, -1.35804e-04 +193 8.511380e+03 4.959869e-01, -1.39815e-04 +194 8.709636e+03 4.959869e-01, -1.43899e-04 +195 8.912509e+03 4.959869e-01, -1.48060e-04 +196 9.120108e+03 4.959869e-01, -1.52299e-04 +197 9.332543e+03 4.959869e-01, -1.56620e-04 +198 9.549926e+03 4.959869e-01, -1.61023e-04 +199 9.772372e+03 4.959869e-01, -1.65511e-04 +200 1.000000e+04 4.959869e-01, -1.70087e-04 diff --git a/Examples/BasicGates/$savepcb.brd b/Examples/BasicGates/$savepcb.brd new file mode 100644 index 00000000..c5b62f89 --- /dev/null +++ b/Examples/BasicGates/$savepcb.brd @@ -0,0 +1,84 @@ +PCBNEW-BOARD Version 1 date 6/7/2013 11:31:39 AM
+
+# Created by Pcbnew(2011-04-29 BZR 2986)-stable
+
+$GENERAL
+encoding utf-8
+LayerCount 2
+Ly 1FFF8001
+EnabledLayers 1FFF8001
+Links 0
+NoConn 0
+Di 0 0 117000 82670
+Ndraw 0
+Ntrack 0
+Nzone 0
+BoardThickness 630
+Nmodule 0
+Nnets 1
+$EndGENERAL
+
+$SHEETDESCR
+Sheet A4 11700 8267
+Title ""
+Date "7 jun 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndSHEETDESCR
+
+$SETUP
+InternalUnit 0.000100 INCH
+Layers 2
+Layer[0] Back signal
+Layer[15] Front signal
+TrackWidth 80
+TrackClearence 100
+ZoneClearence 200
+TrackMinWidth 80
+DrawSegmWidth 150
+EdgeSegmWidth 150
+ViaSize 350
+ViaDrill 250
+ViaMinSize 350
+ViaMinDrill 200
+MicroViaSize 200
+MicroViaDrill 50
+MicroViasAllowed 0
+MicroViaMinSize 200
+MicroViaMinDrill 50
+TextPcbWidth 120
+TextPcbSize 600 800
+EdgeModWidth 150
+TextModSize 600 600
+TextModWidth 120
+PadSize 600 600
+PadDrill 320
+Pad2MaskClearance 100
+AuxiliaryAxisOrg 0 0
+PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory ""))
+$EndSETUP
+
+$EQUIPOT
+Na 0 ""
+St ~
+$EndEQUIPOT
+$NCLASS
+Name "Default"
+Desc "This is the default net class."
+Clearance 100
+TrackWidth 80
+ViaDia 350
+ViaDrill 250
+uViaDia 200
+uViaDrill 50
+AddNet ""
+$EndNCLASS
+$TRACK
+$EndTRACK
+$ZONE
+$EndZONE
+$EndBOARD
diff --git a/Examples/BasicGates/BasicGates-cache.bak b/Examples/BasicGates/BasicGates-cache.bak new file mode 100644 index 00000000..ba5e5f27 --- /dev/null +++ b/Examples/BasicGates/BasicGates-cache.bak @@ -0,0 +1,324 @@ +EESchema-LIBRARY Version 2.3 Date: Sunday 09 December 2012 08:00:09 AM IST +#encoding utf-8 +# +# 74HCT04 +# +DEF 74HCT04 U 0 30 Y Y 6 F N +F0 "U" 150 100 40 H V C CNN +F1 "74HCT04" 200 -100 40 H V C CNN +ALIAS 74HC14 74HC04 74LS14 +DRAW +P 4 0 0 0 -150 150 -150 -150 150 0 -150 150 N +X GND 7 -50 -100 0 U 30 20 0 0 W N +X VCC 14 -50 100 0 D 30 20 0 0 W N +X ~ 1 -450 0 300 R 60 60 1 1 I +X ~ 2 450 0 300 L 60 60 1 1 O I +X ~ 3 -450 0 300 R 60 60 2 1 I +X ~ 4 450 0 300 L 60 60 2 1 O I +X ~ 5 -450 0 300 R 60 60 3 1 I +X ~ 6 450 0 300 L 60 60 3 1 O I +X ~ 8 450 0 300 L 60 60 4 1 O I +X ~ 9 -450 0 300 R 60 60 4 1 I +X ~ 10 450 0 300 L 60 60 5 1 O I +X ~ 11 -450 0 300 R 60 60 5 1 I +X ~ 12 450 0 300 L 60 60 6 1 O I +X ~ 13 -450 0 300 R 60 60 6 1 I +X ~ 1 -450 0 300 R 60 60 1 2 I I +X ~ 2 450 0 300 L 60 60 1 2 O +X ~ 3 -450 0 300 R 60 60 2 2 I I +X ~ 4 450 0 300 L 60 60 2 2 O +X ~ 5 -450 0 300 R 60 60 3 2 I I +X ~ 6 450 0 300 L 60 60 3 2 O +X ~ 8 450 0 300 L 60 60 4 2 O +X ~ 9 -450 0 300 R 60 60 4 2 I I +X ~ 10 450 0 300 L 60 60 5 2 O +X ~ 11 -450 0 300 R 60 60 5 2 I I +X ~ 12 450 0 300 L 60 60 6 2 O +X ~ 13 -450 0 300 R 60 60 6 2 I I +ENDDRAW +ENDDEF +# +# 74LS00 +# +DEF 74LS00 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS00" 0 -100 60 H V C CNN +ALIAS 74LS37 7400 74HCT00 74HC00 +$FPLIST + 14DIP300* + SO14* +$ENDFPLIST +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 D 40 40 0 0 W N +A 100 0 200 -899 899 0 1 0 N 100 -200 100 200 +P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 -600 100 300 R 60 60 1 1 I +X ~ 2 -600 -100 300 R 60 60 1 1 I +X ~ 3 600 0 300 L 60 60 1 1 O I +X ~ 4 -600 100 300 R 60 60 2 1 I +X ~ 5 -600 -100 300 R 60 60 2 1 I +X ~ 6 600 0 300 L 60 60 2 1 O I +X ~ 8 600 0 300 L 60 60 3 1 O I +X ~ 9 -600 100 300 R 60 60 3 1 I +X ~ 10 -600 -100 300 R 60 60 3 1 I +X ~ 11 600 0 300 L 60 60 4 1 O I +X ~ 12 -600 100 300 R 60 60 4 1 I +X ~ 13 -600 -100 300 R 60 60 4 1 I +A -465 0 259 504 -504 0 2 0 N -300 200 -300 -200 +A -11 143 343 -881 -246 0 2 0 N 0 -200 300 0 +A -10 -141 340 244 883 0 2 0 N 300 0 0 200 +P 2 0 2 0 -300 -200 0 -200 N +P 2 0 2 0 -300 200 0 200 N +X ~ 1 -600 100 370 R 60 60 1 2 I I +X ~ 2 -600 -100 370 R 60 60 1 2 I I +X ~ 3 600 0 300 L 60 60 1 2 O +X ~ 4 -600 100 370 R 60 60 2 2 I I +X ~ 5 -600 -100 370 R 60 60 2 2 I I +X ~ 6 600 0 300 L 60 60 2 2 O +X ~ 8 600 0 300 L 60 60 3 2 O +X ~ 9 -600 100 370 R 60 60 3 2 I I +X ~ 10 -600 -100 370 R 60 60 3 2 I I +X ~ 11 600 0 300 L 60 60 4 2 O +X ~ 12 -600 100 370 R 60 60 4 2 I I +X ~ 13 -600 -100 370 R 60 60 4 2 I I +ENDDRAW +ENDDEF +# +# 74LS02 +# +DEF 74LS02 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS02" 50 -50 60 H V C CNN +ALIAS 74HC02 74HCT02 7402 74LS28 +$FPLIST + SO14* + 14DIP* +$ENDFPLIST +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 D 40 40 0 0 W N +A -470 0 262 496 -496 0 1 8 N -300 200 -300 -200 +A -1 -127 327 898 228 0 1 8 N 0 200 300 0 +A -1 128 327 -230 -898 0 1 8 N 300 0 0 -200 +P 2 0 1 8 -300 -200 0 -200 N +P 2 0 1 8 -300 200 0 200 N +X ~ 1 600 0 300 L 60 60 1 1 O I +X ~ 2 -600 100 370 R 60 60 1 1 I +X ~ 3 -600 -100 370 R 60 60 1 1 I +X ~ 4 600 0 300 L 60 60 2 1 O I +X ~ 5 -600 100 370 R 60 60 2 1 I +X ~ 6 -600 -100 370 R 60 60 2 1 I +X ~ 8 -600 100 370 R 60 60 3 1 I +X ~ 9 -600 -100 370 R 60 60 3 1 I +X ~ 10 600 0 300 L 60 60 3 1 O I +X ~ 11 -600 100 370 R 60 60 4 1 I +X ~ 12 -600 -100 370 R 60 60 4 1 I +X ~ 13 600 0 300 L 60 60 4 1 O I +A 100 0 200 896 -896 0 2 8 N 101 200 101 -199 +P 4 0 2 8 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 600 0 300 L 60 60 1 2 O +X ~ 2 -600 100 300 R 60 60 1 2 I I +X ~ 3 -600 -100 300 R 60 60 1 2 I I +X ~ 4 600 0 300 L 60 60 2 2 O +X ~ 5 -600 100 300 R 60 60 2 2 I I +X ~ 6 -600 -100 300 R 60 60 2 2 I I +X ~ 8 -600 100 300 R 60 60 3 2 I I +X ~ 9 -600 -100 300 R 60 60 3 2 I I +X ~ 10 600 0 300 L 60 60 3 2 O +X ~ 11 -600 100 300 R 60 60 4 2 I I +X ~ 12 -600 -100 300 R 60 60 4 2 I I +X ~ 13 600 0 300 L 60 60 4 2 O +ENDDRAW +ENDDEF +# +# 74LS08 +# +DEF 74LS08 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS08" 0 -50 60 H V C CNN +ALIAS 74LS09 +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 U 40 40 0 0 W N +A 100 0 200 896 -896 0 1 0 N 101 200 101 -199 +P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 -600 100 300 R 60 60 1 1 I +X ~ 2 -600 -100 300 R 60 60 1 1 I +X ~ 3 600 0 300 L 60 60 1 1 O +X ~ 4 -600 100 300 R 60 60 2 1 I +X ~ 5 -600 -100 300 R 60 60 2 1 I +X ~ 6 600 0 300 L 60 60 2 1 O +X ~ 8 600 0 300 L 60 60 3 1 O +X ~ 9 -600 100 300 R 60 60 3 1 I +X ~ 10 -600 -100 300 R 60 60 3 1 I +X ~ 11 600 0 300 L 60 60 4 1 O +X ~ 12 -600 100 300 R 60 60 4 1 I +X ~ 13 -600 -100 300 R 60 60 4 1 I +A -470 0 262 495 -495 0 2 0 N -300 199 -300 -198 +A -2 126 326 -897 -225 0 2 0 N 0 -199 299 2 +A 4 -120 320 906 221 0 2 0 N 2 200 300 0 +P 2 0 2 0 -300 -200 0 -200 N +P 2 0 2 0 -300 200 0 200 N +X ~ 1 -600 100 370 R 60 60 1 2 I I +X ~ 2 -600 -100 370 R 60 60 1 2 I I +X ~ 3 600 0 300 L 60 60 1 2 O I +X ~ 4 -600 100 370 R 60 60 2 2 I I +X ~ 5 -600 -100 370 R 60 60 2 2 I I +X ~ 6 600 0 300 L 60 60 2 2 O I +X ~ 8 600 0 300 L 60 60 3 2 O I +X ~ 9 -600 100 370 R 60 60 3 2 I I +X ~ 10 -600 -100 370 R 60 60 3 2 I I +X ~ 11 600 0 300 L 60 60 4 2 O I +X ~ 12 -600 100 370 R 60 60 4 2 I I +X ~ 13 -600 -100 370 R 60 60 4 2 I I +ENDDRAW +ENDDEF +# +# 74LS32 +# +DEF 74LS32 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS32" 0 -50 60 H V C CNN +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 U 40 40 0 0 W N +A -470 0 262 495 -495 0 1 0 N -300 199 -300 -198 +A -2 126 326 -897 -225 0 1 0 N 0 -199 299 2 +A 4 -120 320 906 221 0 1 0 N 2 200 300 0 +P 2 0 1 0 -300 -200 0 -200 N +P 2 0 1 0 -300 200 0 200 N +X ~ 1 -600 100 370 R 60 60 1 1 I +X ~ 2 -600 -100 370 R 60 60 1 1 I +X ~ 3 600 0 300 L 60 60 1 1 O +X ~ 4 -600 100 370 R 60 60 2 1 I +X ~ 5 -600 -100 370 R 60 60 2 1 I +X ~ 6 600 0 300 L 60 60 2 1 O +X ~ 8 600 0 300 L 60 60 3 1 O +X ~ 9 -600 100 370 R 60 60 3 1 I +X ~ 10 -600 -100 370 R 60 60 3 1 I +X ~ 11 600 0 300 L 60 60 4 1 O +X ~ 12 -600 100 370 R 60 60 4 1 I +X ~ 13 -600 -100 370 R 60 60 4 1 I +A 100 0 200 896 -896 0 2 0 N 101 200 101 -199 +P 4 0 2 0 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 -600 100 300 R 60 60 1 2 I I +X ~ 2 -600 -100 300 R 60 60 1 2 I I +X ~ 3 600 0 300 L 60 60 1 2 O I +X ~ 4 -600 100 300 R 60 60 2 2 I I +X ~ 5 -600 -100 300 R 60 60 2 2 I I +X ~ 6 600 0 300 L 60 60 2 2 O I +X ~ 8 600 0 300 L 60 60 3 2 O I +X ~ 9 -600 100 300 R 60 60 3 2 I I +X ~ 10 -600 -100 300 R 60 60 3 2 I I +X ~ 11 600 0 300 L 60 60 4 2 O I +X ~ 12 -600 100 300 R 60 60 4 2 I I +X ~ 13 -600 -100 300 R 60 60 4 2 I I +ENDDRAW +ENDDEF +# +# 74LS86 +# +DEF 74LS86 U 0 30 Y N 4 F N +F0 "U" 50 50 50 H V C CNN +F1 "74LS86" 50 -50 40 H V C CNN +ALIAS 74HC86 +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 D 40 40 0 0 W N +A -470 0 262 495 -495 0 1 0 N -300 199 -300 -198 +A -396 -2 281 457 -451 0 1 0 N -200 199 -198 -200 +A -2 126 326 -897 -225 0 1 0 N 0 -199 299 2 +A 4 -120 320 906 221 0 1 0 N 2 200 300 0 +P 2 0 1 0 -200 -200 0 -200 N +P 2 0 1 0 -200 200 0 200 N +X IN1 1 -600 100 370 R 60 60 1 1 I +X IN2 2 -600 -100 370 R 60 60 1 1 I +X OUT 3 600 0 300 L 60 60 1 1 O +X IN1 4 -600 100 370 R 60 60 2 1 I +X IN2 5 -600 -100 370 R 60 60 2 1 I +X OUT 6 600 0 300 L 60 60 2 1 O +X OUT 8 600 0 300 L 60 60 3 1 O +X IN1 9 -600 100 370 R 60 60 3 1 I +X IN2 10 -600 -100 370 R 60 60 3 1 I +X OUT 11 600 0 300 L 60 60 4 1 O +X IN1 12 -600 100 370 R 60 60 4 1 I +X IN2 13 -600 -100 370 R 60 60 4 1 I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot1 +# +DEF vplot1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/BasicGates/BasicGates-cache.lib b/Examples/BasicGates/BasicGates-cache.lib new file mode 100644 index 00000000..f71daa19 --- /dev/null +++ b/Examples/BasicGates/BasicGates-cache.lib @@ -0,0 +1,207 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_2 +# +DEF adc_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_2" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -100 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT2 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/BasicGates/BasicGates.bak b/Examples/BasicGates/BasicGates.bak new file mode 100644 index 00000000..050f6d4a --- /dev/null +++ b/Examples/BasicGates/BasicGates.bak @@ -0,0 +1,347 @@ +EESchema Schematic File Version 2 date Sunday 09 December 2012 08:37:05 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:BasicGates-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "9 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VPLOT8_1 U1 +U 3 1 50C3FFE2 +P 9700 2500 +F 0 "U1" H 9550 2600 50 0000 C CNN +F 1 "VPLOT8_1" H 9850 2600 50 0000 C CNN + 3 9700 2500 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 50C3FFDB +P 2400 3300 +F 0 "U1" H 2250 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 3400 50 0000 C CNN + 2 2400 3300 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50C3FFD3 +P 2400 1250 +F 0 "U1" H 2250 1350 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 1350 50 0000 C CNN + 1 2400 1250 + 1 0 0 -1 +$EndComp +Connection ~ 9700 3000 +Wire Wire Line + 9700 3000 9700 2800 +Wire Wire Line + 9900 3100 9900 3000 +Wire Wire Line + 9900 3000 9100 3000 +Wire Wire Line + 1700 3800 3750 3800 +Wire Wire Line + 7900 3100 7850 3100 +Wire Wire Line + 7850 3100 7850 3400 +Wire Wire Line + 7850 3400 7750 3400 +Connection ~ 5300 2300 +Wire Wire Line + 5300 2300 5300 3300 +Wire Wire Line + 5300 3300 5500 3300 +Wire Wire Line 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3600 3750 3600 +Wire Wire Line + 3750 3600 3750 3800 +Wire Wire Line + 3500 3800 3500 2400 +Wire Wire Line + 3500 2400 3850 2400 +Connection ~ 3500 3800 +Wire Wire Line + 5050 2300 5800 2300 +Wire Wire Line + 6200 2200 6200 1900 +Wire Wire Line + 5800 2500 5200 2500 +Wire Wire Line + 5200 2500 5200 3500 +Connection ~ 5200 3500 +Wire Wire Line + 6700 3400 6850 3400 +Wire Wire Line + 1750 1700 3650 1700 +Wire Wire Line + 9900 3600 9900 3900 +Text Notes 9150 2850 0 60 ~ 0 +~A.B +Text Notes 9050 2850 0 60 ~ 0 ++ +Text Notes 8900 2850 0 60 ~ 0 +A.B +Text Notes 8000 2300 0 60 ~ 0 +~B +Text Notes 7900 2300 0 60 ~ 0 ++ +Text Notes 7750 2300 0 60 ~ 0 +=~A +Text Notes 7900 3650 0 60 ~ 0 +=A+B +Text Notes 7850 3500 0 60 ~ 0 +A.B+A+B +Text Notes 6450 3600 0 60 ~ 0 +~((A.B)+(A+B)) +Text Notes 7100 2300 0 60 ~ 0 +~((A.B).(A+B)) +$Comp +L 74HC86 U12 +U 1 1 507253B2 +P 8500 3000 +F 0 "U12" H 8550 3050 50 0000 C CNN +F 1 "74HC86" H 8550 2950 40 0000 C CNN + 1 8500 3000 + 1 0 0 -1 +$EndComp +Text Notes 5150 3650 0 60 ~ 0 +A+B +Text Notes 5100 2250 0 60 ~ 0 +A.B +Text Notes 3600 3950 0 60 ~ 0 +B +Text Notes 3500 1650 0 60 ~ 0 +A +$Comp +L 74LS32 U8 +U 1 1 50725446 +P 4500 3500 +F 0 "U8" H 4500 3550 60 0000 C CNN +F 1 "74LS32" H 4500 3450 60 0000 C CNN + 1 4500 3500 + 1 0 0 -1 +$EndComp +$Comp +L 74LS08 U7 +U 1 1 50725428 +P 4450 2300 +F 0 "U7" H 4450 2350 60 0000 C CNN +F 1 "74LS08" H 4450 2250 60 0000 C CNN + 1 4450 2300 + 1 0 0 -1 +$EndComp +$Comp +L 74HC02 U9 +U 1 1 50725415 +P 6100 3400 +F 0 "U9" H 6100 3450 60 0000 C CNN +F 1 "74HC02" H 6150 3350 60 0000 C CNN + 1 6100 3400 + 1 0 0 -1 +$EndComp +$Comp +L 74HC04 U11 +U 1 1 507253DF +P 7300 3400 +F 0 "U11" H 7450 3500 40 0000 C CNN +F 1 "74HC04" H 7500 3300 40 0000 C CNN + 1 7300 3400 + 1 0 0 -1 +$EndComp +$Comp +L 7400 U10 +U 1 1 5072539F +P 6400 2400 +F 0 "U10" H 6400 2450 60 0000 C CNN +F 1 "7400" H 6400 2300 60 0000 C CNN + 1 6400 2400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 5072534B +P 9900 3900 +F 0 "#PWR01" H 9900 3900 30 0001 C CNN +F 1 "GND" H 9900 3830 30 0001 C CNN + 1 9900 3900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 507251F2 +P 2000 2700 +F 0 "#FLG02" H 2000 2970 30 0001 C CNN +F 1 "PWR_FLAG" H 2000 2930 30 0000 C CNN + 1 2000 2700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 507251E5 +P 1750 3150 +F 0 "#PWR03" H 1750 3150 30 0001 C CNN +F 1 "GND" H 1750 3080 30 0001 C CNN + 1 1750 3150 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 507251A7 +P 2250 2250 +F 0 "R3" V 2330 2250 50 0000 C CNN +F 1 "1000" V 2250 2250 50 0000 C CNN + 1 2250 2250 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v2 +U 1 1 50725192 +P 1750 2250 +F 0 "v2" H 1550 2350 60 0000 C CNN +F 1 "PULSE" H 1550 2200 60 0000 C CNN + 1 1750 2250 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG04 +U 1 1 50653022 +P 6200 1900 +F 0 "#FLG04" H 6200 2170 30 0001 C CNN +F 1 "PWR_FLAG" H 6200 2130 30 0000 C CNN + 1 6200 1900 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50652FB6 +P 9900 3350 +F 0 "R2" V 9980 3350 50 0000 C CNN +F 1 "1000" V 9900 3350 50 0000 C CNN + 1 9900 3350 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 505C9F25 +P 2250 4400 +F 0 "R1" V 2330 4400 50 0000 C CNN +F 1 "1000" V 2250 4400 50 0000 C CNN + 1 2250 4400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 505C9EE8 +P 1700 5200 +F 0 "#PWR05" H 1700 5200 30 0001 C CNN +F 1 "GND" H 1700 5130 30 0001 C CNN + 1 1700 5200 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v1 +U 1 1 505C9ECF +P 1700 4400 +F 0 "v1" H 1500 4500 60 0000 C CNN +F 1 "PULSE" H 1500 4350 60 0000 C CNN + 1 1700 4400 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/BasicGates/BasicGates.cir b/Examples/BasicGates/BasicGates.cir new file mode 100644 index 00000000..fbfc4755 --- /dev/null +++ b/Examples/BasicGates/BasicGates.cir @@ -0,0 +1,21 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 8 14:38:19 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R3 8 0 1000 +R2 3 0 1000 +R1 7 0 1000 +U2 12 6 5 d_and +U3 12 6 10 d_or +U4 5 10 1 d_nor +U5 5 10 9 d_nand +U6 1 11 d_inverter +U7 9 11 4 d_xor +U8 4 3 dac_bridge_1 +U1 8 7 12 6 adc_bridge_2 +v2 8 0 pulse +v1 7 0 pulse + +.end diff --git a/Examples/BasicGates/BasicGates.cir (copy).out b/Examples/BasicGates/BasicGates.cir (copy).out new file mode 100644 index 00000000..4c57b83b --- /dev/null +++ b/Examples/BasicGates/BasicGates.cir (copy).out @@ -0,0 +1,66 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 29 december 2014 04:59:08 pm utc + +* Plotting option vplot8_1 +* 74hc86 +* 74ls32 +* 74ls08 +* 74hc02 +* 74hc04 +* 7400 +r3 8 0 1000 +v2 8 0 pulse(0 5 0 0 0 2 20) +r2 9 0 1000 +r1 4 0 1000 +v1 4 0 pulse(5 0 0 0 0 2 20) +a1 [5] [5_in] u12adc +a2 [6] [6_in] u12adc +a3 [5_in 6_in] 9_out u12 +a4 [9_out] [9] u12dac +.model u12 d_xor +.model u12adc adc_bridge(in_low=0.8 in_high=2.0) +.model u12dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a5 [8] [8_in] u8adc +a6 [4] [4_in] u8adc +a7 [8_in 4_in] 10_out u8 +a8 [10_out] [10] u8dac +.model u8 d_or +.model u8adc adc_bridge(in_low=0.8 in_high=2.0) +.model u8dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a9 [8] [8_in] u7adc +a10 [4] [4_in] u7adc +a11 [8_in 4_in] 2_out u7 +a12 [2_out] [2] u7dac +.model u7 d_and +.model u7adc adc_bridge(in_low=0.8 in_high=2.0) +.model u7dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a13 [2] [2_in] u9adc +a14 [10] [10_in] u9adc +a15 [2_in 10_in] 7_out u9 +a16 [7_out] [7] u9dac +.model u9 d_nor +.model u9adc adc_bridge(in_low=0.8 in_high=2.0) +.model u9dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a17 [7] [7_in] u11adc +a18 7_in 6_out u11 +a19 [6_out] [6] u11dac +.model u11 d_inverter +.model u11adc adc_bridge(in_low=0.8 in_high=2.0) +.model u11dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a20 [2] [2_in] u10adc +a21 [10] [10_in] u10adc +a22 [2_in 10_in] 5_out u10 +a23 [5_out] [5] u10dac +.model u10 d_nand +.model u10adc adc_bridge(in_low=0.8 in_high=2.0) +.model u10dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-09 1e-06 0e-00 + +* Control Statements +.control +run +plot v(8) v(4) v(9) +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/BasicGates/BasicGates.cir.ckt b/Examples/BasicGates/BasicGates.cir.ckt new file mode 100644 index 00000000..59b85ffa --- /dev/null +++ b/Examples/BasicGates/BasicGates.cir.ckt @@ -0,0 +1,59 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 29 december 2014 04:59:08 pm utc + +* Plotting option vplot8_1 +* 74hc86 +* 74ls32 +* 74ls08 +* 74hc02 +* 74hc04 +* 7400 +r3 8 0 1000 +v2 8 0 pulse(0 5 0 0 0 2 20) +r2 9 0 1000 +r1 4 0 1000 +v1 4 0 pulse(5 0 0 0 0 2 20) +a1 [5] [5_in] u12adc +a2 [6] [6_in] u12adc +a3 [5_in 6_in] 9_out u12 +a4 [9_out] [9] u12dac +.model u12 d_xor +.model u12adc adc_bridge(in_low=0.8 in_high=2.0) +.model u12dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a5 [8] [8_in] u8adc +a6 [4] [4_in] u8adc +a7 [8_in 4_in] 10_out u8 +a8 [10_out] [10] u8dac +.model u8 d_or +.model u8adc adc_bridge(in_low=0.8 in_high=2.0) +.model u8dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a9 [8] [8_in] u7adc +a10 [4] [4_in] u7adc +a11 [8_in 4_in] 2_out u7 +a12 [2_out] [2] u7dac +.model u7 d_and +.model u7adc adc_bridge(in_low=0.8 in_high=2.0) +.model u7dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a13 [2] [2_in] u9adc +a14 [10] [10_in] u9adc +a15 [2_in 10_in] 7_out u9 +a16 [7_out] [7] u9dac +.model u9 d_nor +.model u9adc adc_bridge(in_low=0.8 in_high=2.0) +.model u9dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a17 [7] [7_in] u11adc +a18 7_in 6_out u11 +a19 [6_out] [6] u11dac +.model u11 d_inverter +.model u11adc adc_bridge(in_low=0.8 in_high=2.0) +.model u11dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a20 [2] [2_in] u10adc +a21 [10] [10_in] u10adc +a22 [2_in 10_in] 5_out u10 +a23 [5_out] [5] u10dac +.model u10 d_nand +.model u10adc adc_bridge(in_low=0.8 in_high=2.0) +.model u10dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-09 1e-06 0e-00 +.plot v(8) v(4) v(9) +.end diff --git a/Examples/BasicGates/BasicGates.cir.out b/Examples/BasicGates/BasicGates.cir.out new file mode 100644 index 00000000..69c4d9ee --- /dev/null +++ b/Examples/BasicGates/BasicGates.cir.out @@ -0,0 +1,48 @@ +* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 14:38:19 2015 + +r3 8 0 1000 +r2 3 0 1000 +r1 7 0 1000 +* u2 12 6 5 d_and +* u3 12 6 10 d_or +* u4 5 10 1 d_nor +* u5 5 10 9 d_nand +* u6 1 11 d_inverter +* u7 9 11 4 d_xor +* u8 4 3 dac_bridge_1 +* u1 8 7 12 6 adc_bridge_2 +v2 8 0 pulse(0 5 0.1u 0.1u 0.1u 2u 20u) +v1 7 0 pulse(5 0 0.1u 0.1u 0.1u 2u 20u) +a1 [12 6 ] 5 u2 +a2 [12 6 ] 10 u3 +a3 [5 10 ] 1 u4 +a4 [5 10 ] 9 u5 +a5 1 11 u6 +a6 [9 11 ] 4 u7 +a7 [4 ] [3 ] u8 +a8 [8 7 ] [12 6 ] u1 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +.tran 10e-06 30e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/BasicGates/BasicGates.cmp b/Examples/BasicGates/BasicGates.cmp new file mode 100644 index 00000000..70877a7f --- /dev/null +++ b/Examples/BasicGates/BasicGates.cmp @@ -0,0 +1,101 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Monday 22 October 2012 05:06:15 PM IST + +BeginCmp +TimeStamp = /505C9F25; +Reference = R1; +ValeurCmp = 1000; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /50652FB6; +Reference = R2; +ValeurCmp = 1000; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /507251A7; +Reference = R3; +ValeurCmp = 1000; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /505FD8A0; +Reference = U3; +ValeurCmp = ADC; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /505FDC21; +Reference = U4; +ValeurCmp = DAC; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725212; +Reference = U6; +ValeurCmp = ADC; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725428; +Reference = U7; +ValeurCmp = 74LS08; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725446; +Reference = U8; +ValeurCmp = 74LS32; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725415; +Reference = U9; +ValeurCmp = 74HC02; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /5072539F; +Reference = U10; +ValeurCmp = 7400; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /507253DF; +Reference = U11; +ValeurCmp = 74HC04; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /507253B2; +Reference = U12; +ValeurCmp = 74HC86; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /505C9ECF; +Reference = v1; +ValeurCmp = PULSE; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725192; +Reference = v2; +ValeurCmp = PULSE; +IdModule = ; +EndCmp + +EndListe diff --git a/Examples/BasicGates/BasicGates.net b/Examples/BasicGates/BasicGates.net new file mode 100644 index 00000000..e5b57d39 --- /dev/null +++ b/Examples/BasicGates/BasicGates.net @@ -0,0 +1,112 @@ +# EESchema Netlist Version 1.1 created Monday 22 October 2012 05:06:15 PM IST +( + ( /505C9F25 R3 R1 1000 + ( 1 N-000006 ) + ( 2 GND ) + ) + ( /50652FB6 R3 R2 1000 + ( 1 N-000007 ) + ( 2 GND ) + ) + ( /507251A7 R3 R3 1000 + ( 1 N-000009 ) + ( 2 GND ) + ) + ( /505FD8A0 $noname$ U3 ADC + ( 1 N-000006 ) + ( 2 N-000005 ) + ) + ( /505FDC21 $noname$ U4 DAC + ( 1 N-000008 ) + ( 2 N-000007 ) + ) + ( /50725212 $noname$ U6 ADC + ( 1 N-000009 ) + ( 2 N-000011 ) + ) + ( /50725428 $noname$ U7 74LS08 + ( 1 N-000011 ) + ( 2 N-000005 ) + ( 3 N-000003 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /50725446 $noname$ U8 74LS32 + ( 1 N-000011 ) + ( 2 N-000005 ) + ( 3 N-000013 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /50725415 $noname$ U9 74HC02 + ( 1 N-000004 ) + ( 2 N-000003 ) + ( 3 N-000013 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /5072539F $noname$ U10 7400 + ( 1 N-000003 ) + ( 2 N-000013 ) + ( 3 N-000010 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /507253DF $noname$ U11 74HC04 + ( 1 N-000004 ) + ( 2 N-000012 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /507253B2 $noname$ U12 74HC86 + ( 1 N-000010 ) + ( 2 N-000012 ) + ( 3 N-000008 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /505C9ECF $noname$ v1 PULSE + ( 1 N-000006 ) + ( 2 GND ) + ) + ( /50725192 $noname$ v2 PULSE + ( 1 N-000009 ) + ( 2 GND ) + ) +) +* +{ Allowed footprints by component: +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R3 + R? + SM0603 + SM0805 + R?-* +$endlist +$component U9 + SO14* + 14DIP* +$endlist +$component U10 + 14DIP300* + SO14* +$endlist +$component v1 + 1_pin +$endlist +$component v2 + 1_pin +$endlist +$endfootprintlist +} diff --git a/Examples/BasicGates/BasicGates.pro b/Examples/BasicGates/BasicGates.pro new file mode 100644 index 00000000..32036155 --- /dev/null +++ b/Examples/BasicGates/BasicGates.pro @@ -0,0 +1,41 @@ +update=Mon Jun 8 14:03:30 2015 +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources diff --git a/Examples/BasicGates/BasicGates.proj b/Examples/BasicGates/BasicGates.proj new file mode 100644 index 00000000..f8a0441b --- /dev/null +++ b/Examples/BasicGates/BasicGates.proj @@ -0,0 +1 @@ +schematicFile BasicGates.sch diff --git a/Examples/BasicGates/BasicGates.sch b/Examples/BasicGates/BasicGates.sch new file mode 100644 index 00000000..0b7634cd --- /dev/null +++ b/Examples/BasicGates/BasicGates.sch @@ -0,0 +1,407 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:BasicGates-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "9 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 9150 2850 0 60 ~ 0 +~A.B +Text Notes 9050 2850 0 60 ~ 0 ++ +Text Notes 8900 2850 0 60 ~ 0 +A.B +Text Notes 8000 2300 0 60 ~ 0 +~B +Text Notes 7900 2300 0 60 ~ 0 ++ +Text Notes 7750 2300 0 60 ~ 0 +=~A +Text Notes 7900 3650 0 60 ~ 0 +=A+B +Text Notes 7850 3500 0 60 ~ 0 +A.B+A+B +Text Notes 6450 3600 0 60 ~ 0 +~((A.B)+(A+B)) +Text Notes 7100 2300 0 60 ~ 0 +~((A.B).(A+B)) +Text Notes 5150 3650 0 60 ~ 0 +A+B +Text Notes 5100 2250 0 60 ~ 0 +A.B +Text Notes 3600 3950 0 60 ~ 0 +B +Text Notes 3500 1650 0 60 ~ 0 +A +$Comp +L GND #PWR01 +U 1 1 5072534B +P 10850 3900 +F 0 "#PWR01" H 10850 3900 30 0001 C CNN +F 1 "GND" H 10850 3830 30 0001 C CNN +F 2 "" H 10850 3900 60 0001 C CNN +F 3 "" H 10850 3900 60 0001 C CNN + 1 10850 3900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 507251F2 +P 1800 1700 +F 0 "#FLG02" H 1800 1970 30 0001 C CNN +F 1 "PWR_FLAG" H 1800 1930 30 0000 C CNN +F 2 "" H 1800 1700 60 0001 C CNN +F 3 "" H 1800 1700 60 0001 C CNN + 1 1800 1700 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 507251E5 +P 2050 1250 +F 0 "#PWR03" H 2050 1250 30 0001 C CNN +F 1 "GND" H 2050 1180 30 0001 C CNN +F 2 "" H 2050 1250 60 0001 C CNN +F 3 "" H 2050 1250 60 0001 C CNN + 1 2050 1250 + -1 0 0 1 +$EndComp +$Comp +L R R3 +U 1 1 507251A7 +P 1400 2200 +F 0 "R3" V 1480 2200 50 0000 C CNN +F 1 "1000" V 1400 2200 50 0000 C CNN +F 2 "" H 1400 2200 60 0001 C CNN +F 3 "" H 1400 2200 60 0001 C CNN + 1 1400 2200 + -1 0 0 1 +$EndComp +$Comp +L R R2 +U 1 1 50652FB6 +P 10850 3350 +F 0 "R2" V 10930 3350 50 0000 C CNN +F 1 "1000" V 10850 3350 50 0000 C CNN +F 2 "" H 10850 3350 60 0001 C CNN +F 3 "" H 10850 3350 60 0001 C CNN + 1 10850 3350 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 505C9F25 +P 2200 5100 +F 0 "R1" V 2280 5100 50 0000 C CNN +F 1 "1000" V 2200 5100 50 0000 C CNN +F 2 "" H 2200 5100 60 0001 C CNN +F 3 "" H 2200 5100 60 0001 C CNN + 1 2200 5100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 505C9EE8 +P 1650 5900 +F 0 "#PWR04" H 1650 5900 30 0001 C CNN +F 1 "GND" H 1650 5830 30 0001 C CNN +F 2 "" H 1650 5900 60 0001 C CNN +F 3 "" H 1650 5900 60 0001 C CNN + 1 1650 5900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5575A2C1 +P 4450 2350 +F 0 "U2" H 4450 2350 60 0000 C CNN +F 1 "d_and" H 4500 2450 60 0000 C CNN +F 2 "" H 4450 2350 60 0000 C CNN +F 3 "" H 4450 2350 60 0000 C CNN + 1 4450 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5575A328 +P 4550 3550 +F 0 "U3" H 4550 3550 60 0000 C CNN +F 1 "d_or" H 4550 3650 60 0000 C CNN +F 2 "" H 4550 3550 60 0000 C CNN +F 3 "" H 4550 3550 60 0000 C CNN + 1 4550 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U4 +U 1 1 5575A38D +P 6200 3450 +F 0 "U4" H 6200 3450 60 0000 C CNN +F 1 "d_nor" H 6250 3550 60 0000 C CNN +F 2 "" H 6200 3450 60 0000 C CNN +F 3 "" H 6200 3450 60 0000 C CNN + 1 6200 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 5575A3E6 +P 6450 2450 +F 0 "U5" H 6450 2450 60 0000 C CNN +F 1 "d_nand" H 6500 2550 60 0000 C CNN +F 2 "" H 6450 2450 60 0000 C CNN +F 3 "" H 6450 2450 60 0000 C CNN + 1 6450 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5575A56B +P 7400 3400 +F 0 "U6" H 7400 3300 60 0000 C CNN +F 1 "d_inverter" H 7400 3550 60 0000 C CNN +F 2 "" H 7450 3350 60 0000 C CNN +F 3 "" H 7450 3350 60 0000 C CNN + 1 7400 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U7 +U 1 1 5575A5B8 +P 8600 3050 +F 0 "U7" H 8600 3050 60 0000 C CNN +F 1 "d_xor" H 8650 3150 47 0000 C CNN +F 2 "" H 8600 3050 60 0000 C CNN +F 3 "" H 8600 3050 60 0000 C CNN + 1 8600 3050 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U8 +U 1 1 5575A633 +P 9800 3050 +F 0 "U8" H 9800 3050 60 0000 C CNN +F 1 "dac_bridge_1" H 9800 3200 60 0000 C CNN +F 2 "" H 9800 3050 60 0000 C CNN +F 3 "" H 9800 3050 60 0000 C CNN + 1 9800 3050 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_2 U1 +U 1 1 5575A8EB +P 2850 3200 +F 0 "U1" H 2850 3200 60 0000 C CNN +F 1 "adc_bridge_2" H 2850 3350 60 0000 C CNN +F 2 "" H 2850 3200 60 0000 C CNN +F 3 "" H 2850 3200 60 0000 C CNN + 1 2850 3200 + 1 0 0 -1 +$EndComp +$Comp +L pulse v2 +U 1 1 5575AD50 +P 2050 2150 +F 0 "v2" H 1850 2250 60 0000 C CNN +F 1 "pulse" H 1850 2100 60 0000 C CNN +F 2 "R1" H 1750 2150 60 0000 C CNN +F 3 "" H 2050 2150 60 0000 C CNN + 1 2050 2150 + -1 0 0 1 +$EndComp +$Comp +L pulse v1 +U 1 1 5575AE1A +P 1650 5100 +F 0 "v1" H 1450 5200 60 0000 C CNN +F 1 "pulse" H 1450 5050 60 0000 C CNN +F 2 "R1" H 1350 5100 60 0000 C CNN +F 3 "" H 1650 5100 60 0000 C CNN + 1 1650 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1650 4500 2200 4500 +Wire Wire Line + 3500 3800 3750 3800 +Wire Wire Line + 7900 3100 7850 3100 +Wire Wire Line + 7850 3100 7850 3400 +Wire Wire Line + 7850 3400 7700 3400 +Connection ~ 5300 2300 +Wire Wire Line + 5300 2300 5300 3300 +Wire Wire Line + 5300 3300 5500 3300 +Wire Wire Line + 5000 3500 5500 3500 +Wire Wire Line + 7900 2900 7350 2900 +Wire Wire Line + 7350 2900 7350 2400 +Wire Wire Line + 7350 2400 6900 2400 +Connection ~ 3750 2200 +Wire Wire Line + 3900 3400 3750 3400 +Wire Wire Line + 3750 3400 3750 2200 +Wire Wire Line + 3650 2200 3850 2200 +Wire Wire Line + 3650 1700 3650 2200 +Connection ~ 1400 2750 +Connection ~ 1800 1500 +Wire Wire Line + 1800 1500 1800 1700 +Wire Wire Line + 2200 4500 2200 4950 +Wire Wire Line + 1650 4500 1650 4650 +Wire Wire Line + 1400 1500 1400 2050 +Wire Wire Line + 1400 1500 2050 1500 +Connection ~ 1650 5750 +Wire Wire Line + 2200 5750 1650 5750 +Wire Wire Line + 2200 5250 2200 5750 +Wire Wire Line + 1650 5550 1650 5900 +Wire Wire Line + 2050 2600 2050 3150 +Wire Wire Line + 1400 2350 1400 2750 +Wire Wire Line + 2050 1700 2050 1250 +Connection ~ 2050 1500 +Wire Wire Line + 3900 3600 3750 3600 +Wire Wire Line + 3750 3600 3750 3800 +Wire Wire Line + 3600 2350 3600 3800 +Wire Wire Line + 4900 2300 5800 2300 +Wire Wire Line + 5800 2500 5200 2500 +Wire Wire Line + 5200 2500 5200 3500 +Connection ~ 5200 3500 +Wire Wire Line + 6650 3400 7100 3400 +Wire Wire Line + 10850 3500 10850 3900 +Connection ~ 3600 3800 +Wire Wire Line + 3400 3250 3500 3250 +Wire Wire Line + 3500 3250 3500 3800 +Wire Wire Line + 3500 3150 3400 3150 +Wire Wire Line + 3500 1700 3500 3150 +Wire Wire Line + 3500 1700 3650 1700 +Wire Wire Line + 2050 3150 2250 3150 +Wire Wire Line + 1400 2750 2050 2750 +Connection ~ 2050 2750 +Wire Wire Line + 2250 3250 2050 3250 +Wire Wire Line + 2050 3250 2050 4500 +Connection ~ 2050 4500 +Wire Wire Line + 3850 2200 3850 2250 +Wire Wire Line + 3850 2250 4000 2250 +Wire Wire Line + 4000 2350 3600 2350 +Wire Wire Line + 3900 3400 3900 3450 +Wire Wire Line + 3900 3450 4100 3450 +Wire Wire Line + 3900 3600 3900 3550 +Wire Wire Line + 3900 3550 4100 3550 +Wire Wire Line + 5800 2300 5800 2350 +Wire Wire Line + 5800 2350 6000 2350 +Wire Wire Line + 5800 2500 5800 2450 +Wire Wire Line + 5800 2450 6000 2450 +Wire Wire Line + 5500 3300 5500 3350 +Wire Wire Line + 5500 3350 5750 3350 +Wire Wire Line + 5500 3500 5500 3450 +Wire Wire Line + 5500 3450 5750 3450 +Wire Wire Line + 7900 2900 7900 2950 +Wire Wire Line + 7900 2950 8150 2950 +Wire Wire Line + 7900 3100 7900 3050 +Wire Wire Line + 7900 3050 8150 3050 +Wire Wire Line + 9050 3000 9200 3000 +Wire Wire Line + 10350 3000 10850 3000 +Wire Wire Line + 10850 3000 10850 3200 +$EndSCHEMATC diff --git a/Examples/BasicGates/BasicGates_Previous_Values.xml b/Examples/BasicGates/BasicGates_Previous_Values.xml new file mode 100644 index 00000000..b26b64e5 --- /dev/null +++ b/Examples/BasicGates/BasicGates_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0.1u</field3><field4 name="Rise Time">0.1u</field4><field5 name="Fall Time">0.1u</field5><field5 name="Pulse width">2u</field5><field5 name="Period">20u</field5></v2><v1 name="Source type">pulse<field1 name="Initial Value">5</field1><field2 name="Pulse Value">0</field2><field3 name="Delay Time">0.1u</field3><field4 name="Rise Time">0.1u</field4><field5 name="Fall Time">0.1u</field5><field5 name="Pulse width">2u</field5><field5 name="Period">20u</field5></v1></source><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_nand<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_xor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">dac_bridge<field19 name="Enter value for input load (default=1.0e-12)" /><field20 name="Enter value for out_low (default=0.0)" /><field21 name="Enter value for out_high (default=5.0)" /><field22 name="Enter the Rise Time (default=1.0e-9)" /><field23 name="Enter the Fall Time (default=1.0e-9)" /><field24 name="Enter value for out_undef (default=0.5)" /></u8><u1 name="type">adc_bridge<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter value for in_high (default=2.0)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /><field28 name="Enter value for in_low (default=1.0)" /></u1></model><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">30</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">us</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/BasicGates/BasicGates_last_input.txt b/Examples/BasicGates/BasicGates_last_input.txt new file mode 100644 index 00000000..5d6f4aa4 --- /dev/null +++ b/Examples/BasicGates/BasicGates_last_input.txt @@ -0,0 +1,20 @@ +v2 8 0 pulse(0 5 0 0 0 2 20) +v1 4 0 pulse(5 0 0 0 0 2 20) +.model u12 d_xor +.model u12adc adc_bridge(in_low=0.8 in_high=2.0) +.model u12dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +.model u8 d_or +.model u8adc adc_bridge(in_low=0.8 in_high=2.0) +.model u8dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +.model u7 d_and +.model u7adc adc_bridge(in_low=0.8 in_high=2.0) +.model u7dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +.model u9 d_nor +.model u9adc adc_bridge(in_low=0.8 in_high=2.0) +.model u9dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +.model u11 d_inverter +.model u11adc adc_bridge(in_low=0.8 in_high=2.0) +.model u11dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +.model u10 d_nand +.model u10adc adc_bridge(in_low=0.8 in_high=2.0) +.model u10dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) diff --git a/Examples/BasicGates/analysis b/Examples/BasicGates/analysis new file mode 100644 index 00000000..2acaeed9 --- /dev/null +++ b/Examples/BasicGates/analysis @@ -0,0 +1 @@ +.tran 10e-06 30e-06 0e-00
\ No newline at end of file diff --git a/Examples/BasicGates/plot_data_i.txt b/Examples/BasicGates/plot_data_i.txt new file mode 100644 index 00000000..dfea4f20 --- /dev/null +++ b/Examples/BasicGates/plot_data_i.txt @@ -0,0 +1,335 @@ +* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 14:38:19 2015 +Transient Analysis Fri Jun 26 11:22:20 2015 +-------------------------------------------------------------------------------- +Index time a7#branch_1_0 v1#branch v2#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 -5.00000e-03 0.000000e+00 +1 1.000000e-09 0.000000e+00 -5.00000e-03 0.000000e+00 +2 2.000000e-09 0.000000e+00 -5.00000e-03 0.000000e+00 +3 4.000000e-09 0.000000e+00 -5.00000e-03 0.000000e+00 +4 8.000000e-09 0.000000e+00 -5.00000e-03 0.000000e+00 +5 1.600000e-08 0.000000e+00 -5.00000e-03 0.000000e+00 +6 3.200000e-08 0.000000e+00 -5.00000e-03 0.000000e+00 +7 6.400000e-08 0.000000e+00 -5.00000e-03 0.000000e+00 +8 1.000000e-07 0.000000e+00 -5.00000e-03 0.000000e+00 +9 1.064000e-07 0.000000e+00 -4.68000e-03 -3.20000e-04 +10 1.192000e-07 0.000000e+00 -4.04000e-03 -9.60000e-04 +11 1.448000e-07 0.000000e+00 -2.76000e-03 -2.24000e-03 +12 1.488000e-07 0.000000e+00 -2.56000e-03 -2.44000e-03 +13 1.489000e-07 -5.00000e-04 -2.55500e-03 -2.44500e-03 +14 1.491000e-07 -1.50000e-03 -2.54500e-03 -2.45500e-03 +15 1.495000e-07 -3.50000e-03 -2.52500e-03 -2.47500e-03 +16 1.498000e-07 -5.00000e-03 -2.51000e-03 -2.49000e-03 +17 1.498800e-07 -5.00000e-03 -2.50600e-03 -2.49400e-03 +18 1.500400e-07 -5.00000e-03 -2.49800e-03 -2.50200e-03 +19 1.503600e-07 -5.00000e-03 -2.48200e-03 -2.51800e-03 +20 1.510000e-07 -5.00000e-03 -2.45000e-03 -2.55000e-03 +21 1.522800e-07 -5.00000e-03 -2.38600e-03 -2.61400e-03 +22 1.548400e-07 -5.00000e-03 -2.25800e-03 -2.74200e-03 +23 1.599600e-07 -5.00000e-03 -2.00200e-03 -2.99800e-03 +24 1.702000e-07 -5.00000e-03 -1.49000e-03 -3.51000e-03 +25 1.742000e-07 -5.00000e-03 -1.29000e-03 -3.71000e-03 +26 1.742900e-07 -4.55000e-03 -1.28550e-03 -3.71450e-03 +27 1.744700e-07 -3.65000e-03 -1.27650e-03 -3.72350e-03 +28 1.748300e-07 -1.85000e-03 -1.25850e-03 -3.74150e-03 +29 1.751000e-07 -5.00000e-04 -1.24500e-03 -3.75500e-03 +30 1.751720e-07 -5.00000e-04 -1.24140e-03 -3.75860e-03 +31 1.753160e-07 -5.00000e-04 -1.23420e-03 -3.76580e-03 +32 1.756040e-07 -5.00000e-04 -1.21980e-03 -3.78020e-03 +33 1.761800e-07 -5.00000e-04 -1.19100e-03 -3.80900e-03 +34 1.773320e-07 -5.00000e-04 -1.13340e-03 -3.86660e-03 +35 1.796360e-07 -5.00000e-04 -1.01820e-03 -3.98180e-03 +36 1.842440e-07 -5.00000e-04 -7.87800e-04 -4.21220e-03 +37 1.882440e-07 -5.00000e-04 -5.87800e-04 -4.41220e-03 +38 1.882540e-07 -4.50000e-04 -5.87300e-04 -4.41270e-03 +39 1.882740e-07 -3.50000e-04 -5.86300e-04 -4.41370e-03 +40 1.883140e-07 -1.50000e-04 -5.84300e-04 -4.41570e-03 +41 1.883440e-07 0.000000e+00 -5.82800e-04 -4.41720e-03 +42 1.883520e-07 0.000000e+00 -5.82400e-04 -4.41760e-03 +43 1.883680e-07 0.000000e+00 -5.81600e-04 -4.41840e-03 +44 1.884000e-07 0.000000e+00 -5.80000e-04 -4.42000e-03 +45 1.884640e-07 0.000000e+00 -5.76800e-04 -4.42320e-03 +46 1.885920e-07 0.000000e+00 -5.70400e-04 -4.42960e-03 +47 1.888480e-07 0.000000e+00 -5.57600e-04 -4.44240e-03 +48 1.893600e-07 0.000000e+00 -5.32000e-04 -4.46800e-03 +49 1.903840e-07 0.000000e+00 -4.80800e-04 -4.51920e-03 +50 1.924320e-07 0.000000e+00 -3.78400e-04 -4.62160e-03 +51 1.965280e-07 0.000000e+00 -1.73600e-04 -4.82640e-03 +52 2.000000e-07 0.000000e+00 0.000000e+00 -5.00000e-03 +53 2.008192e-07 0.000000e+00 0.000000e+00 -5.00000e-03 +54 2.024576e-07 0.000000e+00 0.000000e+00 -5.00000e-03 + +Index time a7#branch_1_0 v1#branch v2#branch +-------------------------------------------------------------------------------- +55 2.057344e-07 0.000000e+00 0.000000e+00 -5.00000e-03 +56 2.122880e-07 0.000000e+00 0.000000e+00 -5.00000e-03 +57 2.253952e-07 0.000000e+00 0.000000e+00 -5.00000e-03 +58 2.516096e-07 0.000000e+00 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-3.58300e-04 +280 2.229287e-05 -1.50000e-04 -4.64370e-03 -3.56300e-04 +281 2.229290e-05 0.000000e+00 -4.64520e-03 -3.54800e-04 +282 2.229291e-05 0.000000e+00 -4.64560e-03 -3.54400e-04 +283 2.229293e-05 0.000000e+00 -4.64640e-03 -3.53600e-04 +284 2.229296e-05 0.000000e+00 -4.64800e-03 -3.52000e-04 +285 2.229302e-05 0.000000e+00 -4.65120e-03 -3.48800e-04 +286 2.229315e-05 0.000000e+00 -4.65760e-03 -3.42400e-04 + +Index time a7#branch_1_0 v1#branch v2#branch +-------------------------------------------------------------------------------- +287 2.229341e-05 0.000000e+00 -4.67040e-03 -3.29600e-04 +288 2.229392e-05 0.000000e+00 -4.69600e-03 -3.04000e-04 +289 2.229494e-05 0.000000e+00 -4.74720e-03 -2.52800e-04 +290 2.229699e-05 0.000000e+00 -4.84960e-03 -1.50400e-04 +291 2.230000e-05 0.000000e+00 -5.00000e-03 -2.66454e-17 +292 2.230041e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +293 2.230123e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +294 2.230287e-05 0.000000e+00 -5.00000e-03 0.000000e+00 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-5.00000e-03 0.000000e+00 +313 2.973845e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +314 3.000000e-05 0.000000e+00 -5.00000e-03 0.000000e+00 diff --git a/Examples/BasicGates/plot_data_v.txt b/Examples/BasicGates/plot_data_v.txt new file mode 100644 index 00000000..99290538 --- /dev/null +++ b/Examples/BasicGates/plot_data_v.txt @@ -0,0 +1,335 @@ +* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 14:38:19 2015 +Transient Analysis Fri Jun 26 11:22:20 2015 +-------------------------------------------------------------------------------- +Index time V(3) V(7) V(8) +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 5.000000e+00 0.000000e+00 +1 1.000000e-09 0.000000e+00 5.000000e+00 0.000000e+00 +2 2.000000e-09 0.000000e+00 5.000000e+00 0.000000e+00 +3 4.000000e-09 0.000000e+00 5.000000e+00 0.000000e+00 +4 8.000000e-09 0.000000e+00 5.000000e+00 0.000000e+00 +5 1.600000e-08 0.000000e+00 5.000000e+00 0.000000e+00 +6 3.200000e-08 0.000000e+00 5.000000e+00 0.000000e+00 +7 6.400000e-08 0.000000e+00 5.000000e+00 0.000000e+00 +8 1.000000e-07 0.000000e+00 5.000000e+00 0.000000e+00 +9 1.064000e-07 0.000000e+00 4.680000e+00 3.200000e-01 +10 1.192000e-07 0.000000e+00 4.040000e+00 9.600000e-01 +11 1.448000e-07 0.000000e+00 2.760000e+00 2.240000e+00 +12 1.488000e-07 0.000000e+00 2.560000e+00 2.440000e+00 +13 1.489000e-07 5.000000e-01 2.555000e+00 2.445000e+00 +14 1.491000e-07 1.500000e+00 2.545000e+00 2.455000e+00 +15 1.495000e-07 3.500000e+00 2.525000e+00 2.475000e+00 +16 1.498000e-07 5.000000e+00 2.510000e+00 2.490000e+00 +17 1.498800e-07 5.000000e+00 2.506000e+00 2.494000e+00 +18 1.500400e-07 5.000000e+00 2.498000e+00 2.502000e+00 +19 1.503600e-07 5.000000e+00 2.482000e+00 2.518000e+00 +20 1.510000e-07 5.000000e+00 2.450000e+00 2.550000e+00 +21 1.522800e-07 5.000000e+00 2.386000e+00 2.614000e+00 +22 1.548400e-07 5.000000e+00 2.258000e+00 2.742000e+00 +23 1.599600e-07 5.000000e+00 2.002000e+00 2.998000e+00 +24 1.702000e-07 5.000000e+00 1.490000e+00 3.510000e+00 +25 1.742000e-07 5.000000e+00 1.290000e+00 3.710000e+00 +26 1.742900e-07 4.550000e+00 1.285500e+00 3.714500e+00 +27 1.744700e-07 3.650000e+00 1.276500e+00 3.723500e+00 +28 1.748300e-07 1.850000e+00 1.258500e+00 3.741500e+00 +29 1.751000e-07 5.000000e-01 1.245000e+00 3.755000e+00 +30 1.751720e-07 5.000000e-01 1.241400e+00 3.758600e+00 +31 1.753160e-07 5.000000e-01 1.234200e+00 3.765800e+00 +32 1.756040e-07 5.000000e-01 1.219800e+00 3.780200e+00 +33 1.761800e-07 5.000000e-01 1.191000e+00 3.809000e+00 +34 1.773320e-07 5.000000e-01 1.133400e+00 3.866600e+00 +35 1.796360e-07 5.000000e-01 1.018200e+00 3.981800e+00 +36 1.842440e-07 5.000000e-01 7.878000e-01 4.212200e+00 +37 1.882440e-07 5.000000e-01 5.878000e-01 4.412200e+00 +38 1.882540e-07 4.500000e-01 5.873000e-01 4.412700e+00 +39 1.882740e-07 3.500000e-01 5.863000e-01 4.413700e+00 +40 1.883140e-07 1.500000e-01 5.843000e-01 4.415700e+00 +41 1.883440e-07 0.000000e+00 5.828000e-01 4.417200e+00 +42 1.883520e-07 0.000000e+00 5.824000e-01 4.417600e+00 +43 1.883680e-07 0.000000e+00 5.816000e-01 4.418400e+00 +44 1.884000e-07 0.000000e+00 5.800000e-01 4.420000e+00 +45 1.884640e-07 0.000000e+00 5.768000e-01 4.423200e+00 +46 1.885920e-07 0.000000e+00 5.704000e-01 4.429600e+00 +47 1.888480e-07 0.000000e+00 5.576000e-01 4.442400e+00 +48 1.893600e-07 0.000000e+00 5.320000e-01 4.468000e+00 +49 1.903840e-07 0.000000e+00 4.808000e-01 4.519200e+00 +50 1.924320e-07 0.000000e+00 3.784000e-01 4.621600e+00 +51 1.965280e-07 0.000000e+00 1.736000e-01 4.826400e+00 +52 2.000000e-07 0.000000e+00 0.000000e+00 5.000000e+00 +53 2.008192e-07 0.000000e+00 0.000000e+00 5.000000e+00 +54 2.024576e-07 0.000000e+00 0.000000e+00 5.000000e+00 + +Index time V(3) V(7) V(8) +-------------------------------------------------------------------------------- +55 2.057344e-07 0.000000e+00 0.000000e+00 5.000000e+00 +56 2.122880e-07 0.000000e+00 0.000000e+00 5.000000e+00 +57 2.253952e-07 0.000000e+00 0.000000e+00 5.000000e+00 +58 2.516096e-07 0.000000e+00 0.000000e+00 5.000000e+00 +59 3.040384e-07 0.000000e+00 0.000000e+00 5.000000e+00 +60 4.088960e-07 0.000000e+00 0.000000e+00 5.000000e+00 +61 6.186112e-07 0.000000e+00 0.000000e+00 5.000000e+00 +62 1.038042e-06 0.000000e+00 0.000000e+00 5.000000e+00 +63 1.638042e-06 0.000000e+00 0.000000e+00 5.000000e+00 +64 2.200000e-06 0.000000e+00 2.117582e-14 5.000000e+00 +65 2.210000e-06 0.000000e+00 5.000000e-01 4.500000e+00 +66 2.230000e-06 0.000000e+00 1.500000e+00 3.500000e+00 +67 2.234000e-06 0.000000e+00 1.700000e+00 3.300000e+00 +68 2.234010e-06 5.000000e-02 1.700500e+00 3.299500e+00 +69 2.234030e-06 1.500000e-01 1.701500e+00 3.298500e+00 +70 2.234070e-06 3.500000e-01 1.703500e+00 3.296500e+00 +71 2.234100e-06 5.000000e-01 1.705000e+00 3.295000e+00 +72 2.234108e-06 5.000000e-01 1.705400e+00 3.294600e+00 +73 2.234124e-06 5.000000e-01 1.706200e+00 3.293800e+00 +74 2.234156e-06 5.000000e-01 1.707800e+00 3.292200e+00 +75 2.234220e-06 5.000000e-01 1.711000e+00 3.289000e+00 +76 2.234348e-06 5.000000e-01 1.717400e+00 3.282600e+00 +77 2.234604e-06 5.000000e-01 1.730200e+00 3.269800e+00 +78 2.235116e-06 5.000000e-01 1.755800e+00 3.244200e+00 +79 2.236140e-06 5.000000e-01 1.807000e+00 3.193000e+00 +80 2.238188e-06 5.000000e-01 1.909400e+00 3.090600e+00 +81 2.242284e-06 5.000000e-01 2.114200e+00 2.885800e+00 +82 2.246284e-06 5.000000e-01 2.314200e+00 2.685800e+00 +83 2.246374e-06 9.500000e-01 2.318700e+00 2.681300e+00 +84 2.246554e-06 1.850000e+00 2.327700e+00 2.672300e+00 +85 2.246914e-06 3.650000e+00 2.345700e+00 2.654300e+00 +86 2.247184e-06 5.000000e+00 2.359200e+00 2.640800e+00 +87 2.247256e-06 5.000000e+00 2.362800e+00 2.637200e+00 +88 2.247400e-06 5.000000e+00 2.370000e+00 2.630000e+00 +89 2.247688e-06 5.000000e+00 2.384400e+00 2.615600e+00 +90 2.248264e-06 5.000000e+00 2.413200e+00 2.586800e+00 +91 2.249416e-06 5.000000e+00 2.470800e+00 2.529200e+00 +92 2.251720e-06 5.000000e+00 2.586000e+00 2.414000e+00 +93 2.256328e-06 5.000000e+00 2.816400e+00 2.183600e+00 +94 2.265544e-06 5.000000e+00 3.277200e+00 1.722800e+00 +95 2.269544e-06 5.000000e+00 3.477200e+00 1.522800e+00 +96 2.269634e-06 4.550000e+00 3.481700e+00 1.518300e+00 +97 2.269814e-06 3.650000e+00 3.490700e+00 1.509300e+00 +98 2.270174e-06 1.850000e+00 3.508700e+00 1.491300e+00 +99 2.270444e-06 5.000000e-01 3.522200e+00 1.477800e+00 +100 2.270516e-06 5.000000e-01 3.525800e+00 1.474200e+00 +101 2.270660e-06 5.000000e-01 3.533000e+00 1.467000e+00 +102 2.270948e-06 5.000000e-01 3.547400e+00 1.452600e+00 +103 2.271524e-06 5.000000e-01 3.576200e+00 1.423800e+00 +104 2.272676e-06 5.000000e-01 3.633800e+00 1.366200e+00 +105 2.274980e-06 5.000000e-01 3.749000e+00 1.251000e+00 +106 2.279588e-06 5.000000e-01 3.979400e+00 1.020600e+00 +107 2.288804e-06 5.000000e-01 4.440200e+00 5.598000e-01 +108 2.292804e-06 5.000000e-01 4.640200e+00 3.598000e-01 +109 2.292814e-06 4.500000e-01 4.640700e+00 3.593000e-01 +110 2.292834e-06 3.500000e-01 4.641700e+00 3.583000e-01 +111 2.292874e-06 1.500000e-01 4.643700e+00 3.563000e-01 +112 2.292904e-06 1.021239e-12 4.645200e+00 3.548000e-01 + +Index time V(3) V(7) V(8) +-------------------------------------------------------------------------------- +113 2.292912e-06 0.000000e+00 4.645600e+00 3.544000e-01 +114 2.292928e-06 0.000000e+00 4.646400e+00 3.536000e-01 +115 2.292960e-06 0.000000e+00 4.648000e+00 3.520000e-01 +116 2.293024e-06 0.000000e+00 4.651200e+00 3.488000e-01 +117 2.293152e-06 0.000000e+00 4.657600e+00 3.424000e-01 +118 2.293408e-06 0.000000e+00 4.670400e+00 3.296000e-01 +119 2.293920e-06 0.000000e+00 4.696000e+00 3.040000e-01 +120 2.294944e-06 0.000000e+00 4.747200e+00 2.528000e-01 +121 2.296992e-06 0.000000e+00 4.849600e+00 1.504000e-01 +122 2.300000e-06 0.000000e+00 5.000000e+00 0.000000e+00 +123 2.300410e-06 0.000000e+00 5.000000e+00 0.000000e+00 +124 2.301229e-06 0.000000e+00 5.000000e+00 0.000000e+00 +125 2.302867e-06 0.000000e+00 5.000000e+00 0.000000e+00 +126 2.306144e-06 0.000000e+00 5.000000e+00 0.000000e+00 +127 2.312698e-06 0.000000e+00 5.000000e+00 0.000000e+00 +128 2.325805e-06 0.000000e+00 5.000000e+00 0.000000e+00 +129 2.352019e-06 0.000000e+00 5.000000e+00 0.000000e+00 +130 2.404448e-06 0.000000e+00 5.000000e+00 0.000000e+00 +131 2.509306e-06 0.000000e+00 5.000000e+00 0.000000e+00 +132 2.719021e-06 0.000000e+00 5.000000e+00 0.000000e+00 +133 3.138451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +134 3.738451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +135 4.338451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +136 4.938451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +137 5.538451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +138 6.138451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +139 6.738451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +140 7.338451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +141 7.938451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +142 8.538451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +143 9.138451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +144 9.738451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +145 1.033845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +146 1.093845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +147 1.153845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +148 1.213845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +149 1.273845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +150 1.333845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +151 1.393845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +152 1.453845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +153 1.513845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +154 1.573845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +155 1.633845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +156 1.693845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +157 1.753845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +158 1.813845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +159 1.873845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +160 1.933845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +161 1.993845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +162 2.010000e-05 0.000000e+00 5.000000e+00 0.000000e+00 +163 2.011000e-05 0.000000e+00 4.500000e+00 5.000000e-01 +164 2.013000e-05 0.000000e+00 3.500000e+00 1.500000e+00 +165 2.013400e-05 0.000000e+00 3.300000e+00 1.700000e+00 +166 2.013401e-05 5.000000e-02 3.299500e+00 1.700500e+00 +167 2.013403e-05 1.500000e-01 3.298500e+00 1.701500e+00 +168 2.013407e-05 3.500000e-01 3.296500e+00 1.703500e+00 +169 2.013410e-05 5.000000e-01 3.295000e+00 1.705000e+00 +170 2.013411e-05 5.000000e-01 3.294600e+00 1.705400e+00 + +Index time V(3) V(7) V(8) +-------------------------------------------------------------------------------- +171 2.013412e-05 5.000000e-01 3.293800e+00 1.706200e+00 +172 2.013416e-05 5.000000e-01 3.292200e+00 1.707800e+00 +173 2.013422e-05 5.000000e-01 3.289000e+00 1.711000e+00 +174 2.013435e-05 5.000000e-01 3.282600e+00 1.717400e+00 +175 2.013460e-05 5.000000e-01 3.269800e+00 1.730200e+00 +176 2.013512e-05 5.000000e-01 3.244200e+00 1.755800e+00 +177 2.013614e-05 5.000000e-01 3.193000e+00 1.807000e+00 +178 2.013819e-05 5.000000e-01 3.090600e+00 1.909400e+00 +179 2.014228e-05 5.000000e-01 2.885800e+00 2.114200e+00 +180 2.014628e-05 5.000000e-01 2.685800e+00 2.314200e+00 +181 2.014637e-05 9.500000e-01 2.681300e+00 2.318700e+00 +182 2.014655e-05 1.850000e+00 2.672300e+00 2.327700e+00 +183 2.014691e-05 3.650000e+00 2.654300e+00 2.345700e+00 +184 2.014718e-05 5.000000e+00 2.640800e+00 2.359200e+00 +185 2.014726e-05 5.000000e+00 2.637200e+00 2.362800e+00 +186 2.014740e-05 5.000000e+00 2.630000e+00 2.370000e+00 +187 2.014769e-05 5.000000e+00 2.615600e+00 2.384400e+00 +188 2.014826e-05 5.000000e+00 2.586800e+00 2.413200e+00 +189 2.014942e-05 5.000000e+00 2.529200e+00 2.470800e+00 +190 2.015172e-05 5.000000e+00 2.414000e+00 2.586000e+00 +191 2.015633e-05 5.000000e+00 2.183600e+00 2.816400e+00 +192 2.016554e-05 5.000000e+00 1.722800e+00 3.277200e+00 +193 2.016954e-05 5.000000e+00 1.522800e+00 3.477200e+00 +194 2.016963e-05 4.550000e+00 1.518300e+00 3.481700e+00 +195 2.016981e-05 3.650000e+00 1.509300e+00 3.490700e+00 +196 2.017017e-05 1.850000e+00 1.491300e+00 3.508700e+00 +197 2.017044e-05 5.000000e-01 1.477800e+00 3.522200e+00 +198 2.017052e-05 5.000000e-01 1.474200e+00 3.525800e+00 +199 2.017066e-05 5.000000e-01 1.467000e+00 3.533000e+00 +200 2.017095e-05 5.000000e-01 1.452600e+00 3.547400e+00 +201 2.017152e-05 5.000000e-01 1.423800e+00 3.576200e+00 +202 2.017268e-05 5.000000e-01 1.366200e+00 3.633800e+00 +203 2.017498e-05 5.000000e-01 1.251000e+00 3.749000e+00 +204 2.017959e-05 5.000000e-01 1.020600e+00 3.979400e+00 +205 2.018880e-05 5.000000e-01 5.598000e-01 4.440200e+00 +206 2.019280e-05 5.000000e-01 3.598000e-01 4.640200e+00 +207 2.019281e-05 4.500000e-01 3.593000e-01 4.640700e+00 +208 2.019283e-05 3.500000e-01 3.583000e-01 4.641700e+00 +209 2.019287e-05 1.500000e-01 3.563000e-01 4.643700e+00 +210 2.019290e-05 0.000000e+00 3.548000e-01 4.645200e+00 +211 2.019291e-05 0.000000e+00 3.544000e-01 4.645600e+00 +212 2.019293e-05 0.000000e+00 3.536000e-01 4.646400e+00 +213 2.019296e-05 0.000000e+00 3.520000e-01 4.648000e+00 +214 2.019302e-05 0.000000e+00 3.488000e-01 4.651200e+00 +215 2.019315e-05 0.000000e+00 3.424000e-01 4.657600e+00 +216 2.019341e-05 0.000000e+00 3.296000e-01 4.670400e+00 +217 2.019392e-05 0.000000e+00 3.040000e-01 4.696000e+00 +218 2.019494e-05 0.000000e+00 2.528000e-01 4.747200e+00 +219 2.019699e-05 0.000000e+00 1.504000e-01 4.849600e+00 +220 2.020000e-05 0.000000e+00 4.796163e-14 5.000000e+00 +221 2.020041e-05 0.000000e+00 0.000000e+00 5.000000e+00 +222 2.020123e-05 0.000000e+00 0.000000e+00 5.000000e+00 +223 2.020287e-05 0.000000e+00 0.000000e+00 5.000000e+00 +224 2.020614e-05 0.000000e+00 0.000000e+00 5.000000e+00 +225 2.021270e-05 0.000000e+00 0.000000e+00 5.000000e+00 +226 2.022580e-05 0.000000e+00 0.000000e+00 5.000000e+00 +227 2.025202e-05 0.000000e+00 0.000000e+00 5.000000e+00 +228 2.030445e-05 0.000000e+00 0.000000e+00 5.000000e+00 + +Index time V(3) V(7) V(8) +-------------------------------------------------------------------------------- +229 2.040931e-05 0.000000e+00 0.000000e+00 5.000000e+00 +230 2.061902e-05 0.000000e+00 0.000000e+00 5.000000e+00 +231 2.103845e-05 0.000000e+00 0.000000e+00 5.000000e+00 +232 2.163845e-05 0.000000e+00 0.000000e+00 5.000000e+00 +233 2.220000e-05 0.000000e+00 2.117582e-14 5.000000e+00 +234 2.221000e-05 0.000000e+00 5.000000e-01 4.500000e+00 +235 2.223000e-05 0.000000e+00 1.500000e+00 3.500000e+00 +236 2.223400e-05 0.000000e+00 1.700000e+00 3.300000e+00 +237 2.223401e-05 5.000000e-02 1.700500e+00 3.299500e+00 +238 2.223403e-05 1.500000e-01 1.701500e+00 3.298500e+00 +239 2.223407e-05 3.500000e-01 1.703500e+00 3.296500e+00 +240 2.223410e-05 5.000000e-01 1.705000e+00 3.295000e+00 +241 2.223411e-05 5.000000e-01 1.705400e+00 3.294600e+00 +242 2.223412e-05 5.000000e-01 1.706200e+00 3.293800e+00 +243 2.223416e-05 5.000000e-01 1.707800e+00 3.292200e+00 +244 2.223422e-05 5.000000e-01 1.711000e+00 3.289000e+00 +245 2.223435e-05 5.000000e-01 1.717400e+00 3.282600e+00 +246 2.223460e-05 5.000000e-01 1.730200e+00 3.269800e+00 +247 2.223512e-05 5.000000e-01 1.755800e+00 3.244200e+00 +248 2.223614e-05 5.000000e-01 1.807000e+00 3.193000e+00 +249 2.223819e-05 5.000000e-01 1.909400e+00 3.090600e+00 +250 2.224228e-05 5.000000e-01 2.114200e+00 2.885800e+00 +251 2.224628e-05 5.000000e-01 2.314200e+00 2.685800e+00 +252 2.224637e-05 9.500000e-01 2.318700e+00 2.681300e+00 +253 2.224655e-05 1.850000e+00 2.327700e+00 2.672300e+00 +254 2.224691e-05 3.650000e+00 2.345700e+00 2.654300e+00 +255 2.224718e-05 5.000000e+00 2.359200e+00 2.640800e+00 +256 2.224726e-05 5.000000e+00 2.362800e+00 2.637200e+00 +257 2.224740e-05 5.000000e+00 2.370000e+00 2.630000e+00 +258 2.224769e-05 5.000000e+00 2.384400e+00 2.615600e+00 +259 2.224826e-05 5.000000e+00 2.413200e+00 2.586800e+00 +260 2.224942e-05 5.000000e+00 2.470800e+00 2.529200e+00 +261 2.225172e-05 5.000000e+00 2.586000e+00 2.414000e+00 +262 2.225633e-05 5.000000e+00 2.816400e+00 2.183600e+00 +263 2.226554e-05 5.000000e+00 3.277200e+00 1.722800e+00 +264 2.226954e-05 5.000000e+00 3.477200e+00 1.522800e+00 +265 2.226963e-05 4.550000e+00 3.481700e+00 1.518300e+00 +266 2.226981e-05 3.650000e+00 3.490700e+00 1.509300e+00 +267 2.227017e-05 1.850000e+00 3.508700e+00 1.491300e+00 +268 2.227044e-05 5.000000e-01 3.522200e+00 1.477800e+00 +269 2.227052e-05 5.000000e-01 3.525800e+00 1.474200e+00 +270 2.227066e-05 5.000000e-01 3.533000e+00 1.467000e+00 +271 2.227095e-05 5.000000e-01 3.547400e+00 1.452600e+00 +272 2.227152e-05 5.000000e-01 3.576200e+00 1.423800e+00 +273 2.227268e-05 5.000000e-01 3.633800e+00 1.366200e+00 +274 2.227498e-05 5.000000e-01 3.749000e+00 1.251000e+00 +275 2.227959e-05 5.000000e-01 3.979400e+00 1.020600e+00 +276 2.228880e-05 5.000000e-01 4.440200e+00 5.598000e-01 +277 2.229280e-05 5.000000e-01 4.640200e+00 3.598000e-01 +278 2.229281e-05 4.500000e-01 4.640700e+00 3.593000e-01 +279 2.229283e-05 3.500000e-01 4.641700e+00 3.583000e-01 +280 2.229287e-05 1.500000e-01 4.643700e+00 3.563000e-01 +281 2.229290e-05 0.000000e+00 4.645200e+00 3.548000e-01 +282 2.229291e-05 0.000000e+00 4.645600e+00 3.544000e-01 +283 2.229293e-05 0.000000e+00 4.646400e+00 3.536000e-01 +284 2.229296e-05 0.000000e+00 4.648000e+00 3.520000e-01 +285 2.229302e-05 0.000000e+00 4.651200e+00 3.488000e-01 +286 2.229315e-05 0.000000e+00 4.657600e+00 3.424000e-01 + +Index time V(3) V(7) V(8) +-------------------------------------------------------------------------------- +287 2.229341e-05 0.000000e+00 4.670400e+00 3.296000e-01 +288 2.229392e-05 0.000000e+00 4.696000e+00 3.040000e-01 +289 2.229494e-05 0.000000e+00 4.747200e+00 2.528000e-01 +290 2.229699e-05 0.000000e+00 4.849600e+00 1.504000e-01 +291 2.230000e-05 0.000000e+00 5.000000e+00 2.664535e-14 +292 2.230041e-05 0.000000e+00 5.000000e+00 0.000000e+00 +293 2.230123e-05 0.000000e+00 5.000000e+00 0.000000e+00 +294 2.230287e-05 0.000000e+00 5.000000e+00 0.000000e+00 +295 2.230614e-05 0.000000e+00 5.000000e+00 0.000000e+00 +296 2.231270e-05 0.000000e+00 5.000000e+00 0.000000e+00 +297 2.232580e-05 0.000000e+00 5.000000e+00 0.000000e+00 +298 2.235202e-05 0.000000e+00 5.000000e+00 0.000000e+00 +299 2.240445e-05 0.000000e+00 5.000000e+00 0.000000e+00 +300 2.250931e-05 0.000000e+00 5.000000e+00 0.000000e+00 +301 2.271902e-05 0.000000e+00 5.000000e+00 0.000000e+00 +302 2.313845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +303 2.373845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +304 2.433845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +305 2.493845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +306 2.553845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +307 2.613845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +308 2.673845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +309 2.733845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +310 2.793845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +311 2.853845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +312 2.913845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +313 2.973845e-05 0.000000e+00 5.000000e+00 0.000000e+00 +314 3.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00 diff --git a/Examples/CMOS_Inverter/.CMOS_Inverter.cir.out.swp b/Examples/CMOS_Inverter/.CMOS_Inverter.cir.out.swp Binary files differnew file mode 100644 index 00000000..f2abf69d --- /dev/null +++ b/Examples/CMOS_Inverter/.CMOS_Inverter.cir.out.swp diff --git a/Examples/CMOS_Inverter/CMOSN.lib b/Examples/CMOS_Inverter/CMOSN.lib new file mode 100644 index 00000000..93bdc23b --- /dev/null +++ b/Examples/CMOS_Inverter/CMOSN.lib @@ -0,0 +1,22 @@ +.model CMOSN NMOS( UB1=-7.61E-18 VSAT=9.366802E4 NFACTOR=2.4358891 CJSWG=3.3E-10 LINT=1.571424E-8 ++ WW=0 WR=1 WLN=1 PVAG=3.85243E-3 MJSW=0.1060414 ++ AGS=0.3939741 DSUB=0.0167075 LKETA=-0.0104078 LW=0 RDSW=105.5517558 ++ KETA=-5.180424E-4 CJSW=2.512138E-10 PRT=0 WL=0 LEVEL=8 ++ UA1=4.31E-9 XPART=0.5 PRDSW=-5 VERSION=3.2 VTH0=0.3823463 ++ B0=-6.413949E-9 B1=-1E-7 W0=1E-7 U0=280.633249 PRWG=0.5 ++ PRWB=-0.1998871 PVTH0=-1.192722E-3 VOFF=-0.0955434 DVT2W=0 NLX=1.910552E-7 ++ PB=0.8 LLN=1 PCLM=0.8073191 PK2=6.450505E-5 KT1L=0 ++ PVSAT=969.1480157 PETA0=1E-4 WINT=7.904732E-10 MJ=0.3864502 MOBMOD=1 ++ WWL=0 WWN=1 UA=-1.208537E-9 UC=5.342807E-11 DWG=1.297221E-9 ++ ETA0=3.104851E-3 TOX=4.1E-9 K3=0.0431669 K2=4.774618E-3 K1=0.5810697 ++ PDIBLCB=-0.1 CDSC=2.4E-4 PU0=6.3268729 DVT0W=0 CGBO=1E-12 ++ XJ=1E-7 CGDO=7.08E-10 XL=0 CF=0 PSCBE1=8E10 ++ CDSCB=0 CDSCD=0 XW=-1E-8 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PUA=2.226552E-11 PUB=0 ETAB=-2.512384E-5 TNOM=27 MJSWG=0.1060414 ++ CJ=9.68858E-4 WKETA=-4.27294E-4 CAPMOD=2 LWN=1 LWL=0 ++ CIT=0 PKETA=-1.049509E-3 CGSO=7.08E-10 LL=0 KT1=-0.11 ++ KT2=0.022 DROUT=0.7875618 A1=0 A0=1.7593146 A2=1 ++ UC1=-5.6E-11 UTE=-1.5 PBSWG=0.809286 K3B=1.1498346 DWB=1.479041E-9 ++ AT=3.3E4 PBSW=0.809286 UB=2.158625E-18 RSH=6.7 PSCBE2=9.213635E-10 ++ DVT1W=0 NCH=2.3549E17 DELTA=0.01 DVT2=0.0713729 DVT0=1.2894824 ++ DVT1=0.3622063 )
\ No newline at end of file diff --git a/Examples/CMOS_Inverter/CMOSP.lib b/Examples/CMOS_Inverter/CMOSP.lib new file mode 100644 index 00000000..f2c89d2e --- /dev/null +++ b/Examples/CMOS_Inverter/CMOSP.lib @@ -0,0 +1,22 @@ +.model CMOSP PMOS( UB1=-7.61E-18 VSAT=1.329694E5 NFACTOR=1.9424315 CJSWG=4.22E-10 LINT=3.028832E-8 ++ WW=0 WR=1 WLN=1 PVAG=15 MJSW=0.3752089 ++ AGS=0.3641621 DSUB=0.7343015 LKETA=2.955547E-3 LW=0 RDSW=168.5705677 ++ KETA=0.0134667 CJSW=2.242609E-10 PRT=0 WL=0 LEVEL=8 ++ UA1=4.31E-9 XPART=0.5 PRDSW=11.5315407 VERSION=3.2 VTH0=-0.3938813 ++ B0=3.427126E-7 B1=1.062928E-6 W0=1E-6 U0=115.6852975 PRWG=0.5 ++ PRWB=-0.4987371 PVTH0=1.888482E-3 VOFF=-0.0994037 DVT2W=0 NLX=1.313191E-7 ++ PB=0.8421173 LLN=1 PCLM=3.2579974 PK2=1.559399E-3 KT1L=0 ++ PVSAT=50 PETA0=1E-4 WINT=0 MJ=0.4109788 MOBMOD=1 ++ WWL=0 WWN=1 UA=1.505832E-9 UC=-1E-10 DWG=-2.349633E-8 ++ ETA0=0.0608072 TOX=4.1E-9 K3=0.0993095 K2=0.0360586 K1=0.5479015 ++ PDIBLCB=-1E-3 CDSC=2.4E-4 PU0=-1.1105313 DVT0W=0 CGBO=1E-12 ++ XJ=1E-7 CGDO=6.32E-10 XL=0 CF=0 PSCBE1=1.454878E10 ++ CDSCB=0 CDSCD=0 XW=-1E-8 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 ++ PUA=-4.62102E-11 PUB=1E-21 ETAB=-0.0426148 TNOM=27 MJSWG=0.3752089 ++ CJ=1.172138E-3 WKETA=0.0319301 CAPMOD=2 LWN=1 LWL=0 ++ CIT=0 PKETA=-4.346368E-3 CGSO=6.32E-10 LL=0 KT1=-0.11 ++ KT2=0.022 DROUT=0 A1=0.6859506 A0=1.7590478 A2=0.3506788 ++ UC1=-5.6E-11 UTE=-1.5 PBSWG=0.8 K3B=5.7086622 DWB=-7.152486E-9 ++ AT=3.3E4 PBSW=0.8 UB=1E-21 RSH=7.8 PSCBE2=4.202027E-9 ++ DVT1W=0 NCH=4.1589E17 DELTA=0.01 DVT2=0.1 DVT0=0.4911363 ++ DVT1=0.2227356 )
\ No newline at end of file diff --git a/Examples/CMOS_Inverter/CMOS_Inverter-cache.bak b/Examples/CMOS_Inverter/CMOS_Inverter-cache.bak new file mode 100644 index 00000000..40de879d --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter-cache.bak @@ -0,0 +1,118 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 28 April 2015 10:53:44 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# MOS_N +# +DEF MOS_N Q 0 0 N Y 1 F N +F0 "Q" 10 170 60 H V R CNN +F1 "MOS_N" 10 -150 60 H V R CNN +ALIAS MOSFET_N +DRAW +P 2 0 1 8 -50 -100 -50 100 N +P 2 0 1 10 0 -150 0 150 N +P 2 0 1 0 100 -100 0 -100 N +P 2 0 1 0 100 100 0 100 N +P 3 0 1 8 100 -100 100 0 50 0 N +P 5 0 1 8 50 30 50 -30 0 0 50 30 50 30 N +X D D 100 200 100 D 40 40 1 1 P +X G G -200 0 150 R 40 40 1 1 I +X S S 100 -200 100 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# MOS_P +# +DEF MOS_P Q 0 40 Y N 1 F N +F0 "Q" 0 190 60 H V R CNN +F1 "MOS_P" 0 -180 60 H V R CNN +ALIAS MOSFET_P +DRAW +P 2 0 1 8 -50 -100 -50 100 N +P 2 0 1 10 0 -150 0 150 N +P 2 0 1 8 30 0 0 0 N +P 2 0 1 0 100 -100 0 -100 N +P 2 0 1 0 100 100 0 100 N +P 3 0 1 0 80 0 100 0 100 -100 N +P 5 0 1 8 30 40 30 -30 80 0 30 40 30 40 N +X D D 100 200 100 D 40 40 1 1 P +X G G -200 0 150 R 40 40 1 1 I +X S S 100 -200 100 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/CMOS_Inverter/CMOS_Inverter-cache.lib b/Examples/CMOS_Inverter/CMOS_Inverter-cache.lib new file mode 100644 index 00000000..2c35750f --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter-cache.lib @@ -0,0 +1,136 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 0 +# +DEF 0 #GND 0 0 Y Y 1 F P +F0 "#GND" 0 -100 40 H I C CNN +F1 "0" 0 -70 40 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X 0 1 0 0 0 R 40 40 1 1 W N +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# MOS_N +# +DEF MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 E +X G 2 -100 -200 210 R 50 50 1 1 I +X S 3 200 -400 100 U 50 50 1 1 C +X B 4 300 -350 98 U 47 47 1 1 I +ENDDRAW +ENDDEF +# +# MOS_P +# +DEF MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 C +X G 2 -150 0 210 R 50 50 1 1 I +X S 3 150 -200 100 U 50 50 1 1 E +X B 4 250 -150 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.bak b/Examples/CMOS_Inverter/CMOS_Inverter.bak new file mode 100644 index 00000000..04c9e079 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:sourcesSpice +LIBS:eSim_Analog +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Devices +LIBS:CMOS_Inverter-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5800 2400 +Wire Wire Line + 5900 2400 5800 2400 +Connection ~ 4200 3350 +Wire Wire Line + 4200 3200 4200 3350 +Wire Wire Line + 6550 3300 6550 3550 +Wire Wire Line + 5800 1150 5800 1400 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 2900 3350 +Wire Wire Line + 2900 3100 2900 3550 +Wire Wire Line + 3100 3350 2900 3350 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 4000 3350 5050 3350 +Connection ~ 5050 3350 +Connection ~ 5800 3300 +Wire Wire Line + 6550 3850 6550 4400 +Wire Wire Line + 6550 4400 5800 4400 +Connection ~ 5800 4400 +Connection ~ 6300 3300 +Text GLabel 5900 2400 2 60 Input ~ 0 +vcc +Text GLabel 6300 3150 1 60 Input ~ 0 +out +Text GLabel 4200 3200 1 60 Input ~ 0 +in +$Comp +L C C1 +U 1 1 551BDFAE +P 6550 3700 +F 0 "C1" H 6600 3800 50 0000 L CNN +F 1 "1u" H 6600 3600 50 0000 L CNN +F 2 "" H 6550 3700 60 0001 C CNN +F 3 "" H 6550 3700 60 0001 C CNN + 1 6550 3700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 551BDA61 +P 5800 1150 +F 0 "#PWR01" H 5800 1150 30 0001 C CNN +F 1 "GND" H 5800 1080 30 0001 C CNN +F 2 "" H 5800 1150 60 0001 C CNN +F 3 "" H 5800 1150 60 0001 C CNN + 1 5800 1150 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 551BDA5A +P 5800 4700 +F 0 "#PWR02" H 5800 4700 30 0001 C CNN +F 1 "GND" H 5800 4630 30 0001 C CNN +F 2 "" H 5800 4700 60 0001 C CNN +F 3 "" H 5800 4700 60 0001 C CNN + 1 5800 4700 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG03 +U 1 1 54F86E05 +P 2900 3100 +F 0 "#FLG03" H 2900 3370 30 0001 C CNN +F 1 "PWR_FLAG" H 2900 3330 30 0000 C CNN +F 2 "" H 2900 3100 60 0001 C CNN +F 3 "" H 2900 3100 60 0001 C CNN + 1 2900 3100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 54F86DBA +P 2900 3550 +F 0 "#PWR04" H 2900 3550 30 0001 C CNN +F 1 "GND" H 2900 3480 30 0001 C CNN +F 2 "" H 2900 3550 60 0001 C CNN +F 3 "" H 2900 3550 60 0001 C CNN + 1 2900 3550 + 1 0 0 -1 +$EndComp +$Comp +L dc v1 +U 1 1 556C4B7E +P 3550 3350 +F 0 "v1" H 3350 3450 60 0000 C CNN +F 1 "dc" H 3350 3300 60 0000 C CNN +F 2 "R1" H 3250 3350 60 0000 C CNN +F 3 "" H 3550 3350 60 0000 C CNN + 1 3550 3350 + 0 1 1 0 +$EndComp +$Comp +L dc v2 +U 1 1 556C4BA7 +P 5800 1850 +F 0 "v2" H 5600 1950 60 0000 C CNN +F 1 "5" H 5600 1800 60 0000 C CNN +F 2 "R1" H 5500 1850 60 0000 C CNN +F 3 "" H 5800 1850 60 0000 C CNN + 1 5800 1850 + -1 0 0 1 +$EndComp +Wire Wire Line + 6300 3150 6300 3300 +Wire Wire Line + 5800 3300 6550 3300 +$Comp +L MOS_N M1 +U 1 1 556F0E6F +P 5600 3650 +F 0 "M1" H 5600 3500 50 0000 R CNN +F 1 "MOS_N" H 5700 3600 50 0000 R CNN +F 2 "" H 5900 3350 29 0000 C CNN +F 3 "" H 5700 3450 60 0000 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L MOS_P M2 +U 1 1 556F0EE6 +P 5650 2700 +F 0 "M2" H 5600 2750 50 0000 R CNN +F 1 "MOS_P" H 5700 2850 50 0000 R CNN +F 2 "" H 5900 2800 29 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 1 0 0 1 +$EndComp +Wire Wire Line + 5800 4050 5800 4700 +Wire Wire Line + 5900 4150 5800 4150 +Connection ~ 5800 4150 +Connection ~ 5800 2450 +Wire Wire Line + 5900 4000 5900 4150 +Wire Wire Line + 5900 2550 5900 2450 +Wire Wire Line + 5900 2450 5800 2450 +$EndSCHEMATC diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.cir b/Examples/CMOS_Inverter/CMOS_Inverter.cir new file mode 100644 index 00000000..b435cd1c --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.cir @@ -0,0 +1,13 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 12 12:25:06 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +C1 3 4 1u +v1 1 4 dc +v2 2 4 5 +M1 3 1 4 4 MOS_N +M2 3 1 2 2 MOS_P + +.end diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.cir.ckt b/Examples/CMOS_Inverter/CMOS_Inverter.cir.ckt new file mode 100644 index 00000000..54d4aaa5 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.cir.ckt @@ -0,0 +1,14 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 29 april 2015 05:48:14 pm ist +.include mos_n.lib +.include mos_p.lib + +v1 in gnd dc 5 +m2 out in gnd gnd mos_n M=100u L=100u W=100u +m1 out in vcc vcc mos_p M=100u L=100u W=100u +c1 out gnd 1u +v2 vcc gnd dc 5 +* Plotting option vplot8_1 + +.tran 10e-03 100e-03 0e-03 +.plot v(in) v(out) +.end diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.cir.out b/Examples/CMOS_Inverter/CMOS_Inverter.cir.out new file mode 100644 index 00000000..318298d5 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 3 14:55:15 2015 + +.include PMOS-5um.lib +.include NMOS-5um.lib +c1 out gnd 1u +v1 in gnd dc 5 +v2 vcc gnd 5 +m1 out in gnd gnd mos_n W=100u L=100u M=1 +m2 out in vcc vcc mos_p W=100u L=100u M=1 +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.pro b/Examples/CMOS_Inverter/CMOS_Inverter.pro new file mode 100644 index 00000000..2b819749 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.pro @@ -0,0 +1,42 @@ +update=Fri Jun 12 12:18:51 2015 +last_client=eeschema +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=sourcesSpice +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName36=/home/gaurav/pspice diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.proj b/Examples/CMOS_Inverter/CMOS_Inverter.proj new file mode 100644 index 00000000..f03822e4 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.proj @@ -0,0 +1 @@ +schematicFile CMOS_Inverter.sch diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.sch b/Examples/CMOS_Inverter/CMOS_Inverter.sch new file mode 100644 index 00000000..2829d5d5 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.sch @@ -0,0 +1,249 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:sourcesSpice +LIBS:eSim_Analog +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Devices +LIBS:pspice +LIBS:CMOS_Inverter-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5800 2400 +Wire Wire Line + 5900 2400 5800 2400 +Connection ~ 4200 3350 +Wire Wire Line + 4200 3200 4200 3350 +Wire Wire Line + 6550 3300 6550 3550 +Wire Wire Line + 5800 1150 5800 1400 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 2900 3350 +Wire Wire Line + 2900 3100 2900 3550 +Wire Wire Line + 3100 3350 2900 3350 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 4000 3350 5050 3350 +Connection ~ 5050 3350 +Connection ~ 5800 3300 +Wire Wire Line + 6550 3850 6550 4400 +Wire Wire Line + 6550 4400 5800 4400 +Connection ~ 5800 4400 +Connection ~ 6300 3300 +Text GLabel 5900 2400 2 60 Input ~ 0 +vcc +Text GLabel 6300 3150 1 60 Input ~ 0 +out +Text GLabel 4200 3200 1 60 Input ~ 0 +in +$Comp +L C C1 +U 1 1 551BDFAE +P 6550 3700 +F 0 "C1" H 6600 3800 50 0000 L CNN +F 1 "1u" H 6600 3600 50 0000 L CNN +F 2 "" H 6550 3700 60 0001 C CNN +F 3 "" H 6550 3700 60 0001 C CNN + 1 6550 3700 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 54F86E05 +P 2900 3100 +F 0 "#FLG01" H 2900 3370 30 0001 C CNN +F 1 "PWR_FLAG" H 2900 3330 30 0000 C CNN +F 2 "" H 2900 3100 60 0001 C CNN +F 3 "" H 2900 3100 60 0001 C CNN + 1 2900 3100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 54F86DBA +P 2900 3550 +F 0 "#PWR02" H 2900 3550 30 0001 C CNN +F 1 "GND" H 2900 3480 30 0001 C CNN +F 2 "" H 2900 3550 60 0001 C CNN +F 3 "" H 2900 3550 60 0001 C CNN + 1 2900 3550 + 1 0 0 -1 +$EndComp +$Comp +L dc v1 +U 1 1 556C4B7E +P 3550 3350 +F 0 "v1" H 3350 3450 60 0000 C CNN +F 1 "dc" H 3350 3300 60 0000 C CNN +F 2 "R1" H 3250 3350 60 0000 C CNN +F 3 "" H 3550 3350 60 0000 C CNN + 1 3550 3350 + 0 1 1 0 +$EndComp +$Comp +L dc v2 +U 1 1 556C4BA7 +P 5800 1850 +F 0 "v2" H 5600 1950 60 0000 C CNN +F 1 "5" H 5600 1800 60 0000 C CNN +F 2 "R1" H 5500 1850 60 0000 C CNN +F 3 "" H 5800 1850 60 0000 C CNN + 1 5800 1850 + -1 0 0 1 +$EndComp +Wire Wire Line + 6300 3150 6300 3300 +Wire Wire Line + 5800 3300 6550 3300 +$Comp +L MOS_N M1 +U 1 1 556F0E6F +P 5600 3650 +F 0 "M1" H 5600 3500 50 0000 R CNN +F 1 "MOS_N" H 5700 3600 50 0000 R CNN +F 2 "" H 5900 3350 29 0000 C CNN +F 3 "" H 5700 3450 60 0000 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L MOS_P M2 +U 1 1 556F0EE6 +P 5650 2700 +F 0 "M2" H 5600 2750 50 0000 R CNN +F 1 "MOS_P" H 5700 2850 50 0000 R CNN +F 2 "" H 5900 2800 29 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 1 0 0 1 +$EndComp +Wire Wire Line + 5800 4050 5800 4700 +Wire Wire Line + 5900 4150 5800 4150 +Connection ~ 5800 4150 +Connection ~ 5800 2450 +Wire Wire Line + 5900 4000 5900 4150 +Wire Wire Line + 5900 2550 5900 2450 +Wire Wire Line + 5900 2450 5800 2450 +$Comp +L PWR_FLAG #FLG03 +U 1 1 557AB7F7 +P 5600 4500 +F 0 "#FLG03" H 5600 4595 50 0001 C CNN +F 1 "PWR_FLAG" H 5600 4680 50 0000 C CNN +F 2 "" H 5600 4500 60 0000 C CNN +F 3 "" H 5600 4500 60 0000 C CNN + 1 5600 4500 + 1 0 0 -1 +$EndComp +Connection ~ 5800 1300 +Wire Wire Line + 5600 4500 5600 4550 +Wire Wire Line + 5600 4550 5800 4550 +Connection ~ 5800 4550 +Wire Wire Line + 6550 4300 6550 4350 +Connection ~ 6550 4350 +$Comp +L 0 #GND05 +U 1 1 557ACE40 +P 5800 1150 +F 0 "#GND05" H 5800 1050 40 0001 C CNN +F 1 "0" H 5800 1080 40 0000 C CNN +F 2 "" H 5800 1150 60 0000 C CNN +F 3 "" H 5800 1150 60 0000 C CNN + 1 5800 1150 + -1 0 0 1 +$EndComp +$Comp +L 0 #GND06 +U 1 1 557ACE67 +P 5800 4700 +F 0 "#GND06" H 5800 4600 40 0001 C CNN +F 1 "0" H 5800 4630 40 0000 C CNN +F 2 "" H 5800 4700 60 0000 C CNN +F 3 "" H 5800 4700 60 0000 C CNN + 1 5800 4700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR07 +U 1 1 557ACF98 +P 5950 1300 +F 0 "#PWR07" H 5950 1300 30 0001 C CNN +F 1 "GND" H 5950 1230 30 0001 C CNN +F 2 "" H 5950 1300 60 0000 C CNN +F 3 "" H 5950 1300 60 0000 C CNN +F 4 "0" H 5950 1300 60 0001 C CNN "Value" + 1 5950 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1300 5850 1250 +Wire Wire Line + 5850 1250 5950 1250 +Wire Wire Line + 5950 1250 5950 1300 +Wire Wire Line + 5850 1300 5800 1300 +$EndSCHEMATC diff --git a/Examples/CMOS_Inverter/CMOS_Inverter_last_input.txt b/Examples/CMOS_Inverter/CMOS_Inverter_last_input.txt new file mode 100644 index 00000000..5f3d6c29 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter_last_input.txt @@ -0,0 +1,2 @@ +v1 in gnd dc 5 +v2 vcc gnd dc 5 diff --git a/Examples/CMOS_Inverter/NMOS-0.5um.lib b/Examples/CMOS_Inverter/NMOS-0.5um.lib new file mode 100755 index 00000000..2e6f4635 --- /dev/null +++ b/Examples/CMOS_Inverter/NMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 ++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 ++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 ++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 ++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 ++ NSUB=1.40E17 )
\ No newline at end of file diff --git a/Examples/CMOS_Inverter/NMOS-5um.lib b/Examples/CMOS_Inverter/NMOS-5um.lib new file mode 100755 index 00000000..a237e1fe --- /dev/null +++ b/Examples/CMOS_Inverter/NMOS-5um.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/Examples/CMOS_Inverter/PMOS-5um.lib b/Examples/CMOS_Inverter/PMOS-5um.lib new file mode 100755 index 00000000..9c3ed976 --- /dev/null +++ b/Examples/CMOS_Inverter/PMOS-5um.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/Examples/CMOS_Inverter/analysis b/Examples/CMOS_Inverter/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/CMOS_Inverter/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/CMOS_Inverter/b3v3check.log b/Examples/CMOS_Inverter/b3v3check.log new file mode 100644 index 00000000..79783fe3 --- /dev/null +++ b/Examples/CMOS_Inverter/b3v3check.log @@ -0,0 +1,6 @@ +BSIM3 Model (Supports: v3.2, v3.2.2, v3.2.3, v3.2.4) +Parameter Checking. +Model = cmosn +W = 0.0001, L = 0.0001, M = 0.0001 +Warning: Pd = 0 is less than W. +Warning: Ps = 0 is less than W. diff --git a/Examples/CMOS_Inverter/mos_n.lib b/Examples/CMOS_Inverter/mos_n.lib new file mode 100644 index 00000000..a237e1fe --- /dev/null +++ b/Examples/CMOS_Inverter/mos_n.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/Examples/CMOS_Inverter/mos_p.lib b/Examples/CMOS_Inverter/mos_p.lib new file mode 100644 index 00000000..9c3ed976 --- /dev/null +++ b/Examples/CMOS_Inverter/mos_p.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/Examples/CMOS_Inverter/plot_data_i.txt b/Examples/CMOS_Inverter/plot_data_i.txt new file mode 100644 index 00000000..d7d0eed7 --- /dev/null +++ b/Examples/CMOS_Inverter/plot_data_i.txt @@ -0,0 +1,67 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 3 14:55:15 2015 +Transient Analysis Mon Jun 8 15:09:27 2015 +-------------------------------------------------------------------------------- +Index time v1#branch v2#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 -5.01000e-12 +1 1.000000e-05 0.000000e+00 -5.01000e-12 +2 2.000000e-05 -3.65682e-22 -5.01000e-12 +3 4.000000e-05 -3.65269e-22 -5.01000e-12 +4 8.000000e-05 -1.82222e-22 -5.01000e-12 +5 1.600000e-04 -9.07020e-23 -5.01000e-12 +6 3.200000e-04 -4.49480e-23 -5.01000e-12 +7 6.400000e-04 -2.20827e-23 -5.01000e-12 +8 1.280000e-03 -1.06724e-23 -5.01000e-12 +9 2.560000e-03 -5.00782e-24 -5.01000e-12 +10 4.560000e-03 5.534460e-24 -5.01000e-12 +11 6.560000e-03 5.744371e-24 -5.01000e-12 +12 8.560000e-03 5.908101e-24 -5.01000e-12 +13 1.056000e-02 6.035806e-24 -5.01000e-12 +14 1.256000e-02 -4.82024e-25 -5.01000e-12 +15 1.456000e-02 2.904399e-24 -5.01000e-12 +16 1.656000e-02 2.965000e-24 -5.01000e-12 +17 1.856000e-02 3.012266e-24 -5.01000e-12 +18 2.056000e-02 3.049134e-24 -5.01000e-12 +19 2.256000e-02 3.077890e-24 -5.01000e-12 +20 2.456000e-02 3.100317e-24 -5.01000e-12 +21 2.656000e-02 3.117809e-24 -5.01000e-12 +22 2.856000e-02 3.131453e-24 -5.01000e-12 +23 3.056000e-02 3.142094e-24 -5.01000e-12 +24 3.256000e-02 3.150396e-24 -5.01000e-12 +25 3.456000e-02 3.156872e-24 -5.01000e-12 +26 3.656000e-02 3.161923e-24 -5.01000e-12 +27 3.856000e-02 3.165861e-24 -5.01000e-12 +28 4.056000e-02 3.168934e-24 -5.01000e-12 +29 4.256000e-02 3.171332e-24 -5.01000e-12 +30 4.456000e-02 3.173202e-24 -5.01000e-12 +31 4.656000e-02 3.174662e-24 -5.01000e-12 +32 4.856000e-02 3.175800e-24 -5.01000e-12 +33 5.056000e-02 3.176686e-24 -5.01000e-12 +34 5.256000e-02 3.177376e-24 -5.01000e-12 +35 5.456000e-02 3.177916e-24 -5.01000e-12 +36 5.656000e-02 3.178339e-24 -5.01000e-12 +37 5.856000e-02 3.178667e-24 -5.01000e-12 +38 6.056000e-02 3.178922e-24 -5.01000e-12 +39 6.256000e-02 3.179121e-24 -5.01000e-12 +40 6.456000e-02 3.179277e-24 -5.01000e-12 +41 6.656000e-02 3.179400e-24 -5.01000e-12 +42 6.856000e-02 3.179495e-24 -5.01000e-12 +43 7.056000e-02 3.179569e-24 -5.01000e-12 +44 7.256000e-02 3.179627e-24 -5.01000e-12 +45 7.456000e-02 3.179673e-24 -5.01000e-12 +46 7.656000e-02 3.179707e-24 -5.01000e-12 +47 7.856000e-02 3.179731e-24 -5.01000e-12 +48 8.056000e-02 3.179753e-24 -5.01000e-12 +49 8.256000e-02 3.179771e-24 -5.01000e-12 +50 8.456000e-02 3.179783e-24 -5.01000e-12 +51 8.656000e-02 3.179793e-24 -5.01000e-12 +52 8.856000e-02 3.179802e-24 -5.01000e-12 +53 9.056000e-02 3.179808e-24 -5.01000e-12 +54 9.256000e-02 3.179811e-24 -5.01000e-12 + +Index time v1#branch v2#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 3.179814e-24 -5.01000e-12 +56 9.656000e-02 3.179817e-24 -5.01000e-12 +57 9.856000e-02 3.179820e-24 -5.01000e-12 +58 1.000000e-01 3.129705e-24 -5.01000e-12 diff --git a/Examples/CMOS_Inverter/plot_data_v.txt b/Examples/CMOS_Inverter/plot_data_v.txt new file mode 100644 index 00000000..8c3925b3 --- /dev/null +++ b/Examples/CMOS_Inverter/plot_data_v.txt @@ -0,0 +1,67 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 3 14:55:15 2015 +Transient Analysis Mon Jun 8 15:09:27 2015 +-------------------------------------------------------------------------------- +Index time in out vcc +-------------------------------------------------------------------------------- +0 0.000000e+00 5.000000e+00 4.053196e-08 5.000000e+00 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+19 2.256000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +20 2.456000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +21 2.656000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +22 2.856000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +23 3.056000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +24 3.256000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +25 3.456000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +26 3.656000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +27 3.856000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +28 4.056000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +29 4.256000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +30 4.456000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +31 4.656000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +32 4.856000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +33 5.056000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +34 5.256000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +35 5.456000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +36 5.656000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +37 5.856000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +38 6.056000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +39 6.256000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +40 6.456000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +41 6.656000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +42 6.856000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +43 7.056000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +44 7.256000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +45 7.456000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +46 7.656000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +47 7.856000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +48 8.056000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +49 8.256000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +50 8.456000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +51 8.656000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +52 8.856000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +53 9.056000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +54 9.256000e-02 5.000000e+00 4.053196e-08 5.000000e+00 + +Index time in out vcc +-------------------------------------------------------------------------------- +55 9.456000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +56 9.656000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +57 9.856000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +58 1.000000e-01 5.000000e+00 4.053196e-08 5.000000e+00 diff --git a/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET diff --git a/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET-cache.lib b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET-cache.lib new file mode 100644 index 00000000..08b76f77 --- /dev/null +++ b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET-cache.lib @@ -0,0 +1,145 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# AC +# +DEF AC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 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3550 3100 + 1 0 0 -1 +$EndComp +$Comp +L vplot8_1 U2 +U 2 1 554CE5B6 +P 8500 2750 +F 0 "U2" H 8350 2850 50 0000 C CNN +F 1 "vplot8_1" H 8650 2850 50 0000 C CNN +F 2 "" H 8500 2750 60 0000 C CNN +F 3 "" H 8500 2750 60 0000 C CNN + 2 8500 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8500 3050 8500 3100 +Connection ~ 8500 3100 +Connection ~ 3550 3500 +$Comp +L PWR_FLAG #FLG03 +U 1 1 554CEAE9 +P 6500 1200 +F 0 "#FLG03" H 6500 1295 50 0001 C CNN +F 1 "PWR_FLAG" H 6500 1380 50 0000 C CNN +F 2 "" H 6500 1200 60 0000 C CNN +F 3 "" H 6500 1200 60 0000 C CNN + 1 6500 1200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 1200 6500 1250 +Connection ~ 6500 1250 +$Comp +L AC v1 +U 1 1 554CED04 +P 3550 4300 +F 0 "v1" H 3350 4400 60 0000 C CNN +F 1 "AC" H 3350 4250 60 0000 C CNN +F 2 "R1" H 3250 4300 60 0000 C CNN +F 3 "" H 3550 4300 60 0000 C CNN + 1 3550 4300 + 1 0 0 -1 +$EndComp +$Comp +L NJF J1 +U 1 1 557065CE +P 6200 3500 +F 0 "J1" H 6100 3550 50 0000 R CNN +F 1 "NJF" H 6150 3650 50 0000 R CNN +F 2 "" H 6400 3600 29 0000 C CNN +F 3 "" H 6200 3500 60 0000 C CNN + 1 6200 3500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.cir b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.cir new file mode 100644 index 00000000..438c3b7b --- /dev/null +++ b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.cir @@ -0,0 +1,26 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jun 4 14:46:46 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R3 5 6 4.7k +R4 7 0 1k +R1 1 3 10k +C1 8 1 0.01u +R2 0 8 1Meg +C2 0 8 5p +C3 8 7 4p +C4 8 6 2p +C5 6 7 0.5p +C6 7 0 2u +C7 6 2 5u +C8 2 0 6p +R5 2 0 2.2k +v2 5 0 dc +*U1 3 vplot8_1 +*U2 2 vplot8_1 +v1 3 0 AC +J1 6 8 7 NJF + +.end diff --git a/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.cir (copy).out b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.cir (copy).out new file mode 100644 index 00000000..be918003 --- /dev/null +++ b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.cir (copy).out @@ -0,0 +1,30 @@ +* eeschema netlist version 1.1 (spice format) creation date: fri may 8 15:00:52 2015 + +.include NJF.lib +j1 6 8 7 J2N3819 +r3 5 6 0.7k +r4 7 0 1k +r1 1 3 10k +c1 8 1 0.01u +r2 0 8 1meg +c2 0 8 5p +c3 8 7 0p +c4 8 6 2p +c5 6 7 0.5p +c6 7 0 2u +c7 6 2 5u +c8 2 0 6p +r5 2 0 2.2k +v2 5 0 dc 20 +v1 3 0 ac 0.1m +.ac lin 100 10Hz 10Meg + +* Control Statements +.control +run +Plot v(3) +plot v(2) +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.cir.out b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.cir.out new file mode 100644 index 00000000..4f27d396 --- /dev/null +++ b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.cir.out @@ -0,0 +1,27 @@ +* eeschema netlist version 1.1 (spice format) creation date: thu jun 4 14:46:46 2015 + +r3 5 6 4.7k +r4 7 0 1k +r1 1 3 10k +c1 8 1 0.01u +r2 0 8 1meg +c2 0 8 5p +c3 8 7 4p +c4 8 6 2p +c5 6 7 0.5p +c6 7 0 2u +c7 6 2 5u +c8 2 0 6p +r5 2 0 2.2k +v2 5 0 dc 0 +v1 3 0 ac 0 +j1 6 8 7 njf +.dc 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.pro b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.pro new file mode 100644 index 00000000..bf72934f --- /dev/null +++ b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.pro @@ -0,0 +1,82 @@ +update=Fri May 8 15:01:43 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/FreeEDA/library/sourcesSpice +LibName36=/home/gaurav/Desktop/FreeEDA/library/measurementSpice +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName=Pcbnew +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=1 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 diff --git a/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.proj b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.proj new file mode 100644 index 00000000..a42dbf28 --- /dev/null +++ b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.proj @@ -0,0 +1 @@ +schematicFile FrequencyResponse_JFET.sch diff --git a/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.sch b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.sch new file mode 100644 index 00000000..d08f5ae9 --- /dev/null +++ b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.sch @@ -0,0 +1,368 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:sourcesSpice +LIBS:measurementSpice +LIBS:FrequencyResponse_JFET-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R3 +U 1 1 554CCD03 +P 6300 2600 +F 0 "R3" V 6380 2600 50 0000 C CNN +F 1 "4.7k" V 6300 2600 50 0000 C CNN +F 2 "" V 6230 2600 30 0000 C CNN +F 3 "" H 6300 2600 30 0000 C CNN + 1 6300 2600 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 554CCD26 +P 6300 4400 +F 0 "R4" V 6380 4400 50 0000 C CNN +F 1 "1k" V 6300 4400 50 0000 C CNN +F 2 "" V 6230 4400 30 0000 C CNN +F 3 "" H 6300 4400 30 0000 C CNN + 1 6300 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 554CCD86 +P 4100 3500 +F 0 "R1" V 4180 3500 50 0000 C CNN +F 1 "10k" V 4100 3500 50 0000 C CNN +F 2 "" V 4030 3500 30 0000 C CNN +F 3 "" H 4100 3500 30 0000 C CNN + 1 4100 3500 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 554CCDF0 +P 4650 3500 +F 0 "C1" H 4675 3600 50 0000 L CNN +F 1 "0.01u" H 4675 3400 50 0000 L CNN +F 2 "" H 4688 3350 30 0000 C CNN +F 3 "" H 4650 3500 60 0000 C CNN + 1 4650 3500 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 554CCF0B +P 5150 4300 +F 0 "R2" V 5230 4300 50 0000 C CNN +F 1 "1Meg" V 5150 4300 50 0000 C CNN +F 2 "" V 5080 4300 30 0000 C CNN +F 3 "" H 5150 4300 30 0000 C CNN + 1 5150 4300 + -1 0 0 1 +$EndComp +$Comp +L C C2 +U 1 1 554CCF4F +P 5450 4300 +F 0 "C2" H 5475 4400 50 0000 L CNN +F 1 "5p" H 5475 4200 50 0000 L CNN +F 2 "" H 5488 4150 30 0000 C CNN +F 3 "" H 5450 4300 60 0000 C CNN + 1 5450 4300 + -1 0 0 1 +$EndComp +$Comp +L C C3 +U 1 1 554CCFBE +P 5950 3900 +F 0 "C3" H 5975 4000 50 0000 L CNN +F 1 "4p" H 5975 3800 50 0000 L CNN +F 2 "" H 5988 3750 30 0000 C CNN +F 3 "" H 5950 3900 60 0000 C CNN + 1 5950 3900 + 0 -1 -1 0 +$EndComp +$Comp +L C C4 +U 1 1 554CCFFC +P 6000 3100 +F 0 "C4" H 6025 3200 50 0000 L CNN +F 1 "2p" H 6025 3000 50 0000 L CNN +F 2 "" H 6038 2950 30 0000 C CNN +F 3 "" H 6000 3100 60 0000 C CNN + 1 6000 3100 + 0 -1 -1 0 +$EndComp +$Comp +L C C5 +U 1 1 554CD040 +P 6750 3550 +F 0 "C5" H 6775 3650 50 0000 L CNN +F 1 "0.5p" H 6775 3450 50 0000 L CNN +F 2 "" H 6788 3400 30 0000 C CNN +F 3 "" H 6750 3550 60 0000 C CNN + 1 6750 3550 + 1 0 0 -1 +$EndComp +$Comp +L C C6 +U 1 1 554CD166 +P 6750 4350 +F 0 "C6" H 6775 4450 50 0000 L CNN +F 1 "2u" H 6775 4250 50 0000 L CNN +F 2 "" H 6788 4200 30 0000 C CNN +F 3 "" H 6750 4350 60 0000 C CNN + 1 6750 4350 + 1 0 0 -1 +$EndComp +$Comp +L C C7 +U 1 1 554CD1B0 +P 7350 3100 +F 0 "C7" H 7375 3200 50 0000 L CNN +F 1 "5u" H 7375 3000 50 0000 L CNN +F 2 "" H 7388 2950 30 0000 C CNN +F 3 "" H 7350 3100 60 0000 C CNN + 1 7350 3100 + 0 -1 -1 0 +$EndComp +$Comp +L C C8 +U 1 1 554CD20C +P 8200 3700 +F 0 "C8" H 8225 3800 50 0000 L CNN +F 1 "6p" H 8225 3600 50 0000 L CNN +F 2 "" H 8238 3550 30 0000 C CNN +F 3 "" H 8200 3700 60 0000 C CNN + 1 8200 3700 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 554CD260 +P 8600 3750 +F 0 "R5" V 8680 3750 50 0000 C CNN +F 1 "2.2k" V 8600 3750 50 0000 C CNN +F 2 "" V 8530 3750 30 0000 C CNN +F 3 "" H 8600 3750 30 0000 C CNN + 1 8600 3750 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 554CD6B0 +P 6300 4850 +F 0 "#PWR01" H 6300 4600 50 0001 C CNN +F 1 "GND" H 6300 4700 50 0000 C CNN +F 2 "" H 6300 4850 60 0000 C CNN +F 3 "" H 6300 4850 60 0000 C CNN + 1 6300 4850 + 1 0 0 -1 +$EndComp +$Comp +L dc v2 +U 1 1 554CD920 +P 6300 1800 +F 0 "v2" H 6100 1900 60 0000 C CNN +F 1 "dc" H 6100 1750 60 0000 C CNN +F 2 "R1" H 6000 1800 60 0000 C CNN +F 3 "" H 6300 1800 60 0000 C CNN + 1 6300 1800 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 554CDAE1 +P 6750 1350 +F 0 "#PWR02" H 6750 1100 50 0001 C CNN +F 1 "GND" H 6750 1200 50 0000 C CNN +F 2 "" H 6750 1350 60 0000 C CNN +F 3 "" H 6750 1350 60 0000 C CNN + 1 6750 1350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6300 3300 6300 2750 +Wire Wire Line + 6300 4250 6300 3700 +Wire Wire Line + 4800 3500 6000 3500 +Wire Wire Line + 5450 4150 5450 3500 +Connection ~ 5450 3500 +Wire Wire Line + 5150 4150 5150 3500 +Connection ~ 5150 3500 +Wire Wire Line + 5650 3900 5800 3900 +Wire Wire Line + 5650 3100 5650 3900 +Connection ~ 5650 3500 +Wire Wire Line + 6100 3900 6750 3900 +Connection ~ 6300 3900 +Wire Wire Line + 6750 3900 6750 3700 +Wire Wire Line + 6150 3100 7200 3100 +Connection ~ 6300 3100 +Wire Wire Line + 6750 3100 6750 3400 +Wire Wire Line + 5850 3100 5650 3100 +Connection ~ 6750 3100 +Wire Wire Line + 7500 3100 8600 3100 +Wire Wire Line + 8600 3100 8600 3600 +Wire Wire Line + 8200 3550 8200 3100 +Connection ~ 8200 3100 +Wire Wire Line + 6750 4200 6750 4100 +Wire Wire Line + 6750 4100 6300 4100 +Connection ~ 6300 4100 +Wire Wire Line + 6300 4550 6300 4850 +Wire Wire Line + 4250 3500 4500 3500 +Wire Wire Line + 5150 4450 5150 4800 +Wire Wire Line + 3550 4800 8600 4800 +Connection ~ 6300 4800 +Wire Wire Line + 8600 4800 8600 3900 +Wire Wire Line + 8200 3850 8200 4800 +Connection ~ 8200 4800 +Wire Wire Line + 6750 4500 6750 4800 +Connection ~ 6750 4800 +Wire Wire Line + 5450 4450 5450 4800 +Connection ~ 5450 4800 +Wire Wire Line + 6300 2250 6300 2450 +Wire Wire Line + 6300 1350 6300 1250 +Wire Wire Line + 6300 1250 6750 1250 +Wire Wire Line + 6750 1250 6750 1350 +Wire Wire Line + 3950 3500 3550 3500 +Wire Wire Line + 3550 3400 3550 3850 +Wire Wire Line + 3550 4750 3550 4800 +Connection ~ 5150 4800 +$Comp +L vplot8_1 U1 +U 1 1 554CE506 +P 3550 3100 +F 0 "U1" H 3400 3200 50 0000 C CNN +F 1 "vplot8_1" H 3700 3200 50 0000 C CNN +F 2 "" H 3550 3100 60 0000 C CNN +F 3 "" H 3550 3100 60 0000 C CNN + 1 3550 3100 + 1 0 0 -1 +$EndComp +$Comp +L vplot8_1 U2 +U 2 1 554CE5B6 +P 8500 2750 +F 0 "U2" H 8350 2850 50 0000 C CNN +F 1 "vplot8_1" H 8650 2850 50 0000 C CNN +F 2 "" H 8500 2750 60 0000 C CNN +F 3 "" H 8500 2750 60 0000 C CNN + 2 8500 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8500 3050 8500 3100 +Connection ~ 8500 3100 +Connection ~ 3550 3500 +$Comp +L PWR_FLAG #FLG03 +U 1 1 554CEAE9 +P 6500 1200 +F 0 "#FLG03" H 6500 1295 50 0001 C CNN +F 1 "PWR_FLAG" H 6500 1380 50 0000 C CNN +F 2 "" H 6500 1200 60 0000 C CNN +F 3 "" H 6500 1200 60 0000 C CNN + 1 6500 1200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 1200 6500 1250 +Connection ~ 6500 1250 +$Comp +L AC v1 +U 1 1 554CED04 +P 3550 4300 +F 0 "v1" H 3350 4400 60 0000 C CNN +F 1 "AC" H 3350 4250 60 0000 C CNN +F 2 "R1" H 3250 4300 60 0000 C CNN +F 3 "" H 3550 4300 60 0000 C CNN + 1 3550 4300 + 1 0 0 -1 +$EndComp +$Comp +L NJF J1 +U 1 1 557065CE +P 6200 3500 +F 0 "J1" H 6100 3550 50 0000 R CNN +F 1 "NJF" H 6150 3650 50 0000 R CNN +F 2 "" H 6400 3600 29 0000 C CNN +F 3 "" H 6200 3500 60 0000 C CNN + 1 6200 3500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET_Previous_Values.xml b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET_Previous_Values.xml new file mode 100644 index 00000000..0a1f9f5c --- /dev/null +++ b/Examples/FrequencyResponse_JFET/FrequencyResponse_JFET_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v2 name="Source type">dc<field1 name="Value" /></v2><v1 name="Source type">ac<field1 name="Amplitude" /></v1></source><model /><devicemodel><j1><field /></j1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">2</field2><field3 name="Stop Time">3</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/FrequencyResponse_JFET/NJF.lib b/Examples/FrequencyResponse_JFET/NJF.lib new file mode 100755 index 00000000..dbb2cbae --- /dev/null +++ b/Examples/FrequencyResponse_JFET/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/Examples/FrequencyResponse_JFET/analysis b/Examples/FrequencyResponse_JFET/analysis new file mode 100644 index 00000000..180ad1bd --- /dev/null +++ b/Examples/FrequencyResponse_JFET/analysis @@ -0,0 +1 @@ +.dc 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/Examples/FrequencyResponse_JFET/plot_data_i.txt b/Examples/FrequencyResponse_JFET/plot_data_i.txt new file mode 100644 index 00000000..5b10d536 --- /dev/null +++ b/Examples/FrequencyResponse_JFET/plot_data_i.txt @@ -0,0 +1,217 @@ +* eeschema netlist version 1.1 (spice format) creation date: thu jun 4 14:46:46 2015 +AC Analysis Mon Jun 22 12:00:29 2015 +-------------------------------------------------------------------------------- +Index frequency v1#branch +-------------------------------------------------------------------------------- +0 1.000000e+01 -2.84038e-11, -4.47862e-11 +1 1.010200e+05 -3.25947e-10, -1.47064e-09 +2 2.020300e+05 -9.54017e-10, -2.74464e-09 +3 3.030400e+05 -1.83286e-09, -3.70449e-09 +4 4.040500e+05 -2.80363e-09, -4.33190e-09 +5 5.050600e+05 -3.74860e-09, -4.67582e-09 +6 6.060700e+05 -4.60309e-09, -4.80907e-09 +7 7.070800e+05 -5.34327e-09, -4.80018e-09 +8 8.080900e+05 -5.96933e-09, -4.70259e-09 +9 9.091000e+05 -6.49258e-09, -4.55390e-09 +10 1.010110e+06 -6.92796e-09, -4.37901e-09 +11 1.111120e+06 -7.29029e-09, -4.19365e-09 +12 1.212130e+06 -7.59270e-09, -4.00746e-09 +13 1.313140e+06 -7.84626e-09, -3.82605e-09 +14 1.414150e+06 -8.06002e-09, -3.65254e-09 +15 1.515160e+06 -8.24128e-09, -3.48847e-09 +16 1.616170e+06 -8.39591e-09, -3.33440e-09 +17 1.717180e+06 -8.52861e-09, -3.19034e-09 +18 1.818190e+06 -8.64316e-09, -3.05596e-09 +19 1.919200e+06 -8.74258e-09, -2.93075e-09 +20 2.020210e+06 -8.82935e-09, -2.81413e-09 +21 2.121220e+06 -8.90545e-09, -2.70547e-09 +22 2.222230e+06 -8.97253e-09, -2.60416e-09 +23 2.323240e+06 -9.03192e-09, -2.50962e-09 +24 2.424250e+06 -9.08473e-09, -2.42130e-09 +25 2.525260e+06 -9.13188e-09, -2.33868e-09 +26 2.626270e+06 -9.17415e-09, -2.26129e-09 +27 2.727280e+06 -9.21217e-09, -2.18871e-09 +28 2.828290e+06 -9.24649e-09, -2.12054e-09 +29 2.929300e+06 -9.27758e-09, -2.05644e-09 +30 3.030310e+06 -9.30583e-09, -1.99607e-09 +31 3.131320e+06 -9.33157e-09, -1.93914e-09 +32 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a/Examples/FrequencyResponse_JFET/plot_data_v.txt b/Examples/FrequencyResponse_JFET/plot_data_v.txt new file mode 100644 index 00000000..7226ed66 --- /dev/null +++ b/Examples/FrequencyResponse_JFET/plot_data_v.txt @@ -0,0 +1,762 @@ +* eeschema netlist version 1.1 (spice format) creation date: thu jun 4 14:46:46 2015 +AC Analysis Mon Jun 22 12:00:29 2015 +-------------------------------------------------------------------------------- +Index frequency V(1) +-------------------------------------------------------------------------------- +0 1.000000e+01 9.971596e-05, -4.47862e-07 +1 1.010200e+05 9.674053e-05, -1.47064e-05 +2 2.020300e+05 9.045983e-05, -2.74464e-05 +3 3.030400e+05 8.167138e-05, -3.70449e-05 +4 4.040500e+05 7.196370e-05, -4.33190e-05 +5 5.050600e+05 6.251400e-05, -4.67582e-05 +6 6.060700e+05 5.396914e-05, -4.80907e-05 +7 7.070800e+05 4.656727e-05, -4.80018e-05 +8 8.080900e+05 4.030672e-05, -4.70259e-05 +9 9.091000e+05 3.507422e-05, -4.55390e-05 +10 1.010110e+06 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2.814668e-06, -7.22892e-06 +99 1.000000e+07 2.799535e-06, -7.17342e-06 + +* eeschema netlist version 1.1 (spice format) creation date: thu jun 4 14:46:46 2015 +AC Analysis Mon Jun 22 12:00:29 2015 +-------------------------------------------------------------------------------- +Index frequency V(2) +-------------------------------------------------------------------------------- +0 1.000000e+01 -2.09971e-06, -5.47954e-05 +1 1.010200e+05 -4.46683e-04, 7.079524e-05 +2 2.020300e+05 -4.15888e-04, 1.337598e-04 +3 3.030400e+05 -3.72793e-04, 1.809161e-04 +4 4.040500e+05 -3.25191e-04, 2.116697e-04 +5 5.050600e+05 -2.78856e-04, 2.284809e-04 +6 6.060700e+05 -2.36958e-04, 2.349407e-04 +7 7.070800e+05 -2.00666e-04, 2.344190e-04 +8 8.080900e+05 -1.69972e-04, 2.295401e-04 +9 9.091000e+05 -1.44321e-04, 2.221512e-04 +10 1.010110e+06 -1.22979e-04, 2.134735e-04 +11 1.111120e+06 -1.05221e-04, 2.042808e-04 +12 1.212130e+06 -9.04022e-05, 1.950450e-04 +13 1.313140e+06 -7.79798e-05, 1.860430e-04 +14 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3.379731e-05 +80 8.080810e+06 9.589429e-06, 3.328728e-05 +81 8.181820e+06 9.631189e-06, 3.278893e-05 +82 8.282830e+06 9.670084e-06, 3.230185e-05 +83 8.383840e+06 9.706244e-06, 3.182565e-05 +84 8.484850e+06 9.739791e-06, 3.135998e-05 +85 8.585860e+06 9.770841e-06, 3.090447e-05 +86 8.686870e+06 9.799502e-06, 3.045881e-05 +87 8.787880e+06 9.825879e-06, 3.002266e-05 +88 8.888890e+06 9.850067e-06, 2.959572e-05 +89 8.989900e+06 9.872161e-06, 2.917770e-05 +90 9.090910e+06 9.892248e-06, 2.876833e-05 +91 9.191920e+06 9.910411e-06, 2.836732e-05 +92 9.292930e+06 9.926728e-06, 2.797444e-05 +93 9.393940e+06 9.941275e-06, 2.758943e-05 +94 9.494950e+06 9.954124e-06, 2.721205e-05 +95 9.595960e+06 9.965341e-06, 2.684209e-05 +96 9.696970e+06 9.974992e-06, 2.647932e-05 +97 9.797980e+06 9.983138e-06, 2.612355e-05 +98 9.898990e+06 9.989838e-06, 2.577456e-05 +99 1.000000e+07 9.995147e-06, 2.543216e-05 + +* eeschema netlist version 1.1 (spice format) creation date: thu jun 4 14:46:46 2015 +AC Analysis Mon Jun 22 12:00:29 2015 +-------------------------------------------------------------------------------- +Index frequency V(3) +-------------------------------------------------------------------------------- +0 1.000000e+01 1.000000e-04, 0.000000e+00 +1 1.010200e+05 1.000000e-04, 0.000000e+00 +2 2.020300e+05 1.000000e-04, 0.000000e+00 +3 3.030400e+05 1.000000e-04, 0.000000e+00 +4 4.040500e+05 1.000000e-04, 0.000000e+00 +5 5.050600e+05 1.000000e-04, 0.000000e+00 +6 6.060700e+05 1.000000e-04, 0.000000e+00 +7 7.070800e+05 1.000000e-04, 0.000000e+00 +8 8.080900e+05 1.000000e-04, 0.000000e+00 +9 9.091000e+05 1.000000e-04, 0.000000e+00 +10 1.010110e+06 1.000000e-04, 0.000000e+00 +11 1.111120e+06 1.000000e-04, 0.000000e+00 +12 1.212130e+06 1.000000e-04, 0.000000e+00 +13 1.313140e+06 1.000000e-04, 0.000000e+00 +14 1.414150e+06 1.000000e-04, 0.000000e+00 +15 1.515160e+06 1.000000e-04, 0.000000e+00 +16 1.616170e+06 1.000000e-04, 0.000000e+00 +17 1.717180e+06 1.000000e-04, 0.000000e+00 +18 1.818190e+06 1.000000e-04, 0.000000e+00 +19 1.919200e+06 1.000000e-04, 0.000000e+00 +20 2.020210e+06 1.000000e-04, 0.000000e+00 +21 2.121220e+06 1.000000e-04, 0.000000e+00 +22 2.222230e+06 1.000000e-04, 0.000000e+00 +23 2.323240e+06 1.000000e-04, 0.000000e+00 +24 2.424250e+06 1.000000e-04, 0.000000e+00 +25 2.525260e+06 1.000000e-04, 0.000000e+00 +26 2.626270e+06 1.000000e-04, 0.000000e+00 +27 2.727280e+06 1.000000e-04, 0.000000e+00 +28 2.828290e+06 1.000000e-04, 0.000000e+00 +29 2.929300e+06 1.000000e-04, 0.000000e+00 +30 3.030310e+06 1.000000e-04, 0.000000e+00 +31 3.131320e+06 1.000000e-04, 0.000000e+00 +32 3.232330e+06 1.000000e-04, 0.000000e+00 +33 3.333340e+06 1.000000e-04, 0.000000e+00 +34 3.434350e+06 1.000000e-04, 0.000000e+00 +35 3.535360e+06 1.000000e-04, 0.000000e+00 +36 3.636370e+06 1.000000e-04, 0.000000e+00 +37 3.737380e+06 1.000000e-04, 0.000000e+00 +38 3.838390e+06 1.000000e-04, 0.000000e+00 +39 3.939400e+06 1.000000e-04, 0.000000e+00 +40 4.040410e+06 1.000000e-04, 0.000000e+00 +41 4.141420e+06 1.000000e-04, 0.000000e+00 +42 4.242430e+06 1.000000e-04, 0.000000e+00 +43 4.343440e+06 1.000000e-04, 0.000000e+00 +44 4.444450e+06 1.000000e-04, 0.000000e+00 +45 4.545460e+06 1.000000e-04, 0.000000e+00 +46 4.646470e+06 1.000000e-04, 0.000000e+00 +47 4.747480e+06 1.000000e-04, 0.000000e+00 +48 4.848490e+06 1.000000e-04, 0.000000e+00 +49 4.949500e+06 1.000000e-04, 0.000000e+00 +50 5.050510e+06 1.000000e-04, 0.000000e+00 +51 5.151520e+06 1.000000e-04, 0.000000e+00 +52 5.252530e+06 1.000000e-04, 0.000000e+00 +53 5.353540e+06 1.000000e-04, 0.000000e+00 +54 5.454550e+06 1.000000e-04, 0.000000e+00 + +Index frequency V(3) +-------------------------------------------------------------------------------- +55 5.555560e+06 1.000000e-04, 0.000000e+00 +56 5.656570e+06 1.000000e-04, 0.000000e+00 +57 5.757580e+06 1.000000e-04, 0.000000e+00 +58 5.858590e+06 1.000000e-04, 0.000000e+00 +59 5.959600e+06 1.000000e-04, 0.000000e+00 +60 6.060610e+06 1.000000e-04, 0.000000e+00 +61 6.161620e+06 1.000000e-04, 0.000000e+00 +62 6.262630e+06 1.000000e-04, 0.000000e+00 +63 6.363640e+06 1.000000e-04, 0.000000e+00 +64 6.464650e+06 1.000000e-04, 0.000000e+00 +65 6.565660e+06 1.000000e-04, 0.000000e+00 +66 6.666670e+06 1.000000e-04, 0.000000e+00 +67 6.767680e+06 1.000000e-04, 0.000000e+00 +68 6.868690e+06 1.000000e-04, 0.000000e+00 +69 6.969700e+06 1.000000e-04, 0.000000e+00 +70 7.070710e+06 1.000000e-04, 0.000000e+00 +71 7.171720e+06 1.000000e-04, 0.000000e+00 +72 7.272730e+06 1.000000e-04, 0.000000e+00 +73 7.373740e+06 1.000000e-04, 0.000000e+00 +74 7.474750e+06 1.000000e-04, 0.000000e+00 +75 7.575760e+06 1.000000e-04, 0.000000e+00 +76 7.676770e+06 1.000000e-04, 0.000000e+00 +77 7.777780e+06 1.000000e-04, 0.000000e+00 +78 7.878790e+06 1.000000e-04, 0.000000e+00 +79 7.979800e+06 1.000000e-04, 0.000000e+00 +80 8.080810e+06 1.000000e-04, 0.000000e+00 +81 8.181820e+06 1.000000e-04, 0.000000e+00 +82 8.282830e+06 1.000000e-04, 0.000000e+00 +83 8.383840e+06 1.000000e-04, 0.000000e+00 +84 8.484850e+06 1.000000e-04, 0.000000e+00 +85 8.585860e+06 1.000000e-04, 0.000000e+00 +86 8.686870e+06 1.000000e-04, 0.000000e+00 +87 8.787880e+06 1.000000e-04, 0.000000e+00 +88 8.888890e+06 1.000000e-04, 0.000000e+00 +89 8.989900e+06 1.000000e-04, 0.000000e+00 +90 9.090910e+06 1.000000e-04, 0.000000e+00 +91 9.191920e+06 1.000000e-04, 0.000000e+00 +92 9.292930e+06 1.000000e-04, 0.000000e+00 +93 9.393940e+06 1.000000e-04, 0.000000e+00 +94 9.494950e+06 1.000000e-04, 0.000000e+00 +95 9.595960e+06 1.000000e-04, 0.000000e+00 +96 9.696970e+06 1.000000e-04, 0.000000e+00 +97 9.797980e+06 1.000000e-04, 0.000000e+00 +98 9.898990e+06 1.000000e-04, 0.000000e+00 +99 1.000000e+07 1.000000e-04, 0.000000e+00 + +* eeschema netlist version 1.1 (spice format) creation date: thu jun 4 14:46:46 2015 +AC Analysis Mon Jun 22 12:00:29 2015 +-------------------------------------------------------------------------------- +Index frequency V(5) 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+72 7.272730e+06 -3.01007e-10, -1.29188e-10 +73 7.373740e+06 -2.93277e-10, -1.26623e-10 +74 7.474750e+06 -2.85854e-10, -1.24152e-10 +75 7.575760e+06 -2.78722e-10, -1.21771e-10 +76 7.676770e+06 -2.71864e-10, -1.19475e-10 +77 7.777780e+06 -2.65268e-10, -1.17259e-10 +78 7.878790e+06 -2.58920e-10, -1.15120e-10 +79 7.979800e+06 -2.52807e-10, -1.13052e-10 +80 8.080810e+06 -2.46919e-10, -1.11054e-10 +81 8.181820e+06 -2.41244e-10, -1.09121e-10 +82 8.282830e+06 -2.35771e-10, -1.07250e-10 +83 8.383840e+06 -2.30493e-10, -1.05438e-10 +84 8.484850e+06 -2.25398e-10, -1.03682e-10 +85 8.585860e+06 -2.20479e-10, -1.01981e-10 +86 8.686870e+06 -2.15728e-10, -1.00330e-10 +87 8.787880e+06 -2.11137e-10, -9.87288e-11 +88 8.888890e+06 -2.06699e-10, -9.71743e-11 +89 8.989900e+06 -2.02407e-10, -9.56645e-11 +90 9.090910e+06 -1.98254e-10, -9.41976e-11 +91 9.191920e+06 -1.94235e-10, -9.27717e-11 +92 9.292930e+06 -1.90345e-10, -9.13851e-11 +93 9.393940e+06 -1.86576e-10, -9.00362e-11 +94 9.494950e+06 -1.82925e-10, -8.87234e-11 +95 9.595960e+06 -1.79387e-10, -8.74453e-11 +96 9.696970e+06 -1.75956e-10, -8.62005e-11 +97 9.797980e+06 -1.72629e-10, -8.49876e-11 +98 9.898990e+06 -1.69400e-10, -8.38056e-11 +99 1.000000e+07 -1.66268e-10, -8.26531e-11 + +* eeschema netlist version 1.1 (spice format) creation date: thu jun 4 14:46:46 2015 +AC Analysis Mon Jun 22 12:00:29 2015 +-------------------------------------------------------------------------------- +Index frequency V(8) +-------------------------------------------------------------------------------- +0 1.000000e+01 2.843657e-05, 4.475814e-05 +1 1.010200e+05 9.650883e-05, -1.46550e-05 +2 2.020300e+05 9.024361e-05, -2.73712e-05 +3 3.030400e+05 8.147682e-05, -3.69486e-05 +4 4.040500e+05 7.179307e-05, -4.32086e-05 +5 5.050600e+05 6.236666e-05, -4.66401e-05 +6 6.060700e+05 5.384286e-05, -4.79698e-05 +7 7.070800e+05 4.645922e-05, -4.78815e-05 +8 8.080900e+05 4.021410e-05, -4.69083e-05 +9 9.091000e+05 3.499450e-05, -4.54254e-05 +10 1.010110e+06 3.065139e-05, -4.36809e-05 +11 1.111120e+06 2.703704e-05, -4.18321e-05 +12 1.212130e+06 2.402036e-05, -3.99749e-05 +13 1.313140e+06 2.149102e-05, -3.81654e-05 +14 1.414150e+06 1.935873e-05, -3.64347e-05 +15 1.515160e+06 1.755058e-05, -3.47981e-05 +16 1.616170e+06 1.600808e-05, -3.32613e-05 +17 1.717180e+06 1.468433e-05, -3.18244e-05 +18 1.818190e+06 1.354170e-05, -3.04839e-05 +19 1.919200e+06 1.254987e-05, -2.92350e-05 +20 2.020210e+06 1.168434e-05, -2.80717e-05 +21 2.121220e+06 1.092515e-05, -2.69879e-05 +22 2.222230e+06 1.025604e-05, -2.59774e-05 +23 2.323240e+06 9.663610e-06, -2.50343e-05 +24 2.424250e+06 9.136802e-06, -2.41533e-05 +25 2.525260e+06 8.666430e-06, -2.33292e-05 +26 2.626270e+06 8.244819e-06, -2.25573e-05 +27 2.727280e+06 7.865530e-06, -2.18333e-05 +28 2.828290e+06 7.523128e-06, -2.11534e-05 +29 2.929300e+06 7.213007e-06, -2.05140e-05 +30 3.030310e+06 6.931246e-06, -1.99118e-05 +31 3.131320e+06 6.674490e-06, -1.93440e-05 +32 3.232330e+06 6.439858e-06, -1.88079e-05 +33 3.333340e+06 6.224866e-06, -1.83011e-05 +34 3.434350e+06 6.027363e-06, -1.78214e-05 +35 3.535360e+06 5.845480e-06, -1.73669e-05 +36 3.636370e+06 5.677588e-06, -1.69357e-05 +37 3.737380e+06 5.522262e-06, -1.65261e-05 +38 3.838390e+06 5.378251e-06, -1.61367e-05 +39 3.939400e+06 5.244453e-06, -1.57661e-05 +40 4.040410e+06 5.119897e-06, -1.54131e-05 +41 4.141420e+06 5.003720e-06, -1.50764e-05 +42 4.242430e+06 4.895158e-06, -1.47551e-05 +43 4.343440e+06 4.793531e-06, -1.44481e-05 +44 4.444450e+06 4.698232e-06, -1.41545e-05 +45 4.545460e+06 4.608716e-06, -1.38736e-05 +46 4.646470e+06 4.524498e-06, -1.36046e-05 +47 4.747480e+06 4.445139e-06, -1.33467e-05 +48 4.848490e+06 4.370245e-06, -1.30994e-05 +49 4.949500e+06 4.299460e-06, -1.28620e-05 +50 5.050510e+06 4.232463e-06, -1.26339e-05 +51 5.151520e+06 4.168962e-06, -1.24147e-05 +52 5.252530e+06 4.108694e-06, -1.22039e-05 +53 5.353540e+06 4.051418e-06, -1.20010e-05 +54 5.454550e+06 3.996916e-06, -1.18055e-05 + +Index frequency V(8) +-------------------------------------------------------------------------------- +55 5.555560e+06 3.944987e-06, -1.16172e-05 +56 5.656570e+06 3.895450e-06, -1.14356e-05 +57 5.757580e+06 3.848137e-06, -1.12605e-05 +58 5.858590e+06 3.802897e-06, -1.10914e-05 +59 5.959600e+06 3.759588e-06, -1.09281e-05 +60 6.060610e+06 3.718083e-06, -1.07703e-05 +61 6.161620e+06 3.678262e-06, -1.06178e-05 +62 6.262630e+06 3.640016e-06, -1.04703e-05 +63 6.363640e+06 3.603246e-06, -1.03275e-05 +64 6.464650e+06 3.567858e-06, -1.01893e-05 +65 6.565660e+06 3.533765e-06, -1.00555e-05 +66 6.666670e+06 3.500889e-06, -9.92578e-06 +67 6.767680e+06 3.469157e-06, -9.80006e-06 +68 6.868690e+06 3.438499e-06, -9.67813e-06 +69 6.969700e+06 3.408852e-06, -9.55985e-06 +70 7.070710e+06 3.380157e-06, -9.44505e-06 +71 7.171720e+06 3.352360e-06, -9.33359e-06 +72 7.272730e+06 3.325410e-06, -9.22534e-06 +73 7.373740e+06 3.299258e-06, -9.12015e-06 +74 7.474750e+06 3.273861e-06, -9.01792e-06 +75 7.575760e+06 3.249178e-06, -8.91851e-06 +76 7.676770e+06 3.225169e-06, -8.82183e-06 +77 7.777780e+06 3.201799e-06, -8.72776e-06 +78 7.878790e+06 3.179033e-06, -8.63620e-06 +79 7.979800e+06 3.156841e-06, -8.54706e-06 +80 8.080810e+06 3.135192e-06, -8.46024e-06 +81 8.181820e+06 3.114058e-06, -8.37566e-06 +82 8.282830e+06 3.093414e-06, -8.29325e-06 +83 8.383840e+06 3.073235e-06, -8.21291e-06 +84 8.484850e+06 3.053499e-06, -8.13457e-06 +85 8.585860e+06 3.034182e-06, -8.05817e-06 +86 8.686870e+06 3.015266e-06, -7.98363e-06 +87 8.787880e+06 2.996731e-06, -7.91088e-06 +88 8.888890e+06 2.978559e-06, -7.83987e-06 +89 8.989900e+06 2.960732e-06, -7.77054e-06 +90 9.090910e+06 2.943236e-06, -7.70283e-06 +91 9.191920e+06 2.926055e-06, -7.63668e-06 +92 9.292930e+06 2.909175e-06, -7.57204e-06 +93 9.393940e+06 2.892582e-06, -7.50887e-06 +94 9.494950e+06 2.876263e-06, -7.44711e-06 +95 9.595960e+06 2.860207e-06, -7.38671e-06 +96 9.696970e+06 2.844403e-06, -7.32764e-06 +97 9.797980e+06 2.828839e-06, -7.26985e-06 +98 9.898990e+06 2.813505e-06, -7.21330e-06 +99 1.000000e+07 2.798393e-06, -7.15795e-06 diff --git a/Examples/Full_Adder/Full_Adder-cache.lib b/Examples/Full_Adder/Full_Adder-cache.lib new file mode 100644 index 00000000..8bbd82d9 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder-cache.lib @@ -0,0 +1,116 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Full_Adder/Full_Adder.bak b/Examples/Full_Adder/Full_Adder.bak new file mode 100644 index 00000000..ee676616 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder.bak @@ -0,0 +1,243 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L full_adder X1 +U 1 1 558AA02B +P 4700 4500 +F 0 "X1" H 6100 5200 60 0000 C CNN +F 1 "full_adder" H 6100 5100 60 0000 C CNN +F 2 "" H 4700 4500 60 0000 C CNN +F 3 "" H 4700 4500 60 0000 C CNN + 1 4700 4500 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U1 +U 1 1 558AA1CF +P 4200 3950 +F 0 "U1" H 4200 3950 60 0000 C CNN +F 1 "adc_bridge_3" H 4200 4100 60 0000 C CNN +F 2 "" H 4200 3950 60 0000 C CNN +F 3 "" H 4200 3950 60 0000 C CNN + 1 4200 3950 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U2 +U 1 1 558AA20A +P 7700 3950 +F 0 "U2" H 7700 3950 60 0000 C CNN +F 1 "dac_bridge_2" H 7750 4100 60 0000 C CNN +F 2 "" H 7700 3950 60 0000 C CNN +F 3 "" H 7700 3950 60 0000 C CNN + 1 7700 3950 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 558AA22C +P 8750 3800 +F 0 "R1" V 8830 3800 50 0000 C CNN +F 1 "1k" V 8750 3800 50 0000 C CNN +F 2 "" V 8680 3800 30 0000 C CNN +F 3 "" H 8750 3800 30 0000 C CNN + 1 8750 3800 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 558AA263 +P 8750 4100 +F 0 "R2" V 8830 4100 50 0000 C CNN +F 1 "1k" V 8750 4100 50 0000 C CNN +F 2 "" V 8680 4100 30 0000 C CNN +F 3 "" H 8750 4100 30 0000 C CNN + 1 8750 4100 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 558AA2B7 +P 9200 4150 +F 0 "#PWR01" H 9200 4150 30 0001 C CNN +F 1 "GND" H 9200 4080 30 0001 C CNN +F 2 "" H 9200 4150 60 0000 C CNN +F 3 "" H 9200 4150 60 0000 C CNN + 1 9200 4150 + 1 0 0 -1 +$EndComp +$Comp +L DC v3 +U 1 1 558AA2E9 +P 2900 3550 +F 0 "v3" H 2700 3650 60 0000 C CNN +F 1 "DC" H 2700 3500 60 0000 C CNN +F 2 "R1" H 2600 3550 60 0000 C CNN +F 3 "" H 2900 3550 60 0000 C CNN + 1 2900 3550 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 558AA31A +P 2700 4000 +F 0 "v1" H 2500 4100 60 0000 C CNN +F 1 "DC" H 2500 3950 60 0000 C CNN +F 2 "R1" H 2400 4000 60 0000 C CNN +F 3 "" H 2700 4000 60 0000 C CNN + 1 2700 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 558AA356 +P 2800 4500 +F 0 "v2" H 2600 4600 60 0000 C CNN +F 1 "DC" H 2600 4450 60 0000 C CNN +F 2 "R1" H 2500 4500 60 0000 C CNN +F 3 "" H 2800 4500 60 0000 C CNN + 1 2800 4500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 558AA3F6 +P 2100 4750 +F 0 "#PWR02" H 2100 4750 30 0001 C CNN +F 1 "GND" H 2100 4680 30 0001 C CNN +F 2 "" H 2100 4750 60 0000 C CNN +F 3 "" H 2100 4750 60 0000 C CNN + 1 2100 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 3550 3350 3900 +Wire Wire Line + 3350 3900 3600 3900 +Wire Wire Line + 3150 4000 3600 4000 +Wire Wire Line + 3600 4100 3400 4100 +Wire Wire Line + 3400 4100 3400 4500 +Wire Wire Line + 3400 4500 3250 4500 +Wire Wire Line + 2450 3550 2100 3550 +Wire Wire Line + 2100 3550 2100 4750 +Wire Wire Line + 2350 4500 2100 4500 +Connection ~ 2100 4500 +Wire Wire Line + 2250 4000 2100 4000 +Connection ~ 2100 4000 +Wire Wire Line + 4750 3900 5000 3900 +Wire Wire Line + 5000 3900 5000 3550 +Wire Wire Line + 5000 3550 5300 3550 +Wire Wire Line + 4750 4000 5150 4000 +Wire Wire Line + 5150 4000 5150 3950 +Wire Wire Line + 5150 3950 5300 3950 +Wire Wire Line + 4750 4100 5300 4100 +Wire Wire Line + 5300 4100 5300 4350 +Wire Wire Line + 6850 3550 6850 3900 +Wire Wire Line + 6850 3900 7250 3900 +Wire Wire Line + 7250 4000 6850 4000 +Wire Wire Line + 6850 4000 6850 4350 +Wire Wire Line + 8250 3900 8400 3900 +Wire Wire Line + 8400 3900 8400 3800 +Wire Wire Line + 8400 3800 8600 3800 +Wire Wire Line + 8250 4000 8400 4000 +Wire Wire Line + 8400 4000 8400 4100 +Wire Wire Line + 8400 4100 8600 4100 +Wire Wire Line + 8900 3800 9200 3800 +Wire Wire Line + 9200 3800 9200 4150 +Wire Wire Line + 8900 4100 9200 4100 +Wire Wire Line + 9200 4100 9200 4050 +Connection ~ 9200 4050 +$Comp +L PWR_FLAG #FLG03 +U 1 1 558AA6B1 +P 9150 3600 +F 0 "#FLG03" H 9150 3695 50 0001 C CNN +F 1 "PWR_FLAG" H 9150 3780 50 0000 C CNN +F 2 "" H 9150 3600 60 0000 C CNN +F 3 "" H 9150 3600 60 0000 C CNN + 1 9150 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9150 3600 9150 3800 +Connection ~ 9150 3800 +$EndSCHEMATC diff --git a/Examples/Full_Adder/Full_Adder.cir b/Examples/Full_Adder/Full_Adder.cir new file mode 100644 index 00000000..f073381c --- /dev/null +++ b/Examples/Full_Adder/Full_Adder.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:29:51 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 4 3 2 1 8 full_adder +U1 10 11 9 4 3 2 adc_bridge_3 +U2 1 8 7 5 dac_bridge_2 +R1 0 7 1k +R2 0 5 1k +v3 10 0 DC +v1 11 0 DC +v2 9 0 DC + +.end diff --git a/Examples/Full_Adder/Full_Adder.cir.out b/Examples/Full_Adder/Full_Adder.cir.out new file mode 100644 index 00000000..803633a9 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder.cir.out @@ -0,0 +1,26 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:29:51 2015 + +.include full_adder.sub +x1 4 3 2 1 8 full_adder +* u1 10 11 9 4 3 2 adc_bridge_3 +* u2 1 8 7 5 dac_bridge_2 +r1 0 7 1k +r2 0 5 1k +v3 10 0 dc 5 +v1 11 0 dc 0 +v2 9 0 dc 5 +a1 [10 11 9 ] [4 3 2 ] u1 +a2 [1 8 ] [7 5 ] u2 +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Full_Adder/Full_Adder.pro b/Examples/Full_Adder/Full_Adder.pro new file mode 100644 index 00000000..c93c55b1 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 12:14:52 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/Examples/Full_Adder/Full_Adder.proj b/Examples/Full_Adder/Full_Adder.proj new file mode 100644 index 00000000..903f1923 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder.proj @@ -0,0 +1 @@ +schematicFile Full_Adder.sch diff --git a/Examples/Full_Adder/Full_Adder.sch b/Examples/Full_Adder/Full_Adder.sch new file mode 100644 index 00000000..ee676616 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder.sch @@ -0,0 +1,243 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L full_adder X1 +U 1 1 558AA02B +P 4700 4500 +F 0 "X1" H 6100 5200 60 0000 C CNN +F 1 "full_adder" H 6100 5100 60 0000 C CNN +F 2 "" H 4700 4500 60 0000 C CNN +F 3 "" H 4700 4500 60 0000 C CNN + 1 4700 4500 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U1 +U 1 1 558AA1CF +P 4200 3950 +F 0 "U1" H 4200 3950 60 0000 C CNN +F 1 "adc_bridge_3" H 4200 4100 60 0000 C CNN +F 2 "" H 4200 3950 60 0000 C CNN +F 3 "" H 4200 3950 60 0000 C CNN + 1 4200 3950 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U2 +U 1 1 558AA20A +P 7700 3950 +F 0 "U2" H 7700 3950 60 0000 C CNN +F 1 "dac_bridge_2" H 7750 4100 60 0000 C CNN +F 2 "" H 7700 3950 60 0000 C CNN +F 3 "" H 7700 3950 60 0000 C CNN + 1 7700 3950 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 558AA22C +P 8750 3800 +F 0 "R1" V 8830 3800 50 0000 C CNN +F 1 "1k" V 8750 3800 50 0000 C CNN +F 2 "" V 8680 3800 30 0000 C CNN +F 3 "" H 8750 3800 30 0000 C CNN + 1 8750 3800 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 558AA263 +P 8750 4100 +F 0 "R2" V 8830 4100 50 0000 C CNN +F 1 "1k" V 8750 4100 50 0000 C CNN +F 2 "" V 8680 4100 30 0000 C CNN +F 3 "" H 8750 4100 30 0000 C CNN + 1 8750 4100 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 558AA2B7 +P 9200 4150 +F 0 "#PWR01" H 9200 4150 30 0001 C CNN +F 1 "GND" H 9200 4080 30 0001 C CNN +F 2 "" H 9200 4150 60 0000 C CNN +F 3 "" H 9200 4150 60 0000 C CNN + 1 9200 4150 + 1 0 0 -1 +$EndComp +$Comp +L DC v3 +U 1 1 558AA2E9 +P 2900 3550 +F 0 "v3" H 2700 3650 60 0000 C CNN +F 1 "DC" H 2700 3500 60 0000 C CNN +F 2 "R1" H 2600 3550 60 0000 C CNN +F 3 "" H 2900 3550 60 0000 C CNN + 1 2900 3550 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 558AA31A +P 2700 4000 +F 0 "v1" H 2500 4100 60 0000 C CNN +F 1 "DC" H 2500 3950 60 0000 C CNN +F 2 "R1" H 2400 4000 60 0000 C CNN +F 3 "" H 2700 4000 60 0000 C CNN + 1 2700 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 558AA356 +P 2800 4500 +F 0 "v2" H 2600 4600 60 0000 C CNN +F 1 "DC" H 2600 4450 60 0000 C CNN +F 2 "R1" H 2500 4500 60 0000 C CNN +F 3 "" H 2800 4500 60 0000 C CNN + 1 2800 4500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 558AA3F6 +P 2100 4750 +F 0 "#PWR02" H 2100 4750 30 0001 C CNN +F 1 "GND" H 2100 4680 30 0001 C CNN +F 2 "" H 2100 4750 60 0000 C CNN +F 3 "" H 2100 4750 60 0000 C CNN + 1 2100 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 3550 3350 3900 +Wire Wire Line + 3350 3900 3600 3900 +Wire Wire Line + 3150 4000 3600 4000 +Wire Wire Line + 3600 4100 3400 4100 +Wire Wire Line + 3400 4100 3400 4500 +Wire Wire Line + 3400 4500 3250 4500 +Wire Wire Line + 2450 3550 2100 3550 +Wire Wire Line + 2100 3550 2100 4750 +Wire Wire Line + 2350 4500 2100 4500 +Connection ~ 2100 4500 +Wire Wire Line + 2250 4000 2100 4000 +Connection ~ 2100 4000 +Wire Wire Line + 4750 3900 5000 3900 +Wire Wire Line + 5000 3900 5000 3550 +Wire Wire Line + 5000 3550 5300 3550 +Wire Wire Line + 4750 4000 5150 4000 +Wire Wire Line + 5150 4000 5150 3950 +Wire Wire Line + 5150 3950 5300 3950 +Wire Wire Line + 4750 4100 5300 4100 +Wire Wire Line + 5300 4100 5300 4350 +Wire Wire Line + 6850 3550 6850 3900 +Wire Wire Line + 6850 3900 7250 3900 +Wire Wire Line + 7250 4000 6850 4000 +Wire Wire Line + 6850 4000 6850 4350 +Wire Wire Line + 8250 3900 8400 3900 +Wire Wire Line + 8400 3900 8400 3800 +Wire Wire Line + 8400 3800 8600 3800 +Wire Wire Line + 8250 4000 8400 4000 +Wire Wire Line + 8400 4000 8400 4100 +Wire Wire Line + 8400 4100 8600 4100 +Wire Wire Line + 8900 3800 9200 3800 +Wire Wire Line + 9200 3800 9200 4150 +Wire Wire Line + 8900 4100 9200 4100 +Wire Wire Line + 9200 4100 9200 4050 +Connection ~ 9200 4050 +$Comp +L PWR_FLAG #FLG03 +U 1 1 558AA6B1 +P 9150 3600 +F 0 "#FLG03" H 9150 3695 50 0001 C CNN +F 1 "PWR_FLAG" H 9150 3780 50 0000 C CNN +F 2 "" H 9150 3600 60 0000 C CNN +F 3 "" H 9150 3600 60 0000 C CNN + 1 9150 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9150 3600 9150 3800 +Connection ~ 9150 3800 +$EndSCHEMATC diff --git a/Examples/Full_Adder/Full_Adder_Previous_Values.xml b/Examples/Full_Adder/Full_Adder_Previous_Values.xml new file mode 100644 index 00000000..5e07a756 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source><v3 name="Source type">dc<field1 name="Value">5</field1></v3><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">5</field1></v2></source><model><u1 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u1><u2 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Full_Adder/analysis b/Examples/Full_Adder/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Full_Adder/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Full_Adder/full_adder-cache.lib b/Examples/Full_Adder/full_adder-cache.lib new file mode 100644 index 00000000..623a7f41 --- /dev/null +++ b/Examples/Full_Adder/full_adder-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Full_Adder/full_adder.cir b/Examples/Full_Adder/full_adder.cir new file mode 100644 index 00000000..6461b5b6 --- /dev/null +++ b/Examples/Full_Adder/full_adder.cir @@ -0,0 +1,12 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 8 7 6 2 half_adder +X2 5 6 4 3 half_adder +U1 8 7 5 4 1 PORT +U2 3 2 1 d_or + +.end diff --git a/Examples/Full_Adder/full_adder.cir.out b/Examples/Full_Adder/full_adder.cir.out new file mode 100644 index 00000000..b90ce70d --- /dev/null +++ b/Examples/Full_Adder/full_adder.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 + +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u1 8 7 5 4 1 port +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Full_Adder/full_adder.pro b/Examples/Full_Adder/full_adder.pro new file mode 100644 index 00000000..c0db0775 --- /dev/null +++ b/Examples/Full_Adder/full_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 12:19:16 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/Examples/Full_Adder/full_adder.sch b/Examples/Full_Adder/full_adder.sch new file mode 100644 index 00000000..8bd400f2 --- /dev/null +++ b/Examples/Full_Adder/full_adder.sch @@ -0,0 +1,180 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L half_adder X1 +U 1 1 558AA064 +P 3800 3350 +F 0 "X1" H 4700 3850 60 0000 C CNN +F 1 "half_adder" H 4700 3750 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L half_adder X2 +U 1 1 558AA0C1 +P 5700 3350 +F 0 "X2" H 6600 3850 60 0000 C CNN +F 1 "half_adder" H 6600 3750 60 0000 C CNN +F 2 "" H 5700 3350 60 0000 C CNN +F 3 "" H 5700 3350 60 0000 C CNN + 1 5700 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558AA277 +P 3450 2650 +F 0 "U1" H 3500 2750 30 0000 C CNN +F 1 "PORT" H 3450 2650 30 0000 C CNN +F 2 "" H 3450 2650 60 0000 C CNN +F 3 "" H 3450 2650 60 0000 C CNN + 1 3450 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558AA29E +P 3450 3250 +F 0 "U1" H 3500 3350 30 0000 C CNN +F 1 "PORT" H 3450 3250 30 0000 C CNN +F 2 "" H 3450 3250 60 0000 C CNN +F 3 "" H 3450 3250 60 0000 C CNN + 2 3450 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558AA2D8 +P 5650 2300 +F 0 "U1" H 5700 2400 30 0000 C CNN +F 1 "PORT" H 5650 2300 30 0000 C CNN +F 2 "" H 5650 2300 60 0000 C CNN +F 3 "" H 5650 2300 60 0000 C CNN + 3 5650 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 558AA378 +P 7900 2650 +F 0 "U1" H 7950 2750 30 0000 C CNN +F 1 "PORT" H 7900 2650 30 0000 C CNN +F 2 "" H 7900 2650 60 0000 C CNN +F 3 "" H 7900 2650 60 0000 C CNN + 4 7900 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 558AA3E0 +P 8700 3400 +F 0 "U1" H 8750 3500 30 0000 C CNN +F 1 "PORT" H 8700 3400 30 0000 C CNN +F 2 "" H 8700 3400 60 0000 C CNN +F 3 "" H 8700 3400 60 0000 C CNN + 5 8700 3400 + -1 0 0 1 +$EndComp +$Comp +L d_or U2 +U 1 1 558AA43B +P 7900 3450 +F 0 "U2" H 7900 3450 60 0000 C CNN +F 1 "d_or" H 7900 3550 60 0000 C CNN +F 2 "" H 7900 3450 60 0000 C CNN +F 3 "" H 7900 3450 60 0000 C CNN + 1 7900 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3700 2650 4100 2650 +Wire Wire Line + 3700 3250 4100 3250 +Wire Wire Line + 5250 2650 5650 2650 +Wire Wire Line + 5650 2650 5650 3250 +Wire Wire Line + 5650 3250 6000 3250 +Wire Wire Line + 5900 2300 5900 2650 +Wire Wire Line + 5900 2650 6000 2650 +Wire Wire Line + 7150 2650 7650 2650 +Wire Wire Line + 7150 3250 7350 3250 +Wire Wire Line + 7350 3250 7350 3350 +Wire Wire Line + 7350 3350 7450 3350 +Wire Wire Line + 5250 3250 5400 3250 +Wire Wire Line + 5400 3250 5400 3450 +Wire Wire Line + 5400 3450 7450 3450 +Wire Wire Line + 8350 3400 8450 3400 +Text Notes 3850 2500 0 60 ~ 0 +IN1 +Text Notes 3850 3150 0 60 ~ 0 +IN2 +Text Notes 6000 2350 0 60 ~ 0 +CIN +Text Notes 7350 2550 0 60 ~ 0 +SUM +Text Notes 8300 3200 0 60 ~ 0 +COUT +$EndSCHEMATC diff --git a/Examples/Full_Adder/full_adder.sub b/Examples/Full_Adder/full_adder.sub new file mode 100644 index 00000000..5f261f78 --- /dev/null +++ b/Examples/Full_Adder/full_adder.sub @@ -0,0 +1,13 @@ +* Subcircuit full_adder +.subckt full_adder 8 7 5 4 1 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_adder
\ No newline at end of file diff --git a/Examples/Full_Adder/full_adder_Previous_Values.xml b/Examples/Full_Adder/full_adder_Previous_Values.xml new file mode 100644 index 00000000..b63184d6 --- /dev/null +++ b/Examples/Full_Adder/full_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Full_Adder/half_adder-cache.lib b/Examples/Full_Adder/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/Examples/Full_Adder/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Full_Adder/half_adder.cir b/Examples/Full_Adder/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/Examples/Full_Adder/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/Examples/Full_Adder/half_adder.cir.out b/Examples/Full_Adder/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/Examples/Full_Adder/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Full_Adder/half_adder.pro b/Examples/Full_Adder/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/Examples/Full_Adder/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/Examples/Full_Adder/half_adder.sch b/Examples/Full_Adder/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/Examples/Full_Adder/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/Examples/Full_Adder/half_adder.sub b/Examples/Full_Adder/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/Examples/Full_Adder/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/Examples/Full_Adder/half_adder_Previous_Values.xml b/Examples/Full_Adder/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/Examples/Full_Adder/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Full_Adder/plot_data_i.txt b/Examples/Full_Adder/plot_data_i.txt new file mode 100644 index 00000000..0b3114d8 --- /dev/null +++ b/Examples/Full_Adder/plot_data_i.txt @@ -0,0 +1,135 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:29:51 2015 +Transient Analysis Tue Jun 30 14:47:07 2015 +-------------------------------------------------------------------------------- +Index time a2#branch_1_0 a2#branch_1_1 v1#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 -5.00000e-03 0.000000e+00 +1 1.000000e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +2 2.000000e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +3 4.000000e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +4 8.000000e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +5 1.600000e-04 0.000000e+00 -5.00000e-03 0.000000e+00 +6 3.200000e-04 0.000000e+00 -5.00000e-03 0.000000e+00 +7 6.400000e-04 0.000000e+00 -5.00000e-03 0.000000e+00 +8 1.280000e-03 0.000000e+00 -5.00000e-03 0.000000e+00 +9 2.560000e-03 0.000000e+00 -5.00000e-03 0.000000e+00 +10 4.560000e-03 0.000000e+00 -5.00000e-03 0.000000e+00 +11 6.560000e-03 0.000000e+00 -5.00000e-03 0.000000e+00 +12 8.560000e-03 0.000000e+00 -5.00000e-03 0.000000e+00 +13 1.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +14 1.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +15 1.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +16 1.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +17 1.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +18 2.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +19 2.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +20 2.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +21 2.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +22 2.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +23 3.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +24 3.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +25 3.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +26 3.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +27 3.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +28 4.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +29 4.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +30 4.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +31 4.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +32 4.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +33 5.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +34 5.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +35 5.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +36 5.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +37 5.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +38 6.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +39 6.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +40 6.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +41 6.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +42 6.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +43 7.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +44 7.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +45 7.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +46 7.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +47 7.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +48 8.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +49 8.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +50 8.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +51 8.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +52 8.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +53 9.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +54 9.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 + +Index time a2#branch_1_0 a2#branch_1_1 v1#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +56 9.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +57 9.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +58 1.000000e-01 0.000000e+00 -5.00000e-03 0.000000e+00 + +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:29:51 2015 +Transient Analysis Tue Jun 30 14:47:07 2015 +-------------------------------------------------------------------------------- +Index time v2#branch v3#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-05 0.000000e+00 0.000000e+00 +2 2.000000e-05 0.000000e+00 0.000000e+00 +3 4.000000e-05 0.000000e+00 0.000000e+00 +4 8.000000e-05 0.000000e+00 0.000000e+00 +5 1.600000e-04 0.000000e+00 0.000000e+00 +6 3.200000e-04 0.000000e+00 0.000000e+00 +7 6.400000e-04 0.000000e+00 0.000000e+00 +8 1.280000e-03 0.000000e+00 0.000000e+00 +9 2.560000e-03 0.000000e+00 0.000000e+00 +10 4.560000e-03 0.000000e+00 0.000000e+00 +11 6.560000e-03 0.000000e+00 0.000000e+00 +12 8.560000e-03 0.000000e+00 0.000000e+00 +13 1.056000e-02 0.000000e+00 0.000000e+00 +14 1.256000e-02 0.000000e+00 0.000000e+00 +15 1.456000e-02 0.000000e+00 0.000000e+00 +16 1.656000e-02 0.000000e+00 0.000000e+00 +17 1.856000e-02 0.000000e+00 0.000000e+00 +18 2.056000e-02 0.000000e+00 0.000000e+00 +19 2.256000e-02 0.000000e+00 0.000000e+00 +20 2.456000e-02 0.000000e+00 0.000000e+00 +21 2.656000e-02 0.000000e+00 0.000000e+00 +22 2.856000e-02 0.000000e+00 0.000000e+00 +23 3.056000e-02 0.000000e+00 0.000000e+00 +24 3.256000e-02 0.000000e+00 0.000000e+00 +25 3.456000e-02 0.000000e+00 0.000000e+00 +26 3.656000e-02 0.000000e+00 0.000000e+00 +27 3.856000e-02 0.000000e+00 0.000000e+00 +28 4.056000e-02 0.000000e+00 0.000000e+00 +29 4.256000e-02 0.000000e+00 0.000000e+00 +30 4.456000e-02 0.000000e+00 0.000000e+00 +31 4.656000e-02 0.000000e+00 0.000000e+00 +32 4.856000e-02 0.000000e+00 0.000000e+00 +33 5.056000e-02 0.000000e+00 0.000000e+00 +34 5.256000e-02 0.000000e+00 0.000000e+00 +35 5.456000e-02 0.000000e+00 0.000000e+00 +36 5.656000e-02 0.000000e+00 0.000000e+00 +37 5.856000e-02 0.000000e+00 0.000000e+00 +38 6.056000e-02 0.000000e+00 0.000000e+00 +39 6.256000e-02 0.000000e+00 0.000000e+00 +40 6.456000e-02 0.000000e+00 0.000000e+00 +41 6.656000e-02 0.000000e+00 0.000000e+00 +42 6.856000e-02 0.000000e+00 0.000000e+00 +43 7.056000e-02 0.000000e+00 0.000000e+00 +44 7.256000e-02 0.000000e+00 0.000000e+00 +45 7.456000e-02 0.000000e+00 0.000000e+00 +46 7.656000e-02 0.000000e+00 0.000000e+00 +47 7.856000e-02 0.000000e+00 0.000000e+00 +48 8.056000e-02 0.000000e+00 0.000000e+00 +49 8.256000e-02 0.000000e+00 0.000000e+00 +50 8.456000e-02 0.000000e+00 0.000000e+00 +51 8.656000e-02 0.000000e+00 0.000000e+00 +52 8.856000e-02 0.000000e+00 0.000000e+00 +53 9.056000e-02 0.000000e+00 0.000000e+00 +54 9.256000e-02 0.000000e+00 0.000000e+00 + +Index time v2#branch v3#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 0.000000e+00 0.000000e+00 +56 9.656000e-02 0.000000e+00 0.000000e+00 +57 9.856000e-02 0.000000e+00 0.000000e+00 +58 1.000000e-01 0.000000e+00 0.000000e+00 diff --git a/Examples/Full_Adder/plot_data_v.txt b/Examples/Full_Adder/plot_data_v.txt new file mode 100644 index 00000000..6cc6c40a --- /dev/null +++ b/Examples/Full_Adder/plot_data_v.txt @@ -0,0 +1,135 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:29:51 2015 +Transient Analysis Tue Jun 30 14:47:07 2015 +-------------------------------------------------------------------------------- +Index time V(5) V(7) V(9) +-------------------------------------------------------------------------------- +0 0.000000e+00 5.000000e+00 0.000000e+00 5.000000e+00 +1 1.000000e-05 5.000000e+00 0.000000e+00 5.000000e+00 +2 2.000000e-05 5.000000e+00 0.000000e+00 5.000000e+00 +3 4.000000e-05 5.000000e+00 0.000000e+00 5.000000e+00 +4 8.000000e-05 5.000000e+00 0.000000e+00 5.000000e+00 +5 1.600000e-04 5.000000e+00 0.000000e+00 5.000000e+00 +6 3.200000e-04 5.000000e+00 0.000000e+00 5.000000e+00 +7 6.400000e-04 5.000000e+00 0.000000e+00 5.000000e+00 +8 1.280000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +9 2.560000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +10 4.560000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +11 6.560000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +12 8.560000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +13 1.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +14 1.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +15 1.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +16 1.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +17 1.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +18 2.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +19 2.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +20 2.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +21 2.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +22 2.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +23 3.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +24 3.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +25 3.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +26 3.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +27 3.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +28 4.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +29 4.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +30 4.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +31 4.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +32 4.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +33 5.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +34 5.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +35 5.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +36 5.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +37 5.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +38 6.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +39 6.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +40 6.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +41 6.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +42 6.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +43 7.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +44 7.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +45 7.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +46 7.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +47 7.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +48 8.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +49 8.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +50 8.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +51 8.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +52 8.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +53 9.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +54 9.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 + +Index time V(5) V(7) V(9) +-------------------------------------------------------------------------------- +55 9.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +56 9.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +57 9.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +58 1.000000e-01 5.000000e+00 0.000000e+00 5.000000e+00 + +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:29:51 2015 +Transient Analysis Tue Jun 30 14:47:07 2015 +-------------------------------------------------------------------------------- +Index time V(10) V(11) +-------------------------------------------------------------------------------- +0 0.000000e+00 5.000000e+00 0.000000e+00 +1 1.000000e-05 5.000000e+00 0.000000e+00 +2 2.000000e-05 5.000000e+00 0.000000e+00 +3 4.000000e-05 5.000000e+00 0.000000e+00 +4 8.000000e-05 5.000000e+00 0.000000e+00 +5 1.600000e-04 5.000000e+00 0.000000e+00 +6 3.200000e-04 5.000000e+00 0.000000e+00 +7 6.400000e-04 5.000000e+00 0.000000e+00 +8 1.280000e-03 5.000000e+00 0.000000e+00 +9 2.560000e-03 5.000000e+00 0.000000e+00 +10 4.560000e-03 5.000000e+00 0.000000e+00 +11 6.560000e-03 5.000000e+00 0.000000e+00 +12 8.560000e-03 5.000000e+00 0.000000e+00 +13 1.056000e-02 5.000000e+00 0.000000e+00 +14 1.256000e-02 5.000000e+00 0.000000e+00 +15 1.456000e-02 5.000000e+00 0.000000e+00 +16 1.656000e-02 5.000000e+00 0.000000e+00 +17 1.856000e-02 5.000000e+00 0.000000e+00 +18 2.056000e-02 5.000000e+00 0.000000e+00 +19 2.256000e-02 5.000000e+00 0.000000e+00 +20 2.456000e-02 5.000000e+00 0.000000e+00 +21 2.656000e-02 5.000000e+00 0.000000e+00 +22 2.856000e-02 5.000000e+00 0.000000e+00 +23 3.056000e-02 5.000000e+00 0.000000e+00 +24 3.256000e-02 5.000000e+00 0.000000e+00 +25 3.456000e-02 5.000000e+00 0.000000e+00 +26 3.656000e-02 5.000000e+00 0.000000e+00 +27 3.856000e-02 5.000000e+00 0.000000e+00 +28 4.056000e-02 5.000000e+00 0.000000e+00 +29 4.256000e-02 5.000000e+00 0.000000e+00 +30 4.456000e-02 5.000000e+00 0.000000e+00 +31 4.656000e-02 5.000000e+00 0.000000e+00 +32 4.856000e-02 5.000000e+00 0.000000e+00 +33 5.056000e-02 5.000000e+00 0.000000e+00 +34 5.256000e-02 5.000000e+00 0.000000e+00 +35 5.456000e-02 5.000000e+00 0.000000e+00 +36 5.656000e-02 5.000000e+00 0.000000e+00 +37 5.856000e-02 5.000000e+00 0.000000e+00 +38 6.056000e-02 5.000000e+00 0.000000e+00 +39 6.256000e-02 5.000000e+00 0.000000e+00 +40 6.456000e-02 5.000000e+00 0.000000e+00 +41 6.656000e-02 5.000000e+00 0.000000e+00 +42 6.856000e-02 5.000000e+00 0.000000e+00 +43 7.056000e-02 5.000000e+00 0.000000e+00 +44 7.256000e-02 5.000000e+00 0.000000e+00 +45 7.456000e-02 5.000000e+00 0.000000e+00 +46 7.656000e-02 5.000000e+00 0.000000e+00 +47 7.856000e-02 5.000000e+00 0.000000e+00 +48 8.056000e-02 5.000000e+00 0.000000e+00 +49 8.256000e-02 5.000000e+00 0.000000e+00 +50 8.456000e-02 5.000000e+00 0.000000e+00 +51 8.656000e-02 5.000000e+00 0.000000e+00 +52 8.856000e-02 5.000000e+00 0.000000e+00 +53 9.056000e-02 5.000000e+00 0.000000e+00 +54 9.256000e-02 5.000000e+00 0.000000e+00 + +Index time V(10) V(11) +-------------------------------------------------------------------------------- +55 9.456000e-02 5.000000e+00 0.000000e+00 +56 9.656000e-02 5.000000e+00 0.000000e+00 +57 9.856000e-02 5.000000e+00 0.000000e+00 +58 1.000000e-01 5.000000e+00 0.000000e+00 diff --git a/Examples/Half_Adder/Half_Adder-cache.lib b/Examples/Half_Adder/Half_Adder-cache.lib new file mode 100644 index 00000000..7b3ea0a8 --- /dev/null +++ b/Examples/Half_Adder/Half_Adder-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_2 +# +DEF adc_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_2" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -100 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT2 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Half_Adder/Half_Adder-rescue.lib b/Examples/Half_Adder/Half_Adder-rescue.lib new file mode 100644 index 00000000..71251f6c --- /dev/null +++ b/Examples/Half_Adder/Half_Adder-rescue.lib @@ -0,0 +1,17 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND-RESCUE-Half_Adder +# +DEF ~GND-RESCUE-Half_Adder #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND-RESCUE-Half_Adder" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Half_Adder/Half_Adder.bak b/Examples/Half_Adder/Half_Adder.bak new file mode 100644 index 00000000..dcfb27c4 --- /dev/null +++ b/Examples/Half_Adder/Half_Adder.bak @@ -0,0 +1,277 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L half_adder X1 +U 1 1 558A91C8 +P 5000 3900 +F 0 "X1" H 5900 4400 60 0000 C CNN +F 1 "half_adder" H 5900 4300 60 0000 C CNN +F 2 "" H 5000 3900 60 0000 C CNN +F 3 "" H 5000 3900 60 0000 C CNN + 1 5000 3900 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_2 U1 +U 1 1 558A92C9 +P 4550 3500 +F 0 "U1" H 4550 3500 60 0000 C CNN +F 1 "adc_bridge_2" H 4550 3650 60 0000 C CNN +F 2 "" H 4550 3500 60 0000 C CNN +F 3 "" H 4550 3500 60 0000 C CNN + 1 4550 3500 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U2 +U 1 1 558A9300 +P 6950 3450 +F 0 "U2" H 6950 3450 60 0000 C CNN +F 1 "dac_bridge_2" H 7000 3600 60 0000 C CNN +F 2 "" H 6950 3450 60 0000 C CNN +F 3 "" H 6950 3450 60 0000 C CNN + 1 6950 3450 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 558A9345 +P 3450 3150 +F 0 "v1" H 3250 3250 60 0000 C CNN +F 1 "DC" H 3250 3100 60 0000 C CNN +F 2 "R1" H 3150 3150 60 0000 C CNN +F 3 "" H 3450 3150 60 0000 C CNN + 1 3450 3150 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 558A937C +P 3450 3800 +F 0 "v2" H 3250 3900 60 0000 C CNN +F 1 "DC" H 3250 3750 60 0000 C CNN +F 2 "R1" H 3150 3800 60 0000 C CNN +F 3 "" H 3450 3800 60 0000 C CNN + 1 3450 3800 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 558A93BB +P 2950 4000 +F 0 "#PWR01" H 2950 4000 30 0001 C CNN +F 1 "GND" H 2950 3930 30 0001 C CNN +F 2 "" H 2950 4000 60 0000 C CNN +F 3 "" H 2950 4000 60 0000 C CNN + 1 2950 4000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 558A93D7 +P 2950 3250 +F 0 "#PWR02" H 2950 3250 30 0001 C CNN +F 1 "GND" H 2950 3180 30 0001 C CNN +F 2 "" H 2950 3250 60 0000 C CNN +F 3 "" H 2950 3250 60 0000 C CNN + 1 2950 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 558A940C +P 7850 3300 +F 0 "R1" V 7930 3300 50 0000 C CNN +F 1 "1k" V 7850 3300 50 0000 C CNN +F 2 "" V 7780 3300 30 0000 C CNN +F 3 "" H 7850 3300 30 0000 C CNN + 1 7850 3300 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 558A945B +P 7850 3550 +F 0 "R2" V 7930 3550 50 0000 C CNN +F 1 "1k" V 7850 3550 50 0000 C CNN +F 2 "" V 7780 3550 30 0000 C CNN +F 3 "" H 7850 3550 30 0000 C CNN + 1 7850 3550 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 558A9480 +P 8350 3650 +F 0 "#PWR03" H 8350 3650 30 0001 C CNN +F 1 "GND" H 8350 3580 30 0001 C CNN +F 2 "" H 8350 3650 60 0000 C CNN +F 3 "" H 8350 3650 60 0000 C CNN + 1 8350 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 3150 2950 3150 +Wire Wire Line + 2950 3150 2950 3250 +Wire Wire Line + 3000 3800 2950 3800 +Wire Wire Line + 2950 3800 2950 4000 +Wire Wire Line + 3900 3800 3950 3800 +Wire Wire Line + 3950 3800 3950 3550 +Wire Wire Line + 3950 3450 3950 3150 +Wire Wire Line + 3950 3150 3900 3150 +Wire Wire Line + 5100 3450 5300 3450 +Wire Wire Line + 5300 3450 5300 3200 +Wire Wire Line + 5100 3550 5300 3550 +Wire Wire Line + 5300 3550 5300 3800 +Wire Wire Line + 6450 3200 6450 3400 +Wire Wire Line + 6450 3400 6500 3400 +Wire Wire Line + 6500 3500 6450 3500 +Wire Wire Line + 6450 3500 6450 3800 +Wire Wire Line + 7500 3400 7600 3400 +Wire Wire Line + 7600 3400 7600 3300 +Wire Wire Line + 7600 3300 7700 3300 +Wire Wire Line + 7500 3500 7600 3500 +Wire Wire Line + 7600 3500 7600 3550 +Wire Wire Line + 7600 3550 7700 3550 +Wire Wire Line + 8000 3300 8350 3300 +Wire Wire Line + 8350 3300 8350 3650 +Wire Wire Line + 8000 3550 8350 3550 +Wire Wire Line + 8350 3550 8350 3500 +Connection ~ 8350 3500 +$Comp +L PWR_FLAG #FLG04 +U 1 1 558A96D4 +P 2850 3850 +F 0 "#FLG04" H 2850 3945 50 0001 C CNN +F 1 "PWR_FLAG" H 2850 4030 50 0000 C CNN +F 2 "" H 2850 3850 60 0000 C CNN +F 3 "" H 2850 3850 60 0000 C CNN + 1 2850 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2850 3850 2850 3900 +Wire Wire Line + 2850 3900 2950 3900 +Connection ~ 2950 3900 +Text GLabel 7600 3150 0 60 Input ~ 0 +sum +Text GLabel 7600 3750 0 60 Input ~ 0 +cout +Text GLabel 4050 3150 2 60 Input ~ 0 +A +Text GLabel 4100 3750 2 60 Input ~ 0 +B +Text GLabel 5200 3250 0 60 Input ~ 0 +1 +Text GLabel 5200 3700 0 60 Input ~ 0 +2 +Text GLabel 6550 3250 2 60 Input ~ 0 +3 +Text GLabel 6550 3650 2 60 Input ~ 0 +4 +Wire Wire Line + 4050 3150 4050 3250 +Wire Wire Line + 4050 3250 3950 3250 +Connection ~ 3950 3250 +Wire Wire Line + 4100 3750 3950 3750 +Connection ~ 3950 3750 +Wire Wire Line + 5200 3700 5300 3700 +Connection ~ 5300 3700 +Wire Wire Line + 5200 3250 5250 3250 +Wire Wire Line + 5250 3250 5250 3450 +Connection ~ 5250 3450 +Wire Wire Line + 6550 3250 6450 3250 +Connection ~ 6450 3250 +Wire Wire Line + 6550 3650 6450 3650 +Connection ~ 6450 3650 +Wire Wire Line + 7600 3750 7650 3750 +Wire Wire Line + 7650 3750 7650 3550 +Connection ~ 7650 3550 +Wire Wire Line + 7600 3150 7600 3350 +Connection ~ 7600 3350 +$EndSCHEMATC diff --git a/Examples/Half_Adder/Half_Adder.cir b/Examples/Half_Adder/Half_Adder.cir new file mode 100644 index 00000000..750f7d56 --- /dev/null +++ b/Examples/Half_Adder/Half_Adder.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 15:44:17 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 1 2 3 4 half_adder +U1 A B 1 2 adc_bridge_2 +U2 3 4 sum cout dac_bridge_2 +v1 A GND DC +v2 B GND DC +R1 GND sum 1k +R2 GND cout 1k + +.end diff --git a/Examples/Half_Adder/Half_Adder.cir.out b/Examples/Half_Adder/Half_Adder.cir.out new file mode 100644 index 00000000..5d7165f1 --- /dev/null +++ b/Examples/Half_Adder/Half_Adder.cir.out @@ -0,0 +1,25 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 15:44:17 2015 + +.include half_adder.sub +x1 1 2 3 4 half_adder +* u1 a b 1 2 adc_bridge_2 +* u2 3 4 sum cout dac_bridge_2 +v1 a gnd dc 5 +v2 b gnd dc 0 +r1 gnd sum 1k +r2 gnd cout 1k +a1 [a b ] [1 2 ] u1 +a2 [3 4 ] [sum cout ] u2 +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Half_Adder/Half_Adder.pro b/Examples/Half_Adder/Half_Adder.pro new file mode 100644 index 00000000..7d91e5b9 --- /dev/null +++ b/Examples/Half_Adder/Half_Adder.pro @@ -0,0 +1,70 @@ +update=Wed Jul 1 11:26:18 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=Half_Adder-rescue +LibName2=power +LibName3=device +LibName4=transistors +LibName5=conn +LibName6=linear +LibName7=regul +LibName8=74xx +LibName9=cmos4000 +LibName10=adc-dac +LibName11=memory +LibName12=xilinx +LibName13=special +LibName14=microcontrollers +LibName15=dsp +LibName16=microchip +LibName17=analog_switches +LibName18=motorola +LibName19=texas +LibName20=intel +LibName21=audio +LibName22=interface +LibName23=digital-audio +LibName24=philips +LibName25=display +LibName26=cypress +LibName27=siliconi +LibName28=opto +LibName29=atmel +LibName30=contrib +LibName31=valves +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName37=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/Examples/Half_Adder/Half_Adder.proj b/Examples/Half_Adder/Half_Adder.proj new file mode 100644 index 00000000..cc4f1c32 --- /dev/null +++ b/Examples/Half_Adder/Half_Adder.proj @@ -0,0 +1 @@ +schematicFile Half_Adder.sch diff --git a/Examples/Half_Adder/Half_Adder.sch b/Examples/Half_Adder/Half_Adder.sch new file mode 100644 index 00000000..d291f9cc --- /dev/null +++ b/Examples/Half_Adder/Half_Adder.sch @@ -0,0 +1,280 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:Half_Adder-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L half_adder X1 +U 1 1 558A91C8 +P 5000 3900 +F 0 "X1" H 5900 4400 60 0000 C CNN +F 1 "half_adder" H 5900 4300 60 0000 C CNN +F 2 "" H 5000 3900 60 0000 C CNN +F 3 "" H 5000 3900 60 0000 C CNN + 1 5000 3900 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_2 U1 +U 1 1 558A92C9 +P 4550 3500 +F 0 "U1" H 4550 3500 60 0000 C CNN +F 1 "adc_bridge_2" H 4550 3650 60 0000 C CNN +F 2 "" H 4550 3500 60 0000 C CNN +F 3 "" H 4550 3500 60 0000 C CNN + 1 4550 3500 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U2 +U 1 1 558A9300 +P 6950 3450 +F 0 "U2" H 6950 3450 60 0000 C CNN +F 1 "dac_bridge_2" H 7000 3600 60 0000 C CNN +F 2 "" H 6950 3450 60 0000 C CNN +F 3 "" H 6950 3450 60 0000 C CNN + 1 6950 3450 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 558A9345 +P 3450 3150 +F 0 "v1" H 3250 3250 60 0000 C CNN +F 1 "DC" H 3250 3100 60 0000 C CNN +F 2 "R1" H 3150 3150 60 0000 C CNN +F 3 "" H 3450 3150 60 0000 C CNN + 1 3450 3150 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 558A937C +P 3450 3800 +F 0 "v2" H 3250 3900 60 0000 C CNN +F 1 "DC" H 3250 3750 60 0000 C CNN +F 2 "R1" H 3150 3800 60 0000 C CNN +F 3 "" H 3450 3800 60 0000 C CNN + 1 3450 3800 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 558A93BB +P 2950 4000 +F 0 "#PWR01" H 2950 4000 30 0001 C CNN +F 1 "GND" H 2950 3930 30 0001 C CNN +F 2 "" H 2950 4000 60 0000 C CNN +F 3 "" H 2950 4000 60 0000 C CNN + 1 2950 4000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 558A93D7 +P 2950 3250 +F 0 "#PWR02" H 2950 3250 30 0001 C CNN +F 1 "GND" H 2950 3180 30 0001 C CNN +F 2 "" H 2950 3250 60 0000 C CNN +F 3 "" H 2950 3250 60 0000 C CNN + 1 2950 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 558A940C +P 7850 3300 +F 0 "R1" V 7930 3300 50 0000 C CNN +F 1 "1k" V 7850 3300 50 0000 C CNN +F 2 "" V 7780 3300 30 0000 C CNN +F 3 "" H 7850 3300 30 0000 C CNN + 1 7850 3300 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 558A945B +P 7850 3550 +F 0 "R2" V 7930 3550 50 0000 C CNN +F 1 "1k" V 7850 3550 50 0000 C CNN +F 2 "" V 7780 3550 30 0000 C CNN +F 3 "" H 7850 3550 30 0000 C CNN + 1 7850 3550 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 558A9480 +P 8350 3650 +F 0 "#PWR03" H 8350 3650 30 0001 C CNN +F 1 "GND" H 8350 3580 30 0001 C CNN +F 2 "" H 8350 3650 60 0000 C CNN +F 3 "" H 8350 3650 60 0000 C CNN + 1 8350 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 3150 2950 3150 +Wire Wire Line + 2950 3150 2950 3250 +Wire Wire Line + 3000 3800 2950 3800 +Wire Wire Line + 2950 3800 2950 4000 +Wire Wire Line + 3900 3800 3950 3800 +Wire Wire Line + 3950 3800 3950 3550 +Wire Wire Line + 3950 3450 3950 3150 +Wire Wire Line + 3950 3150 3900 3150 +Wire Wire Line + 5100 3450 5300 3450 +Wire Wire Line + 5300 3450 5300 3200 +Wire Wire Line + 5100 3550 5300 3550 +Wire Wire Line + 5300 3550 5300 3800 +Wire Wire Line + 6450 3200 6450 3400 +Wire Wire Line + 6450 3400 6500 3400 +Wire Wire Line + 6500 3500 6450 3500 +Wire Wire Line + 6450 3500 6450 3800 +Wire Wire Line + 7500 3400 7600 3400 +Wire Wire Line + 7600 3400 7600 3300 +Wire Wire Line + 7600 3300 7700 3300 +Wire Wire Line + 7500 3500 7600 3500 +Wire Wire Line + 7600 3500 7600 3550 +Wire Wire Line + 7600 3550 7700 3550 +Wire Wire Line + 8000 3300 8350 3300 +Wire Wire Line + 8350 3300 8350 3650 +Wire Wire Line + 8000 3550 8350 3550 +Wire Wire Line + 8350 3550 8350 3500 +Connection ~ 8350 3500 +$Comp +L PWR_FLAG #FLG04 +U 1 1 558A96D4 +P 2850 3850 +F 0 "#FLG04" H 2850 3945 50 0001 C CNN +F 1 "PWR_FLAG" H 2850 4030 50 0000 C CNN +F 2 "" H 2850 3850 60 0000 C CNN +F 3 "" H 2850 3850 60 0000 C CNN + 1 2850 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2850 3850 2850 3900 +Wire Wire Line + 2850 3900 2950 3900 +Connection ~ 2950 3900 +Text GLabel 7600 3150 0 60 Input ~ 0 +sum +Text GLabel 7600 3750 0 60 Input ~ 0 +cout +Text GLabel 4050 3150 2 60 Input ~ 0 +A +Text GLabel 4100 3750 2 60 Input ~ 0 +B +Text GLabel 5200 3250 0 60 Input ~ 0 +1 +Text GLabel 5200 3700 0 60 Input ~ 0 +2 +Text GLabel 6550 3250 2 60 Input ~ 0 +3 +Text GLabel 6550 3650 2 60 Input ~ 0 +4 +Wire Wire Line + 4050 3150 4050 3250 +Wire Wire Line + 4050 3250 3950 3250 +Connection ~ 3950 3250 +Wire Wire Line + 4100 3750 3950 3750 +Connection ~ 3950 3750 +Wire Wire Line + 5200 3700 5300 3700 +Connection ~ 5300 3700 +Wire Wire Line + 5200 3250 5250 3250 +Wire Wire Line + 5250 3250 5250 3450 +Connection ~ 5250 3450 +Wire Wire Line + 6550 3250 6450 3250 +Connection ~ 6450 3250 +Wire Wire Line + 6550 3650 6450 3650 +Connection ~ 6450 3650 +Wire Wire Line + 7600 3750 7650 3750 +Wire Wire Line + 7650 3750 7650 3550 +Connection ~ 7650 3550 +Wire Wire Line + 7600 3150 7650 3150 +Wire Wire Line + 7650 3150 7650 3300 +Connection ~ 7650 3300 +$EndSCHEMATC diff --git a/Examples/Half_Adder/Half_Adder_Previous_Values.xml b/Examples/Half_Adder/Half_Adder_Previous_Values.xml new file mode 100644 index 00000000..8622e049 --- /dev/null +++ b/Examples/Half_Adder/Half_Adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u1><u2 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u2></model><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Half_Adder/analysis b/Examples/Half_Adder/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Half_Adder/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Half_Adder/half_adder-cache.lib b/Examples/Half_Adder/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/Examples/Half_Adder/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Half_Adder/half_adder.cir b/Examples/Half_Adder/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/Examples/Half_Adder/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/Examples/Half_Adder/half_adder.cir.out b/Examples/Half_Adder/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/Examples/Half_Adder/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Half_Adder/half_adder.pro b/Examples/Half_Adder/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/Examples/Half_Adder/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/Examples/Half_Adder/half_adder.sch b/Examples/Half_Adder/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/Examples/Half_Adder/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/Examples/Half_Adder/half_adder.sub b/Examples/Half_Adder/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/Examples/Half_Adder/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/Examples/Half_Adder/half_adder_Previous_Values.xml b/Examples/Half_Adder/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/Examples/Half_Adder/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Half_Adder/plot_data_i.txt b/Examples/Half_Adder/plot_data_i.txt new file mode 100644 index 00000000..b212bde0 --- /dev/null +++ b/Examples/Half_Adder/plot_data_i.txt @@ -0,0 +1,135 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 15:44:17 2015 +Transient Analysis Wed Jul 1 11:38:38 2015 +-------------------------------------------------------------------------------- +Index time a2#branch_1_0 a2#branch_1_1 v1#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 -5.00000e-03 0.000000e+00 0.000000e+00 +1 1.000000e-05 -5.00000e-03 0.000000e+00 0.000000e+00 +2 2.000000e-05 -5.00000e-03 0.000000e+00 0.000000e+00 +3 4.000000e-05 -5.00000e-03 0.000000e+00 0.000000e+00 +4 8.000000e-05 -5.00000e-03 0.000000e+00 0.000000e+00 +5 1.600000e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +6 3.200000e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +7 6.400000e-04 -5.00000e-03 0.000000e+00 0.000000e+00 +8 1.280000e-03 -5.00000e-03 0.000000e+00 0.000000e+00 +9 2.560000e-03 -5.00000e-03 0.000000e+00 0.000000e+00 +10 4.560000e-03 -5.00000e-03 0.000000e+00 0.000000e+00 +11 6.560000e-03 -5.00000e-03 0.000000e+00 0.000000e+00 +12 8.560000e-03 -5.00000e-03 0.000000e+00 0.000000e+00 +13 1.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +14 1.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +15 1.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +16 1.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +17 1.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +18 2.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +19 2.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +20 2.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +21 2.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +22 2.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +23 3.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +24 3.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +25 3.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +26 3.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +27 3.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +28 4.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +29 4.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +30 4.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +31 4.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +32 4.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +33 5.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +34 5.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +35 5.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +36 5.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +37 5.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +38 6.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +39 6.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +40 6.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +41 6.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +42 6.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +43 7.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +44 7.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +45 7.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +46 7.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +47 7.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +48 8.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +49 8.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +50 8.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +51 8.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +52 8.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +53 9.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +54 9.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 + +Index time a2#branch_1_0 a2#branch_1_1 v1#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +56 9.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +57 9.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 +58 1.000000e-01 -5.00000e-03 0.000000e+00 0.000000e+00 + +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 15:44:17 2015 +Transient Analysis Wed Jul 1 11:38:38 2015 +-------------------------------------------------------------------------------- +Index time v2#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 +1 1.000000e-05 0.000000e+00 +2 2.000000e-05 0.000000e+00 +3 4.000000e-05 0.000000e+00 +4 8.000000e-05 0.000000e+00 +5 1.600000e-04 0.000000e+00 +6 3.200000e-04 0.000000e+00 +7 6.400000e-04 0.000000e+00 +8 1.280000e-03 0.000000e+00 +9 2.560000e-03 0.000000e+00 +10 4.560000e-03 0.000000e+00 +11 6.560000e-03 0.000000e+00 +12 8.560000e-03 0.000000e+00 +13 1.056000e-02 0.000000e+00 +14 1.256000e-02 0.000000e+00 +15 1.456000e-02 0.000000e+00 +16 1.656000e-02 0.000000e+00 +17 1.856000e-02 0.000000e+00 +18 2.056000e-02 0.000000e+00 +19 2.256000e-02 0.000000e+00 +20 2.456000e-02 0.000000e+00 +21 2.656000e-02 0.000000e+00 +22 2.856000e-02 0.000000e+00 +23 3.056000e-02 0.000000e+00 +24 3.256000e-02 0.000000e+00 +25 3.456000e-02 0.000000e+00 +26 3.656000e-02 0.000000e+00 +27 3.856000e-02 0.000000e+00 +28 4.056000e-02 0.000000e+00 +29 4.256000e-02 0.000000e+00 +30 4.456000e-02 0.000000e+00 +31 4.656000e-02 0.000000e+00 +32 4.856000e-02 0.000000e+00 +33 5.056000e-02 0.000000e+00 +34 5.256000e-02 0.000000e+00 +35 5.456000e-02 0.000000e+00 +36 5.656000e-02 0.000000e+00 +37 5.856000e-02 0.000000e+00 +38 6.056000e-02 0.000000e+00 +39 6.256000e-02 0.000000e+00 +40 6.456000e-02 0.000000e+00 +41 6.656000e-02 0.000000e+00 +42 6.856000e-02 0.000000e+00 +43 7.056000e-02 0.000000e+00 +44 7.256000e-02 0.000000e+00 +45 7.456000e-02 0.000000e+00 +46 7.656000e-02 0.000000e+00 +47 7.856000e-02 0.000000e+00 +48 8.056000e-02 0.000000e+00 +49 8.256000e-02 0.000000e+00 +50 8.456000e-02 0.000000e+00 +51 8.656000e-02 0.000000e+00 +52 8.856000e-02 0.000000e+00 +53 9.056000e-02 0.000000e+00 +54 9.256000e-02 0.000000e+00 + +Index time v2#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 0.000000e+00 +56 9.656000e-02 0.000000e+00 +57 9.856000e-02 0.000000e+00 +58 1.000000e-01 0.000000e+00 diff --git a/Examples/Half_Adder/plot_data_v.txt b/Examples/Half_Adder/plot_data_v.txt new file mode 100644 index 00000000..89095baa --- /dev/null +++ b/Examples/Half_Adder/plot_data_v.txt @@ -0,0 +1,135 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 15:44:17 2015 +Transient Analysis Wed Jul 1 11:38:38 2015 +-------------------------------------------------------------------------------- +Index time a b cout +-------------------------------------------------------------------------------- +0 0.000000e+00 5.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-05 5.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-05 5.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-05 5.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-05 5.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-04 5.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-04 5.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-04 5.000000e+00 0.000000e+00 0.000000e+00 +8 1.280000e-03 5.000000e+00 0.000000e+00 0.000000e+00 +9 2.560000e-03 5.000000e+00 0.000000e+00 0.000000e+00 +10 4.560000e-03 5.000000e+00 0.000000e+00 0.000000e+00 +11 6.560000e-03 5.000000e+00 0.000000e+00 0.000000e+00 +12 8.560000e-03 5.000000e+00 0.000000e+00 0.000000e+00 +13 1.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +14 1.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +15 1.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +16 1.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +17 1.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +18 2.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +19 2.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +20 2.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +21 2.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +22 2.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +23 3.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +24 3.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +25 3.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +26 3.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +27 3.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +28 4.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +29 4.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +30 4.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +31 4.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +32 4.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +33 5.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +34 5.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +35 5.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +36 5.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +37 5.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +38 6.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +39 6.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +40 6.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +41 6.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +42 6.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +43 7.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +44 7.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +45 7.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +46 7.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +47 7.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +48 8.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +49 8.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +50 8.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +51 8.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +52 8.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +53 9.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +54 9.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 + +Index time a b cout +-------------------------------------------------------------------------------- +55 9.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +56 9.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +57 9.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +58 1.000000e-01 5.000000e+00 0.000000e+00 0.000000e+00 + +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 15:44:17 2015 +Transient Analysis Wed Jul 1 11:38:38 2015 +-------------------------------------------------------------------------------- +Index time sum +-------------------------------------------------------------------------------- +0 0.000000e+00 5.000000e+00 +1 1.000000e-05 5.000000e+00 +2 2.000000e-05 5.000000e+00 +3 4.000000e-05 5.000000e+00 +4 8.000000e-05 5.000000e+00 +5 1.600000e-04 5.000000e+00 +6 3.200000e-04 5.000000e+00 +7 6.400000e-04 5.000000e+00 +8 1.280000e-03 5.000000e+00 +9 2.560000e-03 5.000000e+00 +10 4.560000e-03 5.000000e+00 +11 6.560000e-03 5.000000e+00 +12 8.560000e-03 5.000000e+00 +13 1.056000e-02 5.000000e+00 +14 1.256000e-02 5.000000e+00 +15 1.456000e-02 5.000000e+00 +16 1.656000e-02 5.000000e+00 +17 1.856000e-02 5.000000e+00 +18 2.056000e-02 5.000000e+00 +19 2.256000e-02 5.000000e+00 +20 2.456000e-02 5.000000e+00 +21 2.656000e-02 5.000000e+00 +22 2.856000e-02 5.000000e+00 +23 3.056000e-02 5.000000e+00 +24 3.256000e-02 5.000000e+00 +25 3.456000e-02 5.000000e+00 +26 3.656000e-02 5.000000e+00 +27 3.856000e-02 5.000000e+00 +28 4.056000e-02 5.000000e+00 +29 4.256000e-02 5.000000e+00 +30 4.456000e-02 5.000000e+00 +31 4.656000e-02 5.000000e+00 +32 4.856000e-02 5.000000e+00 +33 5.056000e-02 5.000000e+00 +34 5.256000e-02 5.000000e+00 +35 5.456000e-02 5.000000e+00 +36 5.656000e-02 5.000000e+00 +37 5.856000e-02 5.000000e+00 +38 6.056000e-02 5.000000e+00 +39 6.256000e-02 5.000000e+00 +40 6.456000e-02 5.000000e+00 +41 6.656000e-02 5.000000e+00 +42 6.856000e-02 5.000000e+00 +43 7.056000e-02 5.000000e+00 +44 7.256000e-02 5.000000e+00 +45 7.456000e-02 5.000000e+00 +46 7.656000e-02 5.000000e+00 +47 7.856000e-02 5.000000e+00 +48 8.056000e-02 5.000000e+00 +49 8.256000e-02 5.000000e+00 +50 8.456000e-02 5.000000e+00 +51 8.656000e-02 5.000000e+00 +52 8.856000e-02 5.000000e+00 +53 9.056000e-02 5.000000e+00 +54 9.256000e-02 5.000000e+00 + +Index time sum +-------------------------------------------------------------------------------- +55 9.456000e-02 5.000000e+00 +56 9.656000e-02 5.000000e+00 +57 9.856000e-02 5.000000e+00 +58 1.000000e-01 5.000000e+00 diff --git a/Examples/Halfwave_Rectifier/D.lib b/Examples/Halfwave_Rectifier/D.lib new file mode 100755 index 00000000..ef18bb50 --- /dev/null +++ b/Examples/Halfwave_Rectifier/D.lib @@ -0,0 +1,20 @@ +.MODEL D1N750 D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ Bv=8.1 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=880.5E-18 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/Examples/Halfwave_Rectifier/Halfwave_Rectifier-cache.lib b/Examples/Halfwave_Rectifier/Halfwave_Rectifier-cache.lib new file mode 100644 index 00000000..b5a381ce --- /dev/null +++ b/Examples/Halfwave_Rectifier/Halfwave_Rectifier-cache.lib @@ -0,0 +1,89 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# D +# +DEF D D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "D" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + Diode_* + D-Pak_TO252AA + *SingleDiode + *_Diode_* + *SingleDiode* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Halfwave_Rectifier/Halfwave_Rectifier.bak b/Examples/Halfwave_Rectifier/Halfwave_Rectifier.bak new file mode 100644 index 00000000..6008a5e9 --- /dev/null +++ b/Examples/Halfwave_Rectifier/Halfwave_Rectifier.bak @@ -0,0 +1,53 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:eSim_Miscellaneous +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC diff --git a/Examples/Halfwave_Rectifier/Halfwave_Rectifier.cir b/Examples/Halfwave_Rectifier/Halfwave_Rectifier.cir new file mode 100644 index 00000000..aef7b704 --- /dev/null +++ b/Examples/Halfwave_Rectifier/Halfwave_Rectifier.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jul 1 11:15:52 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +D1 IN OUT D +R1 OUT GND 1k +v1 IN GND sine + +.end diff --git a/Examples/Halfwave_Rectifier/Halfwave_Rectifier.cir.out b/Examples/Halfwave_Rectifier/Halfwave_Rectifier.cir.out new file mode 100644 index 00000000..5207e889 --- /dev/null +++ b/Examples/Halfwave_Rectifier/Halfwave_Rectifier.cir.out @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jul 1 11:15:52 2015 + +.include D.lib +d1 in out D1N750 +r1 out gnd 1k +v1 in gnd sine(0 2 50 0 0) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Halfwave_Rectifier/Halfwave_Rectifier.pro b/Examples/Halfwave_Rectifier/Halfwave_Rectifier.pro new file mode 100644 index 00000000..50b1770e --- /dev/null +++ b/Examples/Halfwave_Rectifier/Halfwave_Rectifier.pro @@ -0,0 +1,70 @@ +update=Wed Jul 1 11:12:33 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=/home/gaurav/Desktop/eSim Library/eSim_Subckt +LibName2=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName3=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName4=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName5=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName6=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName7=/home/gaurav/Desktop/eSim Library/eSim_Miscellaneous +LibName8=/home/gaurav/Desktop/eSim Library/eSim_User +LibName9=power +LibName10=device +LibName11=transistors +LibName12=conn +LibName13=linear +LibName14=regul +LibName15=74xx +LibName16=cmos4000 +LibName17=adc-dac +LibName18=memory +LibName19=xilinx +LibName20=microcontrollers +LibName21=dsp +LibName22=microchip +LibName23=analog_switches +LibName24=motorola +LibName25=texas +LibName26=intel +LibName27=audio +LibName28=interface +LibName29=digital-audio +LibName30=philips +LibName31=display +LibName32=cypress +LibName33=siliconi +LibName34=opto +LibName35=atmel +LibName36=contrib +LibName37=valves diff --git a/Examples/Halfwave_Rectifier/Halfwave_Rectifier.proj b/Examples/Halfwave_Rectifier/Halfwave_Rectifier.proj new file mode 100644 index 00000000..cd8e1689 --- /dev/null +++ b/Examples/Halfwave_Rectifier/Halfwave_Rectifier.proj @@ -0,0 +1 @@ +schematicFile Halfwave_Rectifier.sch diff --git a/Examples/Halfwave_Rectifier/Halfwave_Rectifier.sch b/Examples/Halfwave_Rectifier/Halfwave_Rectifier.sch new file mode 100644 index 00000000..da840534 --- /dev/null +++ b/Examples/Halfwave_Rectifier/Halfwave_Rectifier.sch @@ -0,0 +1,140 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:eSim_Miscellaneous +LIBS:eSim_User +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:Halfwave_Rectifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L D D1 +U 1 1 5593CBB8 +P 5700 2900 +F 0 "D1" H 5700 3000 50 0000 C CNN +F 1 "D" H 5700 2800 50 0000 C CNN +F 2 "" H 5700 2900 60 0000 C CNN +F 3 "" H 5700 2900 60 0000 C CNN + 1 5700 2900 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5593CC2C +P 6300 3350 +F 0 "R1" V 6380 3350 50 0000 C CNN +F 1 "1k" V 6300 3350 50 0000 C CNN +F 2 "" V 6230 3350 30 0000 C CNN +F 3 "" H 6300 3350 30 0000 C CNN + 1 6300 3350 + 1 0 0 -1 +$EndComp +$Comp +L sine v1 +U 1 1 5593CC81 +P 5050 3400 +F 0 "v1" H 4850 3500 60 0000 C CNN +F 1 "sine" H 4850 3350 60 0000 C CNN +F 2 "R1" H 4750 3400 60 0000 C CNN +F 3 "" H 5050 3400 60 0000 C CNN + 1 5050 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 5593CCF2 +P 5700 4050 +F 0 "#PWR01" H 5700 3800 50 0001 C CNN +F 1 "GND" H 5700 3900 50 0000 C CNN +F 2 "" H 5700 4050 60 0000 C CNN +F 3 "" H 5700 4050 60 0000 C CNN + 1 5700 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 2950 5050 2900 +Wire Wire Line + 5050 2900 5550 2900 +Wire Wire Line + 5850 2900 6300 2900 +Wire Wire Line + 6300 2900 6300 3200 +Wire Wire Line + 6300 3500 6300 3900 +Wire Wire Line + 6300 3900 5050 3900 +Wire Wire Line + 5050 3900 5050 3850 +Wire Wire Line + 5700 3800 5700 4050 +Connection ~ 5700 3900 +$Comp +L PWR_FLAG #FLG02 +U 1 1 5593CD49 +P 5700 3800 +F 0 "#FLG02" H 5700 3895 50 0001 C CNN +F 1 "PWR_FLAG" H 5700 3980 50 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +Text GLabel 5200 2750 0 60 Input ~ 0 +IN +Text GLabel 6200 2800 2 60 Input ~ 0 +OUT +Wire Wire Line + 5200 2750 5250 2750 +Wire Wire Line + 5250 2750 5250 2900 +Connection ~ 5250 2900 +Wire Wire Line + 6200 2800 6100 2800 +Wire Wire Line + 6100 2800 6100 2900 +Connection ~ 6100 2900 +$EndSCHEMATC diff --git a/Examples/Halfwave_Rectifier/Halfwave_Rectifier_Previous_Values.xml b/Examples/Halfwave_Rectifier/Halfwave_Rectifier_Previous_Values.xml new file mode 100644 index 00000000..e497fb71 --- /dev/null +++ b/Examples/Halfwave_Rectifier/Halfwave_Rectifier_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source><v1 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">2</field2><field3 name="Frequency">50</field3><field4 name="Delay Time">0</field4><field5 name="Damping Factor">0</field5></v1></source><model /><devicemodel><d1><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d1></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Halfwave_Rectifier/analysis b/Examples/Halfwave_Rectifier/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Halfwave_Rectifier/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Halfwave_Rectifier/plot_data_i.txt b/Examples/Halfwave_Rectifier/plot_data_i.txt new file mode 100644 index 00000000..1dbba44e --- /dev/null +++ b/Examples/Halfwave_Rectifier/plot_data_i.txt @@ -0,0 +1,69 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jul 1 11:15:52 2015 +Transient Analysis Wed Jul 1 11:18:15 2015 +-------------------------------------------------------------------------------- +Index time alli +-------------------------------------------------------------------------------- +0 0.000000e+00 -7.72087e-32 +1 1.000000e-05 -1.08306e-07 +2 2.000000e-05 -1.10674e-07 +3 4.000000e-05 -1.12292e-07 +4 8.000000e-05 -1.13899e-07 +5 1.600000e-04 -1.19071e-07 +6 3.200000e-04 -1.29247e-07 +7 6.400000e-04 -1.65196e-07 +8 1.280000e-03 -1.19696e-04 +9 1.926126e-03 -4.40792e-04 +10 2.657696e-03 -7.71076e-04 +11 3.403762e-03 -1.03378e-03 +12 4.895893e-03 -1.27428e-03 +13 6.895893e-03 -9.38866e-04 +14 8.895893e-03 -4.32200e-05 +15 1.089589e-02 2.834780e-07 +16 1.289589e-02 -1.72056e-07 +17 1.473004e-02 2.124164e-07 +18 1.673004e-02 -2.37142e-07 +19 1.873004e-02 1.409514e-07 +20 2.073004e-02 -3.87967e-07 +21 2.273004e-02 -8.00225e-04 +22 2.473004e-02 -1.26738e-03 +23 2.673004e-02 -9.93105e-04 +24 2.873004e-02 -1.14941e-04 +25 3.073004e-02 4.870695e-07 +26 3.273004e-02 -3.68691e-07 +27 3.473004e-02 4.119457e-07 +28 3.673004e-02 -4.36636e-07 +29 3.873004e-02 3.404039e-07 +30 4.073004e-02 -5.87052e-07 +31 4.273004e-02 -8.00219e-04 +32 4.473004e-02 -1.26738e-03 +33 4.673004e-02 -9.93101e-04 +34 4.873004e-02 -1.14978e-04 +35 5.073004e-02 6.863236e-07 +36 5.273004e-02 -5.67900e-07 +37 5.473004e-02 6.111180e-07 +38 5.673004e-02 -6.35774e-07 +39 5.873004e-02 5.394993e-07 +40 6.073004e-02 -7.85782e-07 +41 6.273004e-02 -8.00214e-04 +42 6.473004e-02 -1.26738e-03 +43 6.673004e-02 -9.93097e-04 +44 6.873004e-02 -1.15014e-04 +45 7.073004e-02 8.852210e-07 +46 7.273004e-02 -7.66753e-07 +47 7.473004e-02 8.099337e-07 +48 7.673004e-02 -8.34554e-07 +49 7.873004e-02 7.382383e-07 +50 8.073004e-02 -9.84160e-07 +51 8.273004e-02 -8.00208e-04 +52 8.473004e-02 -1.26738e-03 +53 8.673004e-02 -9.93093e-04 +54 8.873004e-02 -1.15051e-04 + +Index time alli +-------------------------------------------------------------------------------- +55 9.073004e-02 1.083762e-06 +56 9.273004e-02 -9.65249e-07 +57 9.473004e-02 1.008393e-06 +58 9.673004e-02 -1.03298e-06 +59 9.873004e-02 9.366216e-07 +60 1.000000e-01 -1.10922e-06 diff --git a/Examples/Halfwave_Rectifier/plot_data_v.txt b/Examples/Halfwave_Rectifier/plot_data_v.txt new file mode 100644 index 00000000..d6b3cfbb --- /dev/null +++ b/Examples/Halfwave_Rectifier/plot_data_v.txt @@ -0,0 +1,69 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jul 1 11:15:52 2015 +Transient Analysis Wed Jul 1 11:18:15 2015 +-------------------------------------------------------------------------------- +Index time in out +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 7.720868e-29 +1 1.000000e-05 6.283175e-03 1.083062e-04 +2 2.000000e-05 1.256629e-02 1.106736e-04 +3 4.000000e-05 2.513208e-02 1.122918e-04 +4 8.000000e-05 5.026019e-02 1.138991e-04 +5 1.600000e-04 1.004886e-01 1.190713e-04 +6 3.200000e-04 2.007234e-01 1.292469e-04 +7 6.400000e-04 3.994200e-01 1.651962e-04 +8 1.280000e-03 7.827473e-01 1.196959e-01 +9 1.926126e-03 1.137706e+00 4.407921e-01 +10 2.657696e-03 1.482512e+00 7.710761e-01 +11 3.403762e-03 1.753751e+00 1.033780e+00 +12 4.895893e-03 1.998930e+00 1.274279e+00 +13 6.895893e-03 1.655610e+00 9.388661e-01 +14 8.895893e-03 6.799031e-01 4.321996e-02 +15 1.089589e-02 -5.55504e-01 -2.83478e-04 +16 1.289589e-02 -1.57873e+00 1.720565e-04 +17 1.473004e-02 -1.99281e+00 -2.12416e-04 +18 1.673004e-02 -1.71180e+00 2.371423e-04 +19 1.873004e-02 -7.76939e-01 -1.40951e-04 +20 2.073004e-02 4.546858e-01 3.879668e-04 +21 2.273004e-02 1.512636e+00 8.002246e-01 +22 2.473004e-02 1.992811e+00 1.267384e+00 +23 2.673004e-02 1.711800e+00 9.931050e-01 +24 2.873004e-02 7.769394e-01 1.149414e-01 +25 3.073004e-02 -4.54686e-01 -4.87070e-04 +26 3.273004e-02 -1.51264e+00 3.686913e-04 +27 3.473004e-02 -1.99281e+00 -4.11946e-04 +28 3.673004e-02 -1.71180e+00 4.366365e-04 +29 3.873004e-02 -7.76939e-01 -3.40404e-04 +30 4.073004e-02 4.546858e-01 5.870517e-04 +31 4.273004e-02 1.512636e+00 8.002191e-01 +32 4.473004e-02 1.992811e+00 1.267384e+00 +33 4.673004e-02 1.711800e+00 9.931011e-01 +34 4.873004e-02 7.769394e-01 1.149778e-01 +35 5.073004e-02 -4.54686e-01 -6.86324e-04 +36 5.273004e-02 -1.51264e+00 5.679003e-04 +37 5.473004e-02 -1.99281e+00 -6.11118e-04 +38 5.673004e-02 -1.71180e+00 6.357735e-04 +39 5.873004e-02 -7.76939e-01 -5.39499e-04 +40 6.073004e-02 4.546858e-01 7.857825e-04 +41 6.273004e-02 1.512636e+00 8.002136e-01 +42 6.473004e-02 1.992811e+00 1.267384e+00 +43 6.673004e-02 1.711800e+00 9.930972e-01 +44 6.873004e-02 7.769394e-01 1.150142e-01 +45 7.073004e-02 -4.54686e-01 -8.85221e-04 +46 7.273004e-02 -1.51264e+00 7.667528e-04 +47 7.473004e-02 -1.99281e+00 -8.09934e-04 +48 7.673004e-02 -1.71180e+00 8.345542e-04 +49 7.873004e-02 -7.76939e-01 -7.38238e-04 +50 8.073004e-02 4.546858e-01 9.841597e-04 +51 8.273004e-02 1.512636e+00 8.002081e-01 +52 8.473004e-02 1.992811e+00 1.267384e+00 +53 8.673004e-02 1.711800e+00 9.930934e-01 +54 8.873004e-02 7.769394e-01 1.150506e-01 + +Index time in out +-------------------------------------------------------------------------------- +55 9.073004e-02 -4.54686e-01 -1.08376e-03 +56 9.273004e-02 -1.51264e+00 9.652493e-04 +57 9.473004e-02 -1.99281e+00 -1.00839e-03 +58 9.673004e-02 -1.71180e+00 1.032979e-03 +59 9.873004e-02 -7.76939e-01 -9.36622e-04 +60 1.000000e-01 -2.44929e-15 1.109217e-03 diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier-cache.lib b/Examples/Inverting_Amplifier/Inverting_Amplifier-cache.lib new file mode 100644 index 00000000..1d012df3 --- /dev/null +++ b/Examples/Inverting_Amplifier/Inverting_Amplifier-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# UA741 +# +DEF UA741 X 0 40 Y Y 1 F N +F0 "X" 150 0 60 H V C CNN +F1 "UA741" 250 -150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 0 150 0 -150 350 0 0 150 N +X + 1 -200 100 200 R 50 50 1 1 I +X - 2 -200 -100 200 R 50 50 1 1 I +X ~ 3 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier.cir b/Examples/Inverting_Amplifier/Inverting_Amplifier.cir new file mode 100644 index 00000000..736b20bc --- /dev/null +++ b/Examples/Inverting_Amplifier/Inverting_Amplifier.cir @@ -0,0 +1,14 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 22 15:31:09 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 Net-_R2-Pad1_ In Out UA741 +R2 Net-_R2-Pad1_ GND 1k +R3 GND Out 1k +R5 Out In 1k +v1 Net-_R1-Pad2_ GND sine +R1 In Net-_R1-Pad2_ 1k + +.end diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier.cir.out b/Examples/Inverting_Amplifier/Inverting_Amplifier.cir.out new file mode 100644 index 00000000..19176cc5 --- /dev/null +++ b/Examples/Inverting_Amplifier/Inverting_Amplifier.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: mon jun 22 15:31:09 2015 + +.include ua741.sub +x1 net-_r2-pad1_ in out ua741 +r2 net-_r2-pad1_ gnd 1k +r3 gnd out 1k +r5 out in 1k +v1 net-_r1-pad2_ gnd sine(0 2 50 0 0) +r1 in net-_r1-pad2_ 1k +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier.pro b/Examples/Inverting_Amplifier/Inverting_Amplifier.pro new file mode 100644 index 00000000..f6b5a5b9 --- /dev/null +++ b/Examples/Inverting_Amplifier/Inverting_Amplifier.pro @@ -0,0 +1,69 @@ +update=Mon Jun 22 14:48:33 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier.proj b/Examples/Inverting_Amplifier/Inverting_Amplifier.proj new file mode 100644 index 00000000..ea59291b --- /dev/null +++ b/Examples/Inverting_Amplifier/Inverting_Amplifier.proj @@ -0,0 +1 @@ +schematicFile Inverting_Amplifier.sch diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier.sch b/Examples/Inverting_Amplifier/Inverting_Amplifier.sch new file mode 100644 index 00000000..33941a0d --- /dev/null +++ b/Examples/Inverting_Amplifier/Inverting_Amplifier.sch @@ -0,0 +1,209 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L UA741 X1 +U 1 1 558820F5 +P 5500 3400 +F 0 "X1" H 5650 3400 60 0000 C CNN +F 1 "UA741" H 5750 3250 60 0000 C CNN +F 2 "" H 5500 3400 60 0000 C CNN +F 3 "" H 5500 3400 60 0000 C CNN + 1 5500 3400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 558821D4 +P 5050 3300 +F 0 "R2" V 5130 3300 50 0000 C CNN +F 1 "1k" V 5050 3300 50 0000 C CNN +F 2 "" V 4980 3300 30 0000 C CNN +F 3 "" H 5050 3300 30 0000 C CNN + 1 5050 3300 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 558821F0 +P 6450 3400 +F 0 "R3" V 6530 3400 50 0000 C CNN +F 1 "1k" V 6450 3400 50 0000 C CNN +F 2 "" V 6380 3400 30 0000 C CNN +F 3 "" H 6450 3400 30 0000 C CNN + 1 6450 3400 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 5588243E +P 3550 3950 +F 0 "#PWR01" H 3550 3950 30 0001 C CNN +F 1 "GND" H 3550 3880 30 0001 C CNN +F 2 "" H 3550 3950 60 0000 C CNN +F 3 "" H 3550 3950 60 0000 C CNN + 1 3550 3950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 558824A7 +P 6800 3450 +F 0 "#PWR02" H 6800 3450 30 0001 C CNN +F 1 "GND" H 6800 3380 30 0001 C CNN +F 2 "" H 6800 3450 60 0000 C CNN +F 3 "" H 6800 3450 60 0000 C CNN + 1 6800 3450 + 1 0 0 -1 +$EndComp +Text GLabel 6200 3250 0 60 Input ~ 0 +Out +Text GLabel 5250 3650 0 60 Input ~ 0 +In +$Comp +L PWR_FLAG #FLG03 +U 1 1 55882796 +P 6750 3300 +F 0 "#FLG03" H 6750 3395 50 0001 C CNN +F 1 "PWR_FLAG" H 6750 3480 50 0000 C CNN +F 2 "" H 6750 3300 60 0000 C CNN +F 3 "" H 6750 3300 60 0000 C CNN + 1 6750 3300 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 558828E5 +P 5800 4050 +F 0 "R5" V 5880 4050 50 0000 C CNN +F 1 "1k" V 5800 4050 50 0000 C CNN +F 2 "" V 5730 4050 30 0000 C CNN +F 3 "" H 5800 4050 30 0000 C CNN + 1 5800 4050 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR04 +U 1 1 55882C4B +P 4700 3300 +F 0 "#PWR04" H 4700 3300 30 0001 C CNN +F 1 "GND" H 4700 3230 30 0001 C CNN +F 2 "" H 4700 3300 60 0000 C CNN +F 3 "" H 4700 3300 60 0000 C CNN + 1 4700 3300 + 1 0 0 -1 +$EndComp +$Comp +L sine v1 +U 1 1 55882CA5 +P 4100 3700 +F 0 "v1" H 3900 3800 60 0000 C CNN +F 1 "sine" H 3900 3650 60 0000 C CNN +F 2 "R1" H 3800 3700 60 0000 C CNN +F 3 "" H 4100 3700 60 0000 C CNN + 1 4100 3700 + 0 1 1 0 +$EndComp +$Comp +L R R1 +U 1 1 55882CF2 +P 4850 3500 +F 0 "R1" V 4930 3500 50 0000 C CNN +F 1 "1k" V 4850 3500 50 0000 C CNN +F 2 "" V 4780 3500 30 0000 C CNN +F 3 "" H 4850 3500 30 0000 C CNN + 1 4850 3500 + 0 1 1 0 +$EndComp +Wire Wire Line + 4550 3500 4550 3700 +Wire Wire Line + 6050 3400 6300 3400 +Wire Wire Line + 6600 3400 6800 3400 +Wire Wire Line + 6800 3400 6800 3450 +Wire Wire Line + 3650 3700 3550 3700 +Wire Wire Line + 3550 3700 3550 3950 +Wire Wire Line + 5250 3650 5250 3550 +Wire Wire Line + 5250 3550 5200 3550 +Wire Wire Line + 5200 3550 5200 3500 +Connection ~ 5200 3500 +Wire Wire Line + 6200 3250 6200 3400 +Connection ~ 6200 3400 +Wire Wire Line + 6750 3300 6750 3400 +Connection ~ 6750 3400 +Wire Wire Line + 5950 4050 6100 4050 +Wire Wire Line + 6100 4050 6100 3400 +Connection ~ 6100 3400 +Wire Wire Line + 5100 4050 5650 4050 +Wire Wire Line + 5100 3500 5100 4050 +Connection ~ 5100 3500 +Wire Wire Line + 5200 3300 5300 3300 +Wire Wire Line + 4900 3300 4700 3300 +Wire Wire Line + 4700 3500 4550 3500 +Wire Wire Line + 5000 3500 5300 3500 +$EndSCHEMATC diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier_Previous_Values.xml b/Examples/Inverting_Amplifier/Inverting_Amplifier_Previous_Values.xml new file mode 100644 index 00000000..a3159c27 --- /dev/null +++ b/Examples/Inverting_Amplifier/Inverting_Amplifier_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">10</field1></v1><v2 name="Source type">dc<field1 name="Value">6</field1></v2><v1 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">2</field2><field3 name="Frequency">50</field3><field4 name="Delay Time">0</field4><field5 name="Damping Factor">0</field5></v1></source><model /><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Inverting_Amplifier/analysis b/Examples/Inverting_Amplifier/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Inverting_Amplifier/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Inverting_Amplifier/plot_data_i.txt b/Examples/Inverting_Amplifier/plot_data_i.txt new file mode 100644 index 00000000..d22ff735 --- /dev/null +++ b/Examples/Inverting_Amplifier/plot_data_i.txt @@ -0,0 +1,67 @@ +* eeschema netlist version 1.1 (spice format) creation date: mon jun 22 15:31:09 2015 +Transient Analysis Mon Jun 22 15:32:13 2015 +-------------------------------------------------------------------------------- +Index time e.x1.ein1#branc e.x1.eout1#bran v1#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-05 2.386032e-05 1.292478e-05 -6.40261e-06 +2 2.000000e-05 2.298287e-05 2.547805e-05 -1.26814e-05 +3 4.000000e-05 2.304574e-05 5.061101e-05 -2.52477e-05 +4 8.000000e-05 2.297299e-05 1.008670e-04 -5.03757e-05 +5 1.600000e-04 2.302203e-05 2.013264e-04 -1.00605e-04 +6 3.200000e-04 2.287019e-05 4.017971e-04 -2.00840e-04 +7 6.400000e-04 2.261624e-05 7.991932e-04 -3.99538e-04 +8 1.280000e-03 2.125925e-05 1.565841e-03 -7.82863e-04 +9 2.560000e-03 1.638914e-05 2.881532e-03 -1.44072e-03 +10 4.560000e-03 3.396704e-06 3.961965e-03 -1.98096e-03 +11 6.560000e-03 -1.13261e-05 3.529056e-03 -1.76455e-03 +12 8.560000e-03 -2.12895e-05 1.748174e-03 -8.74135e-04 +13 1.056000e-02 -2.35546e-05 -7.00458e-04 3.501680e-04 +14 1.256000e-02 -1.63887e-05 -2.88153e-03 1.440717e-03 +15 1.456000e-02 -3.39713e-06 -3.96197e-03 1.980963e-03 +16 1.656000e-02 1.132653e-05 -3.52906e-03 1.764546e-03 +17 1.856000e-02 2.128905e-05 -1.74817e-03 8.741351e-04 +18 2.056000e-02 2.355498e-05 7.004579e-04 -3.50168e-04 +19 2.256000e-02 1.638829e-05 2.881532e-03 -1.44072e-03 +20 2.456000e-02 3.397556e-06 3.961965e-03 -1.98096e-03 +21 2.656000e-02 -1.13270e-05 3.529056e-03 -1.76455e-03 +22 2.856000e-02 -2.12886e-05 1.748174e-03 -8.74135e-04 +23 3.056000e-02 -2.35554e-05 -7.00458e-04 3.501680e-04 +24 3.256000e-02 -1.63879e-05 -2.88153e-03 1.440717e-03 +25 3.456000e-02 -3.39798e-06 -3.96197e-03 1.980963e-03 +26 3.656000e-02 1.132739e-05 -3.52906e-03 1.764546e-03 +27 3.856000e-02 2.128820e-05 -1.74817e-03 8.741351e-04 +28 4.056000e-02 2.355584e-05 7.004580e-04 -3.50168e-04 +29 4.256000e-02 1.638744e-05 2.881532e-03 -1.44072e-03 +30 4.456000e-02 3.398413e-06 3.961965e-03 -1.98096e-03 +31 4.656000e-02 -1.13278e-05 3.529056e-03 -1.76455e-03 +32 4.856000e-02 -2.12878e-05 1.748174e-03 -8.74135e-04 +33 5.056000e-02 -2.35563e-05 -7.00458e-04 3.501680e-04 +34 5.256000e-02 -1.63870e-05 -2.88153e-03 1.440717e-03 +35 5.456000e-02 -3.39884e-06 -3.96197e-03 1.980963e-03 +36 5.656000e-02 1.132825e-05 -3.52906e-03 1.764546e-03 +37 5.856000e-02 2.128733e-05 -1.74817e-03 8.741351e-04 +38 6.056000e-02 2.355670e-05 7.004580e-04 -3.50168e-04 +39 6.256000e-02 1.638657e-05 2.881532e-03 -1.44072e-03 +40 6.456000e-02 3.399277e-06 3.961965e-03 -1.98096e-03 +41 6.656000e-02 -1.13287e-05 3.529056e-03 -1.76455e-03 +42 6.856000e-02 -2.12869e-05 1.748174e-03 -8.74135e-04 +43 7.056000e-02 -2.35571e-05 -7.00458e-04 3.501680e-04 +44 7.256000e-02 -1.63861e-05 -2.88153e-03 1.440717e-03 +45 7.456000e-02 -3.39971e-06 -3.96197e-03 1.980963e-03 +46 7.656000e-02 1.132912e-05 -3.52906e-03 1.764546e-03 +47 7.856000e-02 2.128647e-05 -1.74817e-03 8.741351e-04 +48 8.056000e-02 2.355757e-05 7.004580e-04 -3.50168e-04 +49 8.256000e-02 1.638570e-05 2.881532e-03 -1.44072e-03 +50 8.456000e-02 3.400147e-06 3.961965e-03 -1.98096e-03 +51 8.656000e-02 -1.13296e-05 3.529056e-03 -1.76455e-03 +52 8.856000e-02 -2.12860e-05 1.748174e-03 -8.74135e-04 +53 9.056000e-02 -2.35580e-05 -7.00458e-04 3.501680e-04 +54 9.256000e-02 -1.63853e-05 -2.88153e-03 1.440717e-03 + +Index time e.x1.ein1#branc e.x1.eout1#bran v1#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 -3.40058e-06 -3.96197e-03 1.980963e-03 +56 9.656000e-02 1.132999e-05 -3.52906e-03 1.764546e-03 +57 9.856000e-02 2.128559e-05 -1.74817e-03 8.741351e-04 +58 1.000000e-01 2.318983e-05 3.481451e-07 -1.16010e-07 diff --git a/Examples/Inverting_Amplifier/plot_data_v.txt b/Examples/Inverting_Amplifier/plot_data_v.txt new file mode 100644 index 00000000..968de4c5 --- /dev/null +++ b/Examples/Inverting_Amplifier/plot_data_v.txt @@ -0,0 +1,203 @@ +* eeschema netlist version 1.1 (spice format) creation date: mon jun 22 15:31:09 2015 +Transient Analysis Mon Jun 22 15:32:13 2015 +-------------------------------------------------------------------------------- +Index time in net-_r1-pad2_ net-_r2-pad1_ +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-05 -1.19436e-04 6.283175e-03 -5.96883e-08 +2 2.000000e-05 -1.15119e-04 1.256629e-02 -5.75307e-08 +3 4.000000e-05 -1.15578e-04 2.513208e-02 -5.77601e-08 +4 8.000000e-05 -1.15503e-04 5.026019e-02 -5.77228e-08 +5 1.600000e-04 -1.16326e-04 1.004886e-01 -5.81342e-08 +6 3.200000e-04 -1.16720e-04 2.007234e-01 -5.83309e-08 +7 6.400000e-04 -1.17736e-04 3.994200e-01 -5.88386e-08 +8 1.280000e-03 -1.15358e-04 7.827473e-01 -5.76502e-08 +9 2.560000e-03 -9.85643e-05 1.440618e+00 -4.92575e-08 +10 4.560000e-03 -3.97849e-05 1.980923e+00 -1.98825e-08 +11 6.560000e-03 3.635683e-05 1.764582e+00 1.816933e-08 +12 8.560000e-03 9.644407e-05 8.742315e-01 4.819794e-08 +13 1.056000e-02 1.218619e-04 -3.50046e-01 6.090050e-08 +14 1.256000e-02 9.856215e-05 -1.44062e+00 4.925645e-08 +15 1.456000e-02 3.978703e-05 -1.98092e+00 1.988357e-08 +16 1.656000e-02 -3.63590e-05 -1.76458e+00 -1.81704e-08 +17 1.856000e-02 -9.64419e-05 -8.74232e-01 -4.81969e-08 +18 2.056000e-02 -1.21864e-04 3.500461e-01 -6.09016e-08 +19 2.256000e-02 -9.85600e-05 1.440618e+00 -4.92554e-08 +20 2.456000e-02 -3.97892e-05 1.980923e+00 -1.98846e-08 +21 2.656000e-02 3.636109e-05 1.764582e+00 1.817146e-08 +22 2.856000e-02 9.643981e-05 8.742315e-01 4.819581e-08 +23 3.056000e-02 1.218662e-04 -3.50046e-01 6.090264e-08 +24 3.256000e-02 9.855788e-05 -1.44062e+00 4.925431e-08 +25 3.456000e-02 3.979130e-05 -1.98092e+00 1.988571e-08 +26 3.656000e-02 -3.63632e-05 -1.76458e+00 -1.81725e-08 +27 3.856000e-02 -9.64377e-05 -8.74232e-01 -4.81947e-08 +28 4.056000e-02 -1.21868e-04 3.500461e-01 -6.09037e-08 +29 4.256000e-02 -9.85557e-05 1.440618e+00 -4.92532e-08 +30 4.456000e-02 -3.97935e-05 1.980923e+00 -1.98868e-08 +31 4.656000e-02 3.636538e-05 1.764582e+00 1.817360e-08 +32 4.856000e-02 9.643551e-05 8.742315e-01 4.819366e-08 +33 5.056000e-02 1.218705e-04 -3.50046e-01 6.090479e-08 +34 5.256000e-02 9.855358e-05 -1.44062e+00 4.925216e-08 +35 5.456000e-02 3.979561e-05 -1.98092e+00 1.988786e-08 +36 5.656000e-02 -3.63675e-05 -1.76458e+00 -1.81747e-08 +37 5.856000e-02 -9.64334e-05 -8.74232e-01 -4.81926e-08 +38 6.056000e-02 -1.21873e-04 3.500461e-01 -6.09059e-08 +39 6.256000e-02 -9.85514e-05 1.440618e+00 -4.92511e-08 +40 6.456000e-02 -3.97978e-05 1.980923e+00 -1.98889e-08 +41 6.656000e-02 3.636971e-05 1.764582e+00 1.817577e-08 +42 6.856000e-02 9.643118e-05 8.742315e-01 4.819150e-08 +43 7.056000e-02 1.218748e-04 -3.50046e-01 6.090695e-08 +44 7.256000e-02 9.854924e-05 -1.44062e+00 4.925000e-08 +45 7.456000e-02 3.979995e-05 -1.98092e+00 1.989003e-08 +46 7.656000e-02 -3.63719e-05 -1.76458e+00 -1.81769e-08 +47 7.856000e-02 -9.64290e-05 -8.74232e-01 -4.81904e-08 +48 8.056000e-02 -1.21877e-04 3.500461e-01 -6.09080e-08 +49 8.256000e-02 -9.85471e-05 1.440618e+00 -4.92489e-08 +50 8.456000e-02 -3.98021e-05 1.980923e+00 -1.98911e-08 +51 8.656000e-02 3.637406e-05 1.764582e+00 1.817794e-08 +52 8.856000e-02 9.642682e-05 8.742315e-01 4.818932e-08 +53 9.056000e-02 1.218792e-04 -3.50046e-01 6.090913e-08 +54 9.256000e-02 9.854488e-05 -1.44062e+00 4.924782e-08 + +Index time in net-_r1-pad2_ net-_r2-pad1_ +-------------------------------------------------------------------------------- +55 9.456000e-02 3.980431e-05 -1.98092e+00 1.989221e-08 +56 9.656000e-02 -3.63763e-05 -1.76458e+00 -1.81790e-08 +57 9.856000e-02 -9.64246e-05 -8.74232e-01 -4.81882e-08 +58 1.000000e-01 -1.16010e-04 -2.44929e-15 -5.79759e-08 + +* eeschema netlist version 1.1 (spice format) creation date: mon jun 22 15:31:09 2015 +Transient Analysis Mon Jun 22 15:32:13 2015 +-------------------------------------------------------------------------------- +Index time out x1.1 x1.2 +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-05 -6.52211e-03 -7.49147e-03 -7.49147e-03 +2 2.000000e-05 -1.27966e-02 -1.47074e-02 -1.47074e-02 +3 4.000000e-05 -2.53633e-02 -2.91591e-02 -2.91591e-02 +4 8.000000e-05 -5.04913e-02 -5.80563e-02 -5.80563e-02 +5 1.600000e-04 -1.00721e-01 -1.15821e-01 -1.15821e-01 +6 3.200000e-04 -2.00957e-01 -2.31092e-01 -2.31092e-01 +7 6.400000e-04 -3.99655e-01 -4.59595e-01 -4.59595e-01 +8 1.280000e-03 -7.82978e-01 -9.00416e-01 -9.00416e-01 +9 2.560000e-03 -1.44082e+00 -1.65693e+00 -1.65693e+00 +10 4.560000e-03 -1.98100e+00 -2.27815e+00 -2.27815e+00 +11 6.560000e-03 -1.76451e+00 -2.02919e+00 -2.02919e+00 +12 8.560000e-03 -8.74039e-01 -1.00515e+00 -1.00515e+00 +13 1.056000e-02 3.502899e-01 4.028242e-01 4.028242e-01 +14 1.256000e-02 1.440815e+00 1.656930e+00 1.656930e+00 +15 1.456000e-02 1.981002e+00 2.278150e+00 2.278150e+00 +16 1.656000e-02 1.764510e+00 2.029189e+00 2.029189e+00 +17 1.856000e-02 8.740386e-01 1.005152e+00 1.005152e+00 +18 2.056000e-02 -3.50290e-01 -4.02824e-01 -4.02824e-01 +19 2.256000e-02 -1.44082e+00 -1.65693e+00 -1.65693e+00 +20 2.456000e-02 -1.98100e+00 -2.27815e+00 -2.27815e+00 +21 2.656000e-02 -1.76451e+00 -2.02919e+00 -2.02919e+00 +22 2.856000e-02 -8.74039e-01 -1.00515e+00 -1.00515e+00 +23 3.056000e-02 3.502899e-01 4.028243e-01 4.028243e-01 +24 3.256000e-02 1.440815e+00 1.656930e+00 1.656930e+00 +25 3.456000e-02 1.981002e+00 2.278150e+00 2.278150e+00 +26 3.656000e-02 1.764510e+00 2.029189e+00 2.029189e+00 +27 3.856000e-02 8.740386e-01 1.005152e+00 1.005152e+00 +28 4.056000e-02 -3.50290e-01 -4.02824e-01 -4.02824e-01 +29 4.256000e-02 -1.44082e+00 -1.65693e+00 -1.65693e+00 +30 4.456000e-02 -1.98100e+00 -2.27815e+00 -2.27815e+00 +31 4.656000e-02 -1.76451e+00 -2.02919e+00 -2.02919e+00 +32 4.856000e-02 -8.74039e-01 -1.00515e+00 -1.00515e+00 +33 5.056000e-02 3.502899e-01 4.028243e-01 4.028243e-01 +34 5.256000e-02 1.440815e+00 1.656930e+00 1.656930e+00 +35 5.456000e-02 1.981002e+00 2.278150e+00 2.278150e+00 +36 5.656000e-02 1.764510e+00 2.029189e+00 2.029189e+00 +37 5.856000e-02 8.740386e-01 1.005152e+00 1.005152e+00 +38 6.056000e-02 -3.50290e-01 -4.02824e-01 -4.02824e-01 +39 6.256000e-02 -1.44082e+00 -1.65693e+00 -1.65693e+00 +40 6.456000e-02 -1.98100e+00 -2.27815e+00 -2.27815e+00 +41 6.656000e-02 -1.76451e+00 -2.02919e+00 -2.02919e+00 +42 6.856000e-02 -8.74039e-01 -1.00515e+00 -1.00515e+00 +43 7.056000e-02 3.502899e-01 4.028243e-01 4.028243e-01 +44 7.256000e-02 1.440815e+00 1.656930e+00 1.656930e+00 +45 7.456000e-02 1.981002e+00 2.278150e+00 2.278150e+00 +46 7.656000e-02 1.764510e+00 2.029189e+00 2.029189e+00 +47 7.856000e-02 8.740386e-01 1.005152e+00 1.005152e+00 +48 8.056000e-02 -3.50290e-01 -4.02824e-01 -4.02824e-01 +49 8.256000e-02 -1.44082e+00 -1.65693e+00 -1.65693e+00 +50 8.456000e-02 -1.98100e+00 -2.27815e+00 -2.27815e+00 +51 8.656000e-02 -1.76451e+00 -2.02919e+00 -2.02919e+00 +52 8.856000e-02 -8.74039e-01 -1.00515e+00 -1.00515e+00 +53 9.056000e-02 3.502899e-01 4.028243e-01 4.028243e-01 +54 9.256000e-02 1.440815e+00 1.656930e+00 1.656930e+00 + +Index time out x1.1 x1.2 +-------------------------------------------------------------------------------- +55 9.456000e-02 1.981002e+00 2.278150e+00 2.278150e+00 +56 9.656000e-02 1.764510e+00 2.029189e+00 2.029189e+00 +57 9.856000e-02 8.740386e-01 1.005152e+00 1.005152e+00 +58 1.000000e-01 -2.32077e-04 -2.58188e-04 -2.58188e-04 + +* eeschema netlist version 1.1 (spice format) creation date: mon jun 22 15:31:09 2015 +Transient Analysis Mon Jun 22 15:32:13 2015 +-------------------------------------------------------------------------------- +Index time x1.4 +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 +1 1.000000e-05 -1.19377e+01 +2 2.000000e-05 -1.15061e+01 +3 4.000000e-05 -1.15520e+01 +4 8.000000e-05 -1.15446e+01 +5 1.600000e-04 -1.16268e+01 +6 3.200000e-04 -1.16662e+01 +7 6.400000e-04 -1.17677e+01 +8 1.280000e-03 -1.15300e+01 +9 2.560000e-03 -9.85150e+00 +10 4.560000e-03 -3.97650e+00 +11 6.560000e-03 3.633866e+00 +12 8.560000e-03 9.639588e+00 +13 1.056000e-02 1.218010e+01 +14 1.256000e-02 9.851290e+00 +15 1.456000e-02 3.976714e+00 +16 1.656000e-02 -3.63408e+00 +17 1.856000e-02 -9.63937e+00 +18 2.056000e-02 -1.21803e+01 +19 2.256000e-02 -9.85108e+00 +20 2.456000e-02 -3.97693e+00 +21 2.656000e-02 3.634292e+00 +22 2.856000e-02 9.639161e+00 +23 3.056000e-02 1.218053e+01 +24 3.256000e-02 9.850863e+00 +25 3.456000e-02 3.977142e+00 +26 3.656000e-02 -3.63451e+00 +27 3.856000e-02 -9.63895e+00 +28 4.056000e-02 -1.21807e+01 +29 4.256000e-02 -9.85065e+00 +30 4.456000e-02 -3.97736e+00 +31 4.656000e-02 3.634721e+00 +32 4.856000e-02 9.638732e+00 +33 5.056000e-02 1.218096e+01 +34 5.256000e-02 9.850432e+00 +35 5.456000e-02 3.977572e+00 +36 5.656000e-02 -3.63494e+00 +37 5.856000e-02 -9.63852e+00 +38 6.056000e-02 -1.21812e+01 +39 6.256000e-02 -9.85022e+00 +40 6.456000e-02 -3.97779e+00 +41 6.656000e-02 3.635153e+00 +42 6.856000e-02 9.638299e+00 +43 7.056000e-02 1.218139e+01 +44 7.256000e-02 9.849999e+00 +45 7.456000e-02 3.978006e+00 +46 7.656000e-02 -3.63537e+00 +47 7.856000e-02 -9.63808e+00 +48 8.056000e-02 -1.21816e+01 +49 8.256000e-02 -9.84978e+00 +50 8.456000e-02 -3.97822e+00 +51 8.656000e-02 3.635589e+00 +52 8.856000e-02 9.637864e+00 +53 9.056000e-02 1.218183e+01 +54 9.256000e-02 9.849563e+00 + +Index time x1.4 +-------------------------------------------------------------------------------- +55 9.456000e-02 3.978442e+00 +56 9.656000e-02 -3.63581e+00 +57 9.856000e-02 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+DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Inverting_Amplifier/ua741.bak b/Examples/Inverting_Amplifier/ua741.bak new file mode 100644 index 00000000..4e9a8119 --- /dev/null +++ b/Examples/Inverting_Amplifier/ua741.bak @@ -0,0 +1,245 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN +F 2 "" H 6250 2500 60 0001 C CNN +F 3 "" H 6250 2500 60 0001 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 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0001 C CNN +F 3 "" H 5200 2900 60 0001 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN +F 2 "" H 4550 2900 60 0001 C CNN +F 3 "" H 4550 2900 60 0001 C CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN +F 2 "" H 4150 2500 60 0001 C CNN +F 3 "" H 4150 2500 60 0001 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN +F 2 "" H 3700 3400 60 0001 C CNN +F 3 "" H 3700 3400 60 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN +F 2 "" H 3650 2850 60 0001 C CNN +F 3 "" H 3650 2850 60 0001 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN +F 2 "" H 3000 2850 60 0001 C CNN +F 3 "" H 3000 2850 60 0001 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3050 4550 3300 +Wire Wire Line + 3700 2500 4000 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2750 +Wire Wire Line + 4300 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5450 2500 +Wire Wire Line + 5750 2500 6000 2500 +Wire Wire Line + 3000 3100 3000 3000 +Wire Wire Line + 3000 2700 3000 2600 +$EndSCHEMATC diff --git a/Examples/Inverting_Amplifier/ua741.cir b/Examples/Inverting_Amplifier/ua741.cir new file mode 100644 index 00000000..de797429 --- /dev/null +++ b/Examples/Inverting_Amplifier/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/Examples/Inverting_Amplifier/ua741.cir.ckt b/Examples/Inverting_Amplifier/ua741.cir.ckt new file mode 100644 index 00000000..3661a9a2 --- /dev/null +++ b/Examples/Inverting_Amplifier/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/Examples/Inverting_Amplifier/ua741.cir.out b/Examples/Inverting_Amplifier/ua741.cir.out new file mode 100644 index 00000000..72e68514 --- /dev/null +++ b/Examples/Inverting_Amplifier/ua741.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +* u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Inverting_Amplifier/ua741.pro b/Examples/Inverting_Amplifier/ua741.pro new file mode 100644 index 00000000..5dbb81a5 --- /dev/null +++ b/Examples/Inverting_Amplifier/ua741.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:14:06 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/Examples/Inverting_Amplifier/ua741.sch b/Examples/Inverting_Amplifier/ua741.sch new file mode 100644 index 00000000..4e9a8119 --- /dev/null +++ b/Examples/Inverting_Amplifier/ua741.sch @@ -0,0 +1,245 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN +F 2 "" H 6250 2500 60 0001 C CNN +F 3 "" H 6250 2500 60 0001 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN +F 2 "" H 2300 3100 60 0001 C CNN +F 3 "" H 2300 3100 60 0001 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN +F 2 "" H 2250 2600 60 0001 C CNN +F 3 "" H 2250 2600 60 0001 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN +F 2 "" H 3450 3200 60 0001 C CNN +F 3 "" H 3450 3200 60 0001 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN +F 2 "" H 5600 2500 60 0001 C CNN +F 3 "" H 5600 2500 60 0001 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN +F 2 "" H 5200 2900 60 0001 C CNN +F 3 "" H 5200 2900 60 0001 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN +F 2 "" H 4550 2900 60 0001 C CNN +F 3 "" H 4550 2900 60 0001 C CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN +F 2 "" H 4150 2500 60 0001 C CNN +F 3 "" H 4150 2500 60 0001 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN +F 2 "" H 3700 3400 60 0001 C CNN +F 3 "" H 3700 3400 60 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN +F 2 "" H 3650 2850 60 0001 C CNN +F 3 "" H 3650 2850 60 0001 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN +F 2 "" H 3000 2850 60 0001 C CNN +F 3 "" H 3000 2850 60 0001 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3050 4550 3300 +Wire Wire Line + 3700 2500 4000 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2750 +Wire Wire Line + 4300 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5450 2500 +Wire Wire Line + 5750 2500 6000 2500 +Wire Wire Line + 3000 3100 3000 3000 +Wire Wire Line + 3000 2700 3000 2600 +$EndSCHEMATC diff --git a/Examples/Inverting_Amplifier/ua741.sub b/Examples/Inverting_Amplifier/ua741.sub new file mode 100644 index 00000000..ad26c001 --- /dev/null +++ b/Examples/Inverting_Amplifier/ua741.sub @@ -0,0 +1,12 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +* Control Statements + +.ends ua741
\ No newline at end of file diff --git a/Examples/Inverting_Amplifier/ua741_Previous_Values.xml b/Examples/Inverting_Amplifier/ua741_Previous_Values.xml new file mode 100644 index 00000000..9c7bb530 --- /dev/null +++ b/Examples/Inverting_Amplifier/ua741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/bridgerectifier/D.lib b/Examples/bridgerectifier/D.lib new file mode 100755 index 00000000..ef18bb50 --- /dev/null +++ b/Examples/bridgerectifier/D.lib @@ -0,0 +1,20 @@ +.MODEL D1N750 D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ Bv=8.1 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=880.5E-18 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/Examples/bridgerectifier/analysis b/Examples/bridgerectifier/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/bridgerectifier/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/bridgerectifier/bridgerectifier-cache.lib b/Examples/bridgerectifier/bridgerectifier-cache.lib new file mode 100644 index 00000000..94a8fc8e --- /dev/null +++ b/Examples/bridgerectifier/bridgerectifier-cache.lib @@ -0,0 +1,89 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# D +# +DEF D D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "D" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + Diode_* + D-Pak_TO252AA + *SingleDiode + *_Diode_* + *SingleDiode* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/bridgerectifier/bridgerectifier.bak b/Examples/bridgerectifier/bridgerectifier.bak new file mode 100644 index 00000000..74e2aead --- /dev/null +++ b/Examples/bridgerectifier/bridgerectifier.bak @@ -0,0 +1,182 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:bridgerectifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L D D1 +U 1 1 557F721F +P 4000 3000 +F 0 "D1" H 4000 3100 50 0000 C CNN +F 1 "D" H 4000 2900 50 0000 C CNN +F 2 "" H 4000 3000 60 0000 C CNN +F 3 "" H 4000 3000 60 0000 C CNN + 1 4000 3000 + 0 -1 -1 0 +$EndComp +$Comp +L D D3 +U 1 1 557F72FE +P 4950 3000 +F 0 "D3" H 4950 3100 50 0000 C CNN +F 1 "D" H 4950 2900 50 0000 C CNN +F 2 "" H 4950 3000 60 0000 C CNN +F 3 "" H 4950 3000 60 0000 C CNN + 1 4950 3000 + 0 -1 -1 0 +$EndComp +$Comp +L D D4 +U 1 1 557F7345 +P 4950 4400 +F 0 "D4" H 4950 4500 50 0000 C CNN +F 1 "D" V 4950 4300 50 0000 C CNN +F 2 "" H 4950 4400 60 0000 C CNN +F 3 "" H 4950 4400 60 0000 C CNN + 1 4950 4400 + 0 -1 -1 0 +$EndComp +$Comp +L D D2 +U 1 1 557F745E +P 4000 4400 +F 0 "D2" H 4000 4500 50 0000 C CNN +F 1 "D" H 4000 4300 50 0000 C CNN +F 2 "" H 4000 4400 60 0000 C CNN +F 3 "" H 4000 4400 60 0000 C CNN + 1 4000 4400 + 0 -1 -1 0 +$EndComp +$Comp +L R R1 +U 1 1 557F76BB +P 5550 3600 +F 0 "R1" V 5630 3600 50 0000 C CNN +F 1 "1000" V 5550 3600 50 0000 C CNN +F 2 "" V 5480 3600 30 0000 C CNN +F 3 "" H 5550 3600 30 0000 C CNN + 1 5550 3600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 557F76F4 +P 5400 5300 +F 0 "#PWR01" H 5400 5050 50 0001 C CNN +F 1 "GND" H 5400 5150 50 0000 C CNN +F 2 "" H 5400 5300 60 0000 C CNN +F 3 "" H 5400 5300 60 0000 C CNN + 1 5400 5300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4000 2850 4000 2550 +Wire Wire Line + 4000 2550 5550 2550 +Wire Wire Line + 4950 2550 4950 2850 +Wire Wire Line + 5550 2550 5550 3450 +Connection ~ 4950 2550 +Wire Wire Line + 5550 4750 5550 3750 +Wire Wire Line + 4950 4750 4950 4550 +Wire Wire Line + 4000 4750 4000 4550 +Connection ~ 4950 4750 +Wire Wire Line + 4000 4750 5550 4750 +Connection ~ 5400 5300 +Connection ~ 5400 4750 +Wire Wire Line + 5400 4750 5400 5300 +Wire Wire Line + 4000 3150 4000 4250 +Wire Wire Line + 4950 3150 4950 4250 +Wire Wire Line + 4950 3750 3650 3750 +Wire Wire Line + 3650 3750 3650 4050 +Wire Wire Line + 3650 4050 3400 4050 +Connection ~ 4950 3750 +Wire Wire Line + 3400 3150 3800 3150 +Wire Wire Line + 3800 3150 3800 3400 +Wire Wire Line + 3800 3400 4000 3400 +Connection ~ 4000 3400 +$Comp +L PWR_FLAG #FLG02 +U 1 1 557F7E1A +P 5250 4400 +F 0 "#FLG02" H 5250 4495 50 0001 C CNN +F 1 "PWR_FLAG" H 5250 4580 50 0000 C CNN +F 2 "" H 5250 4400 60 0000 C CNN +F 3 "" H 5250 4400 60 0000 C CNN + 1 5250 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 4400 5250 4750 +Connection ~ 5250 4750 +$Comp +L sine v1 +U 1 1 557F7569 +P 3400 3600 +F 0 "v1" H 3200 3700 60 0000 C CNN +F 1 "sine" H 3200 3550 60 0000 C CNN +F 2 "R1" H 3100 3600 60 0000 C CNN +F 3 "" H 3400 3600 60 0000 C CNN + 1 3400 3600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/bridgerectifier/bridgerectifier.cir b/Examples/bridgerectifier/bridgerectifier.cir new file mode 100644 index 00000000..42538839 --- /dev/null +++ b/Examples/bridgerectifier/bridgerectifier.cir @@ -0,0 +1,14 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 17 14:53:06 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ D +D3 Net-_D3-Pad1_ Net-_D1-Pad2_ D +D4 GND Net-_D3-Pad1_ D +D2 GND Net-_D1-Pad1_ D +R1 Net-_D1-Pad2_ GND 1000 +v1 Net-_D1-Pad1_ Net-_D3-Pad1_ sine + +.end diff --git a/Examples/bridgerectifier/bridgerectifier.cir.out b/Examples/bridgerectifier/bridgerectifier.cir.out new file mode 100644 index 00000000..c80f66e7 --- /dev/null +++ b/Examples/bridgerectifier/bridgerectifier.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 17 14:53:06 2015 + +.include D.lib +d1 net-_d1-pad1_ net-_d1-pad2_ D1N750 +d3 net-_d3-pad1_ net-_d1-pad2_ D1N750 +d4 gnd net-_d3-pad1_ D1N750 +d2 gnd net-_d1-pad1_ D1N750 +r1 net-_d1-pad2_ gnd 1000 +v1 net-_d1-pad1_ net-_d3-pad1_ sine(0 2 50 0 0) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/bridgerectifier/bridgerectifier.pro b/Examples/bridgerectifier/bridgerectifier.pro new file mode 100644 index 00000000..cc6e8092 --- /dev/null +++ b/Examples/bridgerectifier/bridgerectifier.pro @@ -0,0 +1,67 @@ +update=Tue Jun 16 17:18:14 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Sources diff --git a/Examples/bridgerectifier/bridgerectifier.proj b/Examples/bridgerectifier/bridgerectifier.proj new file mode 100644 index 00000000..4d1db028 --- /dev/null +++ b/Examples/bridgerectifier/bridgerectifier.proj @@ -0,0 +1 @@ +schematicFile bridgerectifier.sch
diff --git a/Examples/bridgerectifier/bridgerectifier.sch b/Examples/bridgerectifier/bridgerectifier.sch new file mode 100644 index 00000000..74e2aead --- /dev/null +++ b/Examples/bridgerectifier/bridgerectifier.sch @@ -0,0 +1,182 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:bridgerectifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L D D1 +U 1 1 557F721F +P 4000 3000 +F 0 "D1" H 4000 3100 50 0000 C CNN +F 1 "D" H 4000 2900 50 0000 C CNN +F 2 "" H 4000 3000 60 0000 C CNN +F 3 "" H 4000 3000 60 0000 C CNN + 1 4000 3000 + 0 -1 -1 0 +$EndComp +$Comp +L D D3 +U 1 1 557F72FE +P 4950 3000 +F 0 "D3" H 4950 3100 50 0000 C CNN +F 1 "D" H 4950 2900 50 0000 C CNN +F 2 "" H 4950 3000 60 0000 C CNN +F 3 "" H 4950 3000 60 0000 C CNN + 1 4950 3000 + 0 -1 -1 0 +$EndComp +$Comp +L D D4 +U 1 1 557F7345 +P 4950 4400 +F 0 "D4" H 4950 4500 50 0000 C CNN +F 1 "D" V 4950 4300 50 0000 C CNN +F 2 "" H 4950 4400 60 0000 C CNN +F 3 "" H 4950 4400 60 0000 C CNN + 1 4950 4400 + 0 -1 -1 0 +$EndComp +$Comp +L D D2 +U 1 1 557F745E +P 4000 4400 +F 0 "D2" H 4000 4500 50 0000 C CNN +F 1 "D" H 4000 4300 50 0000 C CNN +F 2 "" H 4000 4400 60 0000 C CNN +F 3 "" H 4000 4400 60 0000 C CNN + 1 4000 4400 + 0 -1 -1 0 +$EndComp +$Comp +L R R1 +U 1 1 557F76BB +P 5550 3600 +F 0 "R1" V 5630 3600 50 0000 C CNN +F 1 "1000" V 5550 3600 50 0000 C CNN +F 2 "" V 5480 3600 30 0000 C CNN +F 3 "" H 5550 3600 30 0000 C CNN + 1 5550 3600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 557F76F4 +P 5400 5300 +F 0 "#PWR01" H 5400 5050 50 0001 C CNN +F 1 "GND" H 5400 5150 50 0000 C CNN +F 2 "" H 5400 5300 60 0000 C CNN +F 3 "" H 5400 5300 60 0000 C CNN + 1 5400 5300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4000 2850 4000 2550 +Wire Wire Line + 4000 2550 5550 2550 +Wire Wire Line + 4950 2550 4950 2850 +Wire Wire Line + 5550 2550 5550 3450 +Connection ~ 4950 2550 +Wire Wire Line + 5550 4750 5550 3750 +Wire Wire Line + 4950 4750 4950 4550 +Wire Wire Line + 4000 4750 4000 4550 +Connection ~ 4950 4750 +Wire Wire Line + 4000 4750 5550 4750 +Connection ~ 5400 5300 +Connection ~ 5400 4750 +Wire Wire Line + 5400 4750 5400 5300 +Wire Wire Line + 4000 3150 4000 4250 +Wire Wire Line + 4950 3150 4950 4250 +Wire Wire Line + 4950 3750 3650 3750 +Wire Wire Line + 3650 3750 3650 4050 +Wire Wire Line + 3650 4050 3400 4050 +Connection ~ 4950 3750 +Wire Wire Line + 3400 3150 3800 3150 +Wire Wire Line + 3800 3150 3800 3400 +Wire Wire Line + 3800 3400 4000 3400 +Connection ~ 4000 3400 +$Comp +L PWR_FLAG #FLG02 +U 1 1 557F7E1A +P 5250 4400 +F 0 "#FLG02" H 5250 4495 50 0001 C CNN +F 1 "PWR_FLAG" H 5250 4580 50 0000 C CNN +F 2 "" H 5250 4400 60 0000 C CNN +F 3 "" H 5250 4400 60 0000 C CNN + 1 5250 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 4400 5250 4750 +Connection ~ 5250 4750 +$Comp +L sine v1 +U 1 1 557F7569 +P 3400 3600 +F 0 "v1" H 3200 3700 60 0000 C CNN +F 1 "sine" H 3200 3550 60 0000 C CNN +F 2 "R1" H 3100 3600 60 0000 C CNN +F 3 "" H 3400 3600 60 0000 C CNN + 1 3400 3600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/bridgerectifier/bridgerectifier_Previous_Values.xml b/Examples/bridgerectifier/bridgerectifier_Previous_Values.xml new file mode 100644 index 00000000..e3953650 --- /dev/null +++ b/Examples/bridgerectifier/bridgerectifier_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">2</field2><field3 name="Frequency">50</field3><field4 name="Delay Time">0</field4><field5 name="Damping Factor">0</field5></v1></source><model /><devicemodel><d4><field /></d4><d2><field /></d2><d3><field /></d3><d1><field /></d1><d4><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d1><d4><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d1><d4><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d1><d4><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d1><d4><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d1><d4><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d1><d4><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d1><d4><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d1><d4><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d1><d4><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/eSim-master-new/src/deviceModelLibrary/Diode/D.lib</field></d1><d4><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d1><d4><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d1><d4><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>/home/gaurav/workspace/eSim/src/deviceModelLibrary/Diode/D.lib</field></d1></devicemodel><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/bridgerectifier/plot_data_i.txt b/Examples/bridgerectifier/plot_data_i.txt new file mode 100644 index 00000000..1104d67e --- /dev/null +++ b/Examples/bridgerectifier/plot_data_i.txt @@ -0,0 +1,73 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 17 14:53:06 2015 +Transient Analysis Wed Jul 1 14:20:12 2015 +-------------------------------------------------------------------------------- +Index time alli +-------------------------------------------------------------------------------- +0 0.000000e+00 3.761582e-37 +1 1.000000e-05 -1.09955e-07 +2 2.000000e-05 -1.09956e-07 +3 4.000000e-05 -1.09960e-07 +4 8.000000e-05 -1.09972e-07 +5 1.600000e-04 -1.10024e-07 +6 3.200000e-04 -1.10229e-07 +7 6.400000e-04 -1.11097e-07 +8 1.280000e-03 -1.18621e-07 +9 2.560000e-03 -1.16150e-04 +10 3.917817e-03 -4.86647e-04 +11 5.283879e-03 -5.83395e-04 +12 6.862639e-03 -2.94367e-04 +13 8.646643e-03 9.417078e-08 +14 1.049092e-02 1.214997e-07 +15 1.227690e-02 4.107483e-05 +16 1.370034e-02 4.415757e-04 +17 1.520525e-02 5.866982e-04 +18 1.714494e-02 2.080447e-04 +19 1.914494e-02 -1.22187e-07 +20 2.059751e-02 -9.88610e-08 +21 2.207308e-02 -1.08983e-05 +22 2.354237e-02 -4.04707e-04 +23 2.489420e-02 -5.89792e-04 +24 2.689420e-02 -2.84824e-04 +25 2.889420e-02 9.962164e-08 +26 3.084968e-02 1.220034e-07 +27 3.284968e-02 2.062797e-04 +28 3.461295e-02 5.775662e-04 +29 3.636021e-02 4.274504e-04 +30 3.832771e-02 9.263736e-08 +31 4.032771e-02 -8.59359e-08 +32 4.232771e-02 -5.24974e-05 +33 4.383193e-02 -4.69735e-04 +34 4.541870e-02 -5.75001e-04 +35 4.741870e-02 -1.22335e-04 +36 4.941870e-02 9.011078e-08 +37 5.110569e-02 1.321927e-07 +38 5.275422e-02 1.764658e-04 +39 5.434500e-02 5.518961e-04 +40 5.597909e-02 5.050263e-04 +41 5.775008e-02 3.542701e-05 +42 5.975008e-02 -1.34645e-07 +43 6.153710e-02 -1.44896e-07 +44 6.328931e-02 -3.38310e-04 +45 6.528931e-02 -5.83243e-04 +46 6.728931e-02 -1.62681e-04 +47 6.928931e-02 1.879068e-07 +48 7.061999e-02 3.288734e-08 +49 7.190623e-02 2.643203e-06 +50 7.358268e-02 4.144726e-04 +51 7.518496e-02 5.878443e-04 +52 7.718496e-02 1.954071e-04 +53 7.918496e-02 -5.31062e-08 +54 8.118496e-02 -1.70279e-07 + +Index time alli +-------------------------------------------------------------------------------- +55 8.303657e-02 -2.64203e-04 +56 8.503657e-02 -5.90995e-04 +57 8.697843e-02 -2.59491e-04 +58 8.897843e-02 1.165010e-07 +59 9.097843e-02 1.054355e-07 +60 9.297843e-02 2.464709e-04 +61 9.497843e-02 5.908059e-04 +62 9.681511e-02 3.084229e-04 +63 9.881511e-02 -1.77852e-07 +64 1.000000e-01 -4.39906e-08 diff --git a/Examples/bridgerectifier/plot_data_v.txt b/Examples/bridgerectifier/plot_data_v.txt new file mode 100644 index 00000000..cf3951c6 --- /dev/null +++ b/Examples/bridgerectifier/plot_data_v.txt @@ -0,0 +1,73 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 17 14:53:06 2015 +Transient Analysis Wed Jul 1 14:20:12 2015 +-------------------------------------------------------------------------------- +Index time net-_d1-pad1_ net-_d1-pad2_ net-_d3-pad1_ +-------------------------------------------------------------------------------- +0 0.000000e+00 -6.30747e-22 -4.10932e-29 -6.30747e-22 +1 1.000000e-05 3.141587e-03 -5.74966e-16 -3.14159e-03 +2 2.000000e-05 6.283331e-03 3.745327e-07 -6.28296e-03 +3 4.000000e-05 1.256661e-02 1.136541e-06 -1.25655e-02 +4 8.000000e-05 2.513105e-02 1.906007e-06 -2.51291e-02 +5 1.600000e-04 5.024641e-02 4.186235e-06 -5.02422e-02 +6 3.200000e-04 1.003657e-01 8.039324e-06 -1.00358e-01 +7 6.400000e-04 1.997183e-01 1.666521e-05 -1.99702e-01 +8 1.280000e-03 3.913928e-01 3.830120e-05 -3.91355e-01 +9 2.560000e-03 7.783468e-01 1.160756e-01 -6.62271e-01 +10 3.917817e-03 1.186056e+00 4.865881e-01 -6.99468e-01 +11 5.283879e-03 1.287737e+00 5.834229e-01 -7.04314e-01 +12 6.862639e-03 9.808312e-01 2.944210e-01 -6.86410e-01 +13 8.646643e-03 4.124795e-01 8.133101e-06 -4.12471e-01 +14 1.049092e-02 -1.53629e-01 -2.39452e-05 1.536051e-01 +15 1.227690e-02 -6.35322e-01 4.105838e-02 6.763808e-01 +16 1.370034e-02 -6.97074e-01 4.414449e-01 1.138519e+00 +17 1.520525e-02 -7.04528e-01 5.867871e-01 1.291315e+00 +18 1.714494e-02 -6.77401e-01 2.080453e-01 8.854465e-01 +19 1.914494e-02 -2.65388e-01 3.703840e-05 2.654253e-01 +20 2.059751e-02 1.865897e-01 -4.37267e-05 -1.86633e-01 +21 2.207308e-02 6.116420e-01 1.088078e-02 -6.00761e-01 +22 2.354237e-02 1.099257e+00 4.045713e-01 -6.94685e-01 +23 2.489420e-02 1.294381e+00 5.898674e-01 -7.04514e-01 +24 2.689420e-02 9.705119e-01 2.848161e-01 -6.85696e-01 +25 2.889420e-02 3.404851e-01 6.504934e-05 -3.40420e-01 +26 3.084968e-02 -2.63811e-01 -7.14480e-05 2.637393e-01 +27 3.284968e-02 -6.77210e-01 2.063133e-01 8.835235e-01 +28 3.461295e-02 -7.03898e-01 5.774359e-01 1.281334e+00 +29 3.636021e-02 -6.96270e-01 4.276179e-01 1.123888e+00 +30 3.832771e-02 -5.01492e-01 7.369949e-05 5.015652e-01 +31 4.032771e-02 1.028330e-01 1.215185e-04 -1.02712e-01 +32 4.232771e-02 6.939657e-01 5.229666e-02 -6.41669e-01 +33 4.383193e-02 1.168319e+00 4.697936e-01 -6.98525e-01 +34 4.541870e-02 1.278818e+00 5.749139e-01 -7.03904e-01 +35 4.741870e-02 7.861999e-01 1.225298e-01 -6.63670e-01 +36 4.941870e-02 1.815468e-01 -1.22632e-04 -1.81669e-01 +37 5.110569e-02 -3.40352e-01 1.369380e-04 3.404886e-01 +38 5.275422e-02 -6.73115e-01 1.763036e-01 8.494190e-01 +39 5.434500e-02 -7.02929e-01 5.519480e-01 1.254877e+00 +40 5.597909e-02 -7.00572e-01 5.049867e-01 1.205559e+00 +41 5.775008e-02 -6.31627e-01 3.560316e-02 6.672302e-01 +42 5.975008e-02 -7.85057e-02 -1.44179e-04 7.836157e-02 +43 6.153710e-02 4.644607e-01 2.339281e-04 -4.64227e-01 +44 6.328931e-02 1.028060e+00 3.380667e-01 -6.89994e-01 +45 6.528931e-02 1.287588e+00 5.834319e-01 -7.04157e-01 +46 6.728931e-02 8.336234e-01 1.625897e-01 -6.71034e-01 +47 6.928931e-02 2.214529e-01 6.455847e-05 -2.21388e-01 +48 7.061999e-02 -1.93579e-01 -6.68753e-05 1.935121e-01 +49 7.190623e-02 -5.62412e-01 2.581019e-03 5.649928e-01 +50 7.358268e-02 -6.95306e-01 4.143838e-01 1.109689e+00 +51 7.518496e-02 -7.04369e-01 5.878861e-01 1.292255e+00 +52 7.718496e-02 -6.75788e-01 1.954555e-01 8.712440e-01 +53 7.918496e-02 -2.53234e-01 5.859887e-05 2.532926e-01 +54 8.118496e-02 3.637039e-01 -4.74738e-05 -3.63751e-01 + +Index time net-_d1-pad1_ net-_d1-pad2_ net-_d3-pad1_ +-------------------------------------------------------------------------------- +55 8.303657e-02 9.478479e-01 2.642635e-01 -6.83584e-01 +56 8.503657e-02 1.295365e+00 5.908612e-01 -7.04503e-01 +57 8.697843e-02 9.428324e-01 2.597018e-01 -6.83131e-01 +58 8.897843e-02 3.153700e-01 -1.69418e-04 -3.15539e-01 +59 9.097843e-02 -3.02481e-01 1.684733e-04 3.026493e-01 +60 9.297843e-02 -6.81891e-01 2.462494e-01 9.281400e-01 +61 9.497843e-02 -7.04502e-01 5.909495e-01 1.295452e+00 +62 9.681511e-02 -6.87601e-01 3.083478e-01 9.959484e-01 +63 9.881511e-02 -3.63679e-01 5.335145e-05 3.637328e-01 +64 1.000000e-01 -4.17455e-05 -8.34857e-05 -4.17455e-05 diff --git a/Examples/rc/analysis b/Examples/rc/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/rc/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/rc/plot_data_i.txt b/Examples/rc/plot_data_i.txt new file mode 100644 index 00000000..dc758804 --- /dev/null +++ b/Examples/rc/plot_data_i.txt @@ -0,0 +1,71 @@ +* eeschema netlist version 1.1 (spice format) creation date: thu jun 11 10:11:01 2015 +Transient Analysis Thu Jun 11 10:14:02 2015 +-------------------------------------------------------------------------------- +Index time alli +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 +1 1.000000e-05 -6.22097e-06 +2 1.084561e-05 -6.74657e-06 +3 1.253682e-05 -7.79688e-06 +4 1.591924e-05 -9.89218e-06 +5 2.268408e-05 -1.40616e-05 +6 3.621377e-05 -2.23161e-05 +7 6.327316e-05 -3.84931e-05 +8 1.173919e-04 -6.95590e-05 +9 2.256294e-04 -1.26836e-04 +10 4.421045e-04 -2.24094e-04 +11 8.750546e-04 -3.63022e-04 +12 1.561534e-03 -4.74794e-04 +13 2.607354e-03 -4.89430e-04 +14 4.103506e-03 -3.33740e-04 +15 6.103506e-03 2.009336e-05 +16 8.103506e-03 3.793351e-04 +17 1.010351e-02 5.936837e-04 +18 1.210351e-02 5.812653e-04 +19 1.410351e-02 3.468234e-04 +20 1.610351e-02 -2.00934e-05 +21 1.810351e-02 -3.79335e-04 +22 2.010351e-02 -5.93684e-04 +23 2.210351e-02 -5.81265e-04 +24 2.410351e-02 -3.46823e-04 +25 2.610351e-02 2.009336e-05 +26 2.810351e-02 3.793351e-04 +27 3.010351e-02 5.936837e-04 +28 3.210351e-02 5.812653e-04 +29 3.410351e-02 3.468234e-04 +30 3.610351e-02 -2.00934e-05 +31 3.810351e-02 -3.79335e-04 +32 4.010351e-02 -5.93684e-04 +33 4.210351e-02 -5.81265e-04 +34 4.410351e-02 -3.46823e-04 +35 4.610351e-02 2.009336e-05 +36 4.810351e-02 3.793351e-04 +37 5.010351e-02 5.936837e-04 +38 5.210351e-02 5.812653e-04 +39 5.410351e-02 3.468234e-04 +40 5.610351e-02 -2.00934e-05 +41 5.810351e-02 -3.79335e-04 +42 6.010351e-02 -5.93684e-04 +43 6.210351e-02 -5.81265e-04 +44 6.410351e-02 -3.46823e-04 +45 6.610351e-02 2.009336e-05 +46 6.810351e-02 3.793351e-04 +47 7.010351e-02 5.936837e-04 +48 7.210351e-02 5.812653e-04 +49 7.410351e-02 3.468234e-04 +50 7.610351e-02 -2.00934e-05 +51 7.810351e-02 -3.79335e-04 +52 8.010351e-02 -5.93684e-04 +53 8.210351e-02 -5.81265e-04 +54 8.410351e-02 -3.46823e-04 + +Index time alli +-------------------------------------------------------------------------------- +55 8.610351e-02 2.009336e-05 +56 8.810351e-02 3.793351e-04 +57 9.010351e-02 5.936837e-04 +58 9.210351e-02 5.812653e-04 +59 9.410351e-02 3.468234e-04 +60 9.610351e-02 -2.00934e-05 +61 9.810351e-02 -3.79335e-04 +62 1.000000e-01 -5.86156e-04 diff --git a/Examples/rc/plot_data_v.txt b/Examples/rc/plot_data_v.txt new file mode 100644 index 00000000..1523c7e7 --- /dev/null +++ b/Examples/rc/plot_data_v.txt @@ -0,0 +1,71 @@ +* eeschema netlist version 1.1 (spice format) creation date: thu jun 11 10:11:01 2015 +Transient Analysis Thu Jun 11 10:14:02 2015 +-------------------------------------------------------------------------------- +Index time V(1) V(4) +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-05 6.220965e-05 6.283175e-03 +2 1.084561e-05 6.791459e-05 6.814482e-03 +3 1.253682e-05 8.021261e-05 7.877094e-03 +4 1.591924e-05 1.101286e-04 1.000231e-02 +5 2.268408e-05 1.911502e-04 1.425271e-02 +6 3.621377e-05 4.372392e-04 2.275329e-02 +7 6.327316e-05 1.259968e-03 3.975308e-02 +8 1.173919e-04 4.183792e-03 7.374280e-02 +9 2.256294e-04 1.481245e-02 1.416485e-01 +10 4.421045e-04 5.279624e-02 2.768902e-01 +11 8.750546e-04 1.798921e-01 5.429139e-01 +12 1.561534e-03 4.674640e-01 9.422583e-01 +13 2.607354e-03 9.716663e-01 1.461096e+00 +14 4.103506e-03 1.587461e+00 1.921201e+00 +15 6.103506e-03 1.901107e+00 1.881014e+00 +16 8.103506e-03 1.501679e+00 1.122344e+00 +17 1.010351e-02 5.286602e-01 -6.50235e-02 +18 1.210351e-02 -6.46289e-01 -1.22755e+00 +19 1.410351e-02 -1.57438e+00 -1.92120e+00 +20 1.610351e-02 -1.90111e+00 -1.88101e+00 +21 1.810351e-02 -1.50168e+00 -1.12234e+00 +22 2.010351e-02 -5.28660e-01 6.502348e-02 +23 2.210351e-02 6.462888e-01 1.227554e+00 +24 2.410351e-02 1.574377e+00 1.921201e+00 +25 2.610351e-02 1.901107e+00 1.881014e+00 +26 2.810351e-02 1.501679e+00 1.122344e+00 +27 3.010351e-02 5.286602e-01 -6.50235e-02 +28 3.210351e-02 -6.46289e-01 -1.22755e+00 +29 3.410351e-02 -1.57438e+00 -1.92120e+00 +30 3.610351e-02 -1.90111e+00 -1.88101e+00 +31 3.810351e-02 -1.50168e+00 -1.12234e+00 +32 4.010351e-02 -5.28660e-01 6.502348e-02 +33 4.210351e-02 6.462888e-01 1.227554e+00 +34 4.410351e-02 1.574377e+00 1.921201e+00 +35 4.610351e-02 1.901107e+00 1.881014e+00 +36 4.810351e-02 1.501679e+00 1.122344e+00 +37 5.010351e-02 5.286602e-01 -6.50235e-02 +38 5.210351e-02 -6.46289e-01 -1.22755e+00 +39 5.410351e-02 -1.57438e+00 -1.92120e+00 +40 5.610351e-02 -1.90111e+00 -1.88101e+00 +41 5.810351e-02 -1.50168e+00 -1.12234e+00 +42 6.010351e-02 -5.28660e-01 6.502348e-02 +43 6.210351e-02 6.462888e-01 1.227554e+00 +44 6.410351e-02 1.574377e+00 1.921201e+00 +45 6.610351e-02 1.901107e+00 1.881014e+00 +46 6.810351e-02 1.501679e+00 1.122344e+00 +47 7.010351e-02 5.286602e-01 -6.50235e-02 +48 7.210351e-02 -6.46289e-01 -1.22755e+00 +49 7.410351e-02 -1.57438e+00 -1.92120e+00 +50 7.610351e-02 -1.90111e+00 -1.88101e+00 +51 7.810351e-02 -1.50168e+00 -1.12234e+00 +52 8.010351e-02 -5.28660e-01 6.502348e-02 +53 8.210351e-02 6.462888e-01 1.227554e+00 +54 8.410351e-02 1.574377e+00 1.921201e+00 + +Index time V(1) V(4) +-------------------------------------------------------------------------------- +55 8.610351e-02 1.901107e+00 1.881014e+00 +56 8.810351e-02 1.501679e+00 1.122344e+00 +57 9.010351e-02 5.286602e-01 -6.50235e-02 +58 9.210351e-02 -6.46289e-01 -1.22755e+00 +59 9.410351e-02 -1.57438e+00 -1.92120e+00 +60 9.610351e-02 -1.90111e+00 -1.88101e+00 +61 9.810351e-02 -1.50168e+00 -1.12234e+00 +62 1.000000e-01 -5.86156e-01 -2.44929e-15 diff --git a/Examples/rc/rc-cache.lib b/Examples/rc/rc-cache.lib new file mode 100644 index 00000000..35095f47 --- /dev/null +++ b/Examples/rc/rc-cache.lib @@ -0,0 +1,89 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/rc/rc.bak b/Examples/rc/rc.bak new file mode 100644 index 00000000..be41e011 --- /dev/null +++ b/Examples/rc/rc.bak @@ -0,0 +1,131 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:rc-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 556C372A +P 5100 2300 +F 0 "R1" V 5180 2300 50 0000 C CNN +F 1 "1k" V 5100 2300 50 0000 C CNN +F 2 "" V 5030 2300 30 0000 C CNN +F 3 "" H 5100 2300 30 0000 C CNN + 1 5100 2300 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 556C3744 +P 5600 2650 +F 0 "C1" H 5625 2750 50 0000 L CNN +F 1 "1u" H 5625 2550 50 0000 L CNN +F 2 "" H 5638 2500 30 0000 C CNN +F 3 "" H 5600 2650 60 0000 C CNN + 1 5600 2650 + 1 0 0 -1 +$EndComp +$Comp +L sine v1 +U 1 1 556C37C5 +P 4650 2850 +F 0 "v1" H 4450 2950 60 0000 C CNN +F 1 "sine" H 4450 2800 60 0000 C CNN +F 2 "R1" H 4350 2850 60 0000 C CNN +F 3 "" H 4650 2850 60 0000 C CNN + 1 4650 2850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 556C3835 +P 5150 3400 +F 0 "#PWR01" H 5150 3150 50 0001 C CNN +F 1 "GND" H 5150 3250 50 0000 C CNN +F 2 "" H 5150 3400 60 0000 C CNN +F 3 "" H 5150 3400 60 0000 C CNN + 1 5150 3400 + 1 0 0 -1 +$EndComp +Text GLabel 5050 3400 0 60 Input ~ 0 +gnd +Wire Wire Line + 4650 2400 4650 2300 +Wire Wire Line + 4650 2300 4950 2300 +Wire Wire Line + 5250 2300 5600 2300 +Wire Wire Line + 5600 2800 5600 3300 +Wire Wire Line + 5600 3300 4650 3300 +Wire Wire Line + 5150 3400 5150 3300 +Connection ~ 5150 3300 +Wire Wire Line + 5050 3400 5100 3400 +Wire Wire Line + 5100 3400 5100 3350 +Wire Wire Line + 5100 3350 5150 3350 +Connection ~ 5150 3350 +Wire Wire Line + 5600 2300 5600 2500 +$Comp +L PWR_FLAG #FLG02 +U 1 1 55795DBE +P 5150 3300 +F 0 "#FLG02" H 5150 3395 50 0001 C CNN +F 1 "PWR_FLAG" H 5150 3480 50 0000 C CNN +F 2 "" H 5150 3300 60 0000 C CNN +F 3 "" H 5150 3300 60 0000 C CNN + 1 5150 3300 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/rc/rc.cir b/Examples/rc/rc.cir new file mode 100644 index 00000000..1e5ca11e --- /dev/null +++ b/Examples/rc/rc.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jun 11 10:11:01 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R1 1 4 1k +C1 1 2 1u +v1 4 2 sine + +.end diff --git a/Examples/rc/rc.cir.out b/Examples/rc/rc.cir.out new file mode 100644 index 00000000..282ac877 --- /dev/null +++ b/Examples/rc/rc.cir.out @@ -0,0 +1,14 @@ +* eeschema netlist version 1.1 (spice format) creation date: thu jun 11 10:11:01 2015 + +r1 1 4 1k +c1 1 0 1u +v1 4 0 sine(0 2 50 0 0) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/rc/rc.pro b/Examples/rc/rc.pro new file mode 100644 index 00000000..f1f5e0ac --- /dev/null +++ b/Examples/rc/rc.pro @@ -0,0 +1,68 @@ +update=Wed Jun 3 15:51:38 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources diff --git a/Examples/rc/rc.proj b/Examples/rc/rc.proj new file mode 100644 index 00000000..c3d616a5 --- /dev/null +++ b/Examples/rc/rc.proj @@ -0,0 +1 @@ +schematicFile rc.sch diff --git a/Examples/rc/rc.sch b/Examples/rc/rc.sch new file mode 100644 index 00000000..7fa7a6d4 --- /dev/null +++ b/Examples/rc/rc.sch @@ -0,0 +1,131 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:rc-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 556C372A +P 5100 2300 +F 0 "R1" V 5180 2300 50 0000 C CNN +F 1 "1k" V 5100 2300 50 0000 C CNN +F 2 "" V 5030 2300 30 0000 C CNN +F 3 "" H 5100 2300 30 0000 C CNN + 1 5100 2300 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 556C3744 +P 5600 2650 +F 0 "C1" H 5625 2750 50 0000 L CNN +F 1 "1u" H 5625 2550 50 0000 L CNN +F 2 "" H 5638 2500 30 0000 C CNN +F 3 "" H 5600 2650 60 0000 C CNN + 1 5600 2650 + 1 0 0 -1 +$EndComp +$Comp +L sine v1 +U 1 1 556C37C5 +P 4650 2850 +F 0 "v1" H 4450 2950 60 0000 C CNN +F 1 "sine" H 4450 2800 60 0000 C CNN +F 2 "R1" H 4350 2850 60 0000 C CNN +F 3 "" H 4650 2850 60 0000 C CNN + 1 4650 2850 + 1 0 0 -1 +$EndComp +Text GLabel 5050 3400 0 60 Input ~ 0 +gnd +Wire Wire Line + 4650 2400 4650 2300 +Wire Wire Line + 4650 2300 4950 2300 +Wire Wire Line + 5250 2300 5600 2300 +Wire Wire Line + 5600 2800 5600 3300 +Wire Wire Line + 5600 3300 4650 3300 +Connection ~ 5150 3300 +Wire Wire Line + 5050 3400 5100 3400 +Wire Wire Line + 5100 3400 5100 3350 +Wire Wire Line + 5100 3350 5150 3350 +Connection ~ 5150 3350 +Wire Wire Line + 5600 2300 5600 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 55795DBE +P 5150 3300 +F 0 "#FLG01" H 5150 3395 50 0001 C CNN +F 1 "PWR_FLAG" H 5150 3480 50 0000 C CNN +F 2 "" H 5150 3300 60 0000 C CNN +F 3 "" H 5150 3300 60 0000 C CNN + 1 5150 3300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR? +U 1 1 55796439 +P 5150 3400 +F 0 "#PWR?" H 5150 3400 30 0001 C CNN +F 1 "GND" H 5150 3330 30 0001 C CNN +F 2 "" H 5150 3400 60 0000 C CNN +F 3 "" H 5150 3400 60 0000 C CNN + 1 5150 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 3300 5150 3400 +$EndSCHEMATC |