SN74LS76 as a Dual J-K Flip-Flops with Clear and Preset

8 files changed, 655 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/SN74LS76/SN74LS76-cache.lib b/library/SubcircuitLibrary/SN74LS76/SN74LS76-cache.lib
new file mode 100644
index 00000000..231ae378
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS76/SN74LS76-cache.lib
@@ -0,0 +1,114 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS76/SN74LS76.cir b/library/SubcircuitLibrary/SN74LS76/SN74LS76.cir
new file mode 100644
index 00000000..ddcfb1b9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS76/SN74LS76.cir
@@ -0,0 +1,21 @@
+* C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS76\SN74LS76.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/10/25 06:29:32
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X2  Net-_U1-Pad6_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U2-Pad2_ 3_and		
+X3  Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_U2-Pad1_ 3_and		
+X4  Net-_U1-Pad1_ Net-_U4-Pad2_ Net-_U1-Pad2_ Net-_U5-Pad1_ 3_and		
+X5  Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U5-Pad2_ 3_and		
+X1  Net-_U1-Pad5_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad1_ 4_and		
+U3  Net-_U3-Pad1_ Net-_U3-Pad2_ d_inverter		
+X6  Net-_U1-Pad4_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad1_ Net-_U4-Pad1_ 4_and		
+U4  Net-_U4-Pad1_ Net-_U4-Pad2_ d_inverter		
+U5  Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U1-Pad5_ d_nor		
+U2  Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad1_ d_nor		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS76/SN74LS76.cir.out b/library/SubcircuitLibrary/SN74LS76/SN74LS76.cir.out
new file mode 100644
index 00000000..cb94902c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS76/SN74LS76.cir.out
@@ -0,0 +1,36 @@
+* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\sn74ls76\sn74ls76.cir
+
+.include 3_and.sub
+.include 4_and.sub
+x2 net-_u1-pad6_ net-_u3-pad2_ net-_u1-pad5_ net-_u2-pad2_ 3_and
+x3 net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad6_ net-_u2-pad1_ 3_and
+x4 net-_u1-pad1_ net-_u4-pad2_ net-_u1-pad2_ net-_u5-pad1_ 3_and
+x5 net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u5-pad2_ 3_and
+x1 net-_u1-pad5_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad1_ 4_and
+* u3  net-_u3-pad1_ net-_u3-pad2_ d_inverter
+x6 net-_u1-pad4_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad1_ net-_u4-pad1_ 4_and
+* u4  net-_u4-pad1_ net-_u4-pad2_ d_inverter
+* u5  net-_u5-pad1_ net-_u5-pad2_ net-_u1-pad5_ d_nor
+* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_nor
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+a1 net-_u3-pad1_ net-_u3-pad2_ u3
+a2 net-_u4-pad1_ net-_u4-pad2_ u4
+a3 [net-_u5-pad1_ net-_u5-pad2_ ] net-_u1-pad5_ u5
+a4 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u2 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS76/SN74LS76.pro b/library/SubcircuitLibrary/SN74LS76/SN74LS76.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS76/SN74LS76.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LS76/SN74LS76.sch b/library/SubcircuitLibrary/SN74LS76/SN74LS76.sch
new file mode 100644
index 00000000..3ff063bc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS76/SN74LS76.sch
@@ -0,0 +1,379 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
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+EELAYER END
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+F 0 "U1" H 9800 5250 30  0000 C CNN
+F 1 "PORT" H 9750 5150 30  0000 C CNN
+F 2 "" H 9750 5150 60  0000 C CNN
+F 3 "" H 9750 5150 60  0000 C CNN
+	7    9750 5150
+	-1   0    0    1   
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS76/SN74LS76.sub b/library/SubcircuitLibrary/SN74LS76/SN74LS76.sub
new file mode 100644
index 00000000..8e8b56c3
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS76/SN74LS76.sub
@@ -0,0 +1,30 @@
+* Subcircuit SN74LS76
+.subckt SN74LS76 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 
+* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\sn74ls76\sn74ls76.cir
+.include 3_and.sub
+.include 4_and.sub
+x2 net-_u1-pad6_ net-_u3-pad2_ net-_u1-pad5_ net-_u2-pad2_ 3_and
+x3 net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad6_ net-_u2-pad1_ 3_and
+x4 net-_u1-pad1_ net-_u4-pad2_ net-_u1-pad2_ net-_u5-pad1_ 3_and
+x5 net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u5-pad2_ 3_and
+x1 net-_u1-pad5_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad1_ 4_and
+* u3  net-_u3-pad1_ net-_u3-pad2_ d_inverter
+x6 net-_u1-pad4_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad1_ net-_u4-pad1_ 4_and
+* u4  net-_u4-pad1_ net-_u4-pad2_ d_inverter
+* u5  net-_u5-pad1_ net-_u5-pad2_ net-_u1-pad5_ d_nor
+* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_nor
+a1 net-_u3-pad1_ net-_u3-pad2_ u3
+a2 net-_u4-pad1_ net-_u4-pad2_ u4
+a3 [net-_u5-pad1_ net-_u5-pad2_ ] net-_u1-pad5_ u5
+a4 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u2 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74LS76
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS76/SN74LS76_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS76/SN74LS76_Previous_Values.xml
new file mode 100644
index 00000000..55b723c5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS76/SN74LS76_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_nor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x4><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x1><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x1><x6><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS76/analysis b/library/SubcircuitLibrary/SN74LS76/analysis
new file mode 100644
index 00000000..e17ad61d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS76/analysis
@@ -0,0 +1 @@
+.tran 0.001e-00 8e-00 0e-00
\ No newline at end of file