Add CD4066B quad bilateral switch subcircuit

10 files changed, 724 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B-cache.lib b/library/SubcircuitLibrary/CD4066B/CD4066B-cache.lib
new file mode 100644
index 00000000..ae0c7685
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4066B/CD4066B-cache.lib
@@ -0,0 +1,168 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 P
+X ~ 2 250 0 100 L 30 30 2 1 P
+X ~ 3 250 0 100 L 30 30 3 1 P
+X ~ 4 250 0 100 L 30 30 4 1 P
+X ~ 5 250 0 100 L 30 30 5 1 P
+X ~ 6 250 0 100 L 30 30 6 1 P
+X ~ 7 250 0 100 L 30 30 7 1 P
+X ~ 8 250 0 100 L 30 30 8 1 P
+X ~ 9 250 0 100 L 30 30 9 1 P
+X ~ 10 250 0 100 L 30 30 10 1 P
+X ~ 11 250 0 100 L 30 30 11 1 P
+X ~ 12 250 0 100 L 30 30 12 1 P
+X ~ 13 250 0 100 L 30 30 13 1 P
+X ~ 14 250 0 100 L 30 30 14 1 P
+X ~ 15 250 0 100 L 30 30 15 1 P
+X ~ 16 250 0 100 L 30 30 16 1 P
+X ~ 17 250 0 100 L 30 30 17 1 P
+X ~ 18 250 0 100 L 30 30 18 1 P
+X ~ 19 250 0 100 L 30 30 19 1 P
+X ~ 20 250 0 100 L 30 30 20 1 P
+X ~ 21 250 0 100 L 30 30 21 1 P
+X ~ 22 250 0 100 L 30 30 22 1 P
+X ~ 23 250 0 100 L 30 30 23 1 P
+X ~ 24 250 0 100 L 30 30 24 1 P
+X ~ 25 250 0 100 L 30 30 25 1 P
+X ~ 26 250 0 100 L 30 30 26 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B.cir b/library/SubcircuitLibrary/CD4066B/CD4066B.cir
new file mode 100644
index 00000000..9e2c34d0
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4066B/CD4066B.cir
@@ -0,0 +1,22 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4066B\CD4066B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/09/25 14:21:31
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3  Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter		
+U4  Net-_U3-Pad2_ Net-_U4-Pad2_ d_inverter		
+U7  Net-_U4-Pad2_ Net-_U6-Pad1_ d_inverter		
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ ? eSim_MOS_P		
+M3  Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ ? eSim_MOS_N		
+M2  Net-_M1-Pad3_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_N		
+M4  Net-_M4-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad1_ ? eSim_MOS_P		
+M5  Net-_M4-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad1_ Net-_M1-Pad3_ eSim_MOS_N		
+U2  Net-_U1-Pad1_ Net-_U2-Pad2_ adc_bridge_1		
+U6  Net-_U6-Pad1_ Net-_M1-Pad2_ dac_bridge_1		
+U5  Net-_U4-Pad2_ Net-_M3-Pad2_ dac_bridge_1		
+U1  Net-_U1-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M4-Pad1_ GND PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B.cir.out b/library/SubcircuitLibrary/CD4066B/CD4066B.cir.out
new file mode 100644
index 00000000..c304a2c8
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4066B/CD4066B.cir.out
@@ -0,0 +1,43 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd4066b\cd4066b.cir
+
+.include NMOS-0.5um.lib
+.include PMOS-0.5um.lib
+* u3  net-_u2-pad2_ net-_u3-pad2_ d_inverter
+* u4  net-_u3-pad2_ net-_u4-pad2_ d_inverter
+* u7  net-_u4-pad2_ net-_u6-pad1_ d_inverter
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ ? mos_p W=100u L=5u M=1
+m3 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ ? mos_n W=100u L=5u M=1
+m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_n W=100u L=5u M=1
+m4 net-_m4-pad1_ net-_m1-pad2_ net-_m1-pad1_ ? mos_p W=100u L=5u M=1
+m5 net-_m4-pad1_ net-_m3-pad2_ net-_m1-pad1_ net-_m1-pad3_ mos_n W=100u L=5u M=1
+* u2  net-_u1-pad1_ net-_u2-pad2_ adc_bridge_1
+* u6  net-_u6-pad1_ net-_m1-pad2_ dac_bridge_1
+* u5  net-_u4-pad2_ net-_m3-pad2_ dac_bridge_1
+* u1  net-_u1-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m4-pad1_ gnd port
+a1 net-_u2-pad2_ net-_u3-pad2_ u3
+a2 net-_u3-pad2_ net-_u4-pad2_ u4
+a3 net-_u4-pad2_ net-_u6-pad1_ u7
+a4 [net-_u1-pad1_ ] [net-_u2-pad2_ ] u2
+a5 [net-_u6-pad1_ ] [net-_m1-pad2_ ] u6
+a6 [net-_u4-pad2_ ] [net-_m3-pad2_ ] u5
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u6 dac_bridge(out_low= 0 out_high= 5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u5 dac_bridge(out_low= 0 out_high= 5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B.pro b/library/SubcircuitLibrary/CD4066B/CD4066B.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4066B/CD4066B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B.sch b/library/SubcircuitLibrary/CD4066B/CD4066B.sch
new file mode 100644
index 00000000..d91e6739
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4066B/CD4066B.sch
@@ -0,0 +1,367 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4066B-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U3
+U 1 1 681D78A2
+P 3600 4450
+F 0 "U3" H 3600 4350 60  0000 C CNN
+F 1 "d_inverter" H 3600 4600 60  0000 C CNN
+F 2 "" H 3650 4400 60  0000 C CNN
+F 3 "" H 3650 4400 60  0000 C CNN
+	1    3600 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 681D78A3
+P 4400 4450
+F 0 "U4" H 4400 4350 60  0000 C CNN
+F 1 "d_inverter" H 4400 4600 60  0000 C CNN
+F 2 "" H 4450 4400 60  0000 C CNN
+F 3 "" H 4450 4400 60  0000 C CNN
+	1    4400 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 681D78A4
+P 5325 4450
+F 0 "U7" H 5325 4350 60  0000 C CNN
+F 1 "d_inverter" H 5325 4600 60  0000 C CNN
+F 2 "" H 5375 4400 60  0000 C CNN
+F 3 "" H 5375 4400 60  0000 C CNN
+	1    5325 4450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3900 4450 4100 4450
+Wire Wire Line
+	4700 4450 5025 4450
+$Comp
+L eSim_MOS_P M1
+U 1 1 681D78A5
+P 6200 3800
+F 0 "M1" H 6150 3850 50  0000 R CNN
+F 1 "eSim_MOS_P" H 6250 3950 50  0000 R CNN
+F 2 "" H 6450 3900 29  0000 C CNN
+F 3 "" H 6250 3800 60  0000 C CNN
+	1    6200 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M3
+U 1 1 681D78A6
+P 7375 3600
+F 0 "M3" H 7375 3450 50  0000 R CNN
+F 1 "eSim_MOS_N" H 7475 3550 50  0000 R CNN
+F 2 "" H 7675 3300 29  0000 C CNN
+F 3 "" H 7475 3400 60  0000 C CNN
+	1    7375 3600
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
+	6350 4000 6350 4150
+Wire Wire Line
+	7175 4150 7175 4000
+Wire Wire Line
+	6350 4150 7175 4150
+$Comp
+L eSim_MOS_N M2
+U 1 1 681D78A7
+P 6525 4525
+F 0 "M2" H 6525 4375 50  0000 R CNN
+F 1 "eSim_MOS_N" H 6625 4475 50  0000 R CNN
+F 2 "" H 6825 4225 29  0000 C CNN
+F 3 "" H 6625 4325 60  0000 C CNN
+	1    6525 4525
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6725 4925 6725 5200
+Wire Wire Line
+	6725 4975 6825 4975
+Wire Wire Line
+	6825 4975 6825 4875
+Connection ~ 6725 4975
+Wire Wire Line
+	6725 4150 6725 4525
+Connection ~ 6725 4150
+Wire Wire Line
+	5725 4725 6425 4725
+Wire Wire Line
+	5725 2875 5725 4725
+Wire Wire Line
+	6050 3800 5725 3800
+Connection ~ 5725 3800
+Wire Wire Line
+	6350 3600 6350 3450
+Wire Wire Line
+	6350 3450 7175 3450
+Wire Wire Line
+	7175 3450 7175 3600
+$Comp
+L eSim_MOS_P M4
+U 1 1 681D78A8
+P 8425 3475
+F 0 "M4" H 8375 3525 50  0000 R CNN
+F 1 "eSim_MOS_P" H 8475 3625 50  0000 R CNN
+F 2 "" H 8675 3575 29  0000 C CNN
+F 3 "" H 8475 3475 60  0000 C CNN
+	1    8425 3475
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_MOS_N M5
+U 1 1 681D78A9
+P 8625 4325
+F 0 "M5" H 8625 4175 50  0000 R CNN
+F 1 "eSim_MOS_N" H 8725 4275 50  0000 R CNN
+F 2 "" H 8925 4025 29  0000 C CNN
+F 3 "" H 8725 4125 60  0000 C CNN
+	1    8625 4325
+	0    1    -1   0   
+$EndComp
+Wire Wire Line
+	8100 3625 8225 3625
+Wire Wire Line
+	8100 3625 8100 4125
+Wire Wire Line
+	8100 4125 8225 4125
+Wire Wire Line
+	7675 4025 8275 4025
+Wire Wire Line
+	8175 3725 8275 3725
+Wire Wire Line
+	8625 3625 8700 3625
+Wire Wire Line
+	8700 3625 8700 4125
+Wire Wire Line
+	8700 4125 8625 4125
+Wire Wire Line
+	7675 4025 7675 4400
+Wire Wire Line
+	7675 4400 6725 4400
+Connection ~ 6725 4400
+Wire Wire Line
+	5725 2875 8425 2875
+Wire Wire Line
+	8425 2875 8425 3325
+Wire Wire Line
+	8425 5700 8425 4425
+Connection ~ 4850 4450
+Wire Wire Line
+	4850 5700 8425 5700
+Wire Wire Line
+	7475 3800 7475 5700
+Connection ~ 7475 5700
+Connection ~ 8700 3925
+Connection ~ 5725 4450
+Wire Wire Line
+	6775 2350 6775 3450
+Connection ~ 6775 3450
+Wire Wire Line
+	6775 3075 7850 3075
+Wire Wire Line
+	7850 3075 7850 3850
+Wire Wire Line
+	7850 3850 8100 3850
+Connection ~ 8100 3850
+Connection ~ 6775 3075
+Wire Wire Line
+	3300 4450 3150 4450
+Wire Wire Line
+	5675 3950 5675 4450
+Wire Wire Line
+	5675 4450 5725 4450
+Wire Wire Line
+	5375 3950 5675 3950
+Wire Wire Line
+	3150 4450 3150 4475
+$Comp
+L adc_bridge_1 U2
+U 1 1 681D78B2
+P 2600 4525
+F 0 "U2" H 2600 4525 60  0000 C CNN
+F 1 "adc_bridge_1" H 2600 4675 60  0000 C CNN
+F 2 "" H 2600 4525 60  0000 C CNN
+F 3 "" H 2600 4525 60  0000 C CNN
+	1    2600 4525
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5375 3875 5375 3950
+Wire Wire Line
+	5625 4450 5625 4100
+Wire Wire Line
+	5625 4100 4225 4100
+Wire Wire Line
+	4225 4100 4225 3875
+Wire Wire Line
+	4850 4450 4850 4500
+Wire Wire Line
+	4850 5700 4850 5650
+$Comp
+L dac_bridge_1 U6
+U 1 1 681D78B5
+P 4825 3925
+F 0 "U6" H 4825 3925 60  0000 C CNN
+F 1 "dac_bridge_1" H 4825 4075 60  0000 C CNN
+F 2 "" H 4825 3925 60  0000 C CNN
+F 3 "" H 4825 3925 60  0000 C CNN
+	1    4825 3925
+	1    0    0    -1  
+$EndComp
+$Comp
+L dac_bridge_1 U5
+U 1 1 681D78B6
+P 4800 5100
+F 0 "U5" H 4800 5100 60  0000 C CNN
+F 1 "dac_bridge_1" H 4800 5250 60  0000 C CNN
+F 2 "" H 4800 5100 60  0000 C CNN
+F 3 "" H 4800 5100 60  0000 C CNN
+	1    4800 5100
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	8700 3925 9675 3925
+Wire Wire Line
+	6775 2350 5900 2350
+Wire Wire Line
+	2000 4475 1775 4475
+$Comp
+L PORT U1
+U 2 1 681D7CCF
+P 5650 2350
+F 0 "U1" H 5700 2450 30  0000 C CNN
+F 1 "PORT" H 5650 2350 30  0000 C CNN
+F 2 "" H 5650 2350 60  0000 C CNN
+F 3 "" H 5650 2350 60  0000 C CNN
+	2    5650 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 681D7E66
+P 9925 3925
+F 0 "U1" H 9975 4025 30  0000 C CNN
+F 1 "PORT" H 9925 3925 30  0000 C CNN
+F 2 "" H 9925 3925 60  0000 C CNN
+F 3 "" H 9925 3925 60  0000 C CNN
+	4    9925 3925
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 681D7F45
+P 1525 4475
+F 0 "U1" H 1575 4575 30  0000 C CNN
+F 1 "PORT" H 1525 4475 30  0000 C CNN
+F 2 "" H 1525 4475 60  0000 C CNN
+F 3 "" H 1525 4475 60  0000 C CNN
+	1    1525 4475
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 681D808E
+P 6725 5450
+F 0 "U1" H 6775 5550 30  0000 C CNN
+F 1 "PORT" H 6725 5450 30  0000 C CNN
+F 2 "" H 6725 5450 60  0000 C CNN
+F 3 "" H 6725 5450 60  0000 C CNN
+	3    6725 5450
+	0    -1   -1   0   
+$EndComp
+$Comp
+L PORT U1
+U 5 1 681DC295
+P 8550 1900
+F 0 "U1" H 8600 2000 30  0000 C CNN
+F 1 "PORT" H 8550 1900 30  0000 C CNN
+F 2 "" H 8550 1900 60  0000 C CNN
+F 3 "" H 8550 1900 60  0000 C CNN
+	5    8550 1900
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 681DC2F8
+P 9000 1900
+F 0 "#PWR01" H 9000 1650 50  0001 C CNN
+F 1 "eSim_GND" H 9000 1750 50  0000 C CNN
+F 2 "" H 9000 1900 50  0001 C CNN
+F 3 "" H 9000 1900 50  0001 C CNN
+	1    9000 1900
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9000 1900 8800 1900
+$Comp
+L PWR_FLAG #FLG02
+U 1 1 681DC50D
+P 8875 1850
+F 0 "#FLG02" H 8875 1925 50  0001 C CNN
+F 1 "PWR_FLAG" H 8875 2000 50  0000 C CNN
+F 2 "" H 8875 1850 50  0001 C CNN
+F 3 "" H 8875 1850 50  0001 C CNN
+	1    8875 1850
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8875 1850 8875 1900
+Connection ~ 8875 1900
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B.sub b/library/SubcircuitLibrary/CD4066B/CD4066B.sub
new file mode 100644
index 00000000..cddaccc7
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4066B/CD4066B.sub
@@ -0,0 +1,37 @@
+* Subcircuit CD4066B
+.subckt CD4066B net-_u1-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m4-pad1_ gnd 
+* c:\fossee\esim\library\subcircuitlibrary\cd4066b\cd4066b.cir
+.include NMOS-0.5um.lib
+.include PMOS-0.5um.lib
+* u3  net-_u2-pad2_ net-_u3-pad2_ d_inverter
+* u4  net-_u3-pad2_ net-_u4-pad2_ d_inverter
+* u7  net-_u4-pad2_ net-_u6-pad1_ d_inverter
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ ? mos_p W=100u L=5u M=1
+m3 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ ? mos_n W=100u L=5u M=1
+m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_n W=100u L=5u M=1
+m4 net-_m4-pad1_ net-_m1-pad2_ net-_m1-pad1_ ? mos_p W=100u L=5u M=1
+m5 net-_m4-pad1_ net-_m3-pad2_ net-_m1-pad1_ net-_m1-pad3_ mos_n W=100u L=5u M=1
+* u2  net-_u1-pad1_ net-_u2-pad2_ adc_bridge_1
+* u6  net-_u6-pad1_ net-_m1-pad2_ dac_bridge_1
+* u5  net-_u4-pad2_ net-_m3-pad2_ dac_bridge_1
+a1 net-_u2-pad2_ net-_u3-pad2_ u3
+a2 net-_u3-pad2_ net-_u4-pad2_ u4
+a3 net-_u4-pad2_ net-_u6-pad1_ u7
+a4 [net-_u1-pad1_ ] [net-_u2-pad2_ ] u2
+a5 [net-_u6-pad1_ ] [net-_m1-pad2_ ] u6
+a6 [net-_u4-pad2_ ] [net-_m3-pad2_ ] u5
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u6 dac_bridge(out_low= 0 out_high= 5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u5 dac_bridge(out_low= 0 out_high= 5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends CD4066B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B_Previous_Values.xml b/library/SubcircuitLibrary/CD4066B/CD4066B_Previous_Values.xml
new file mode 100644
index 00000000..c471f4de
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4066B/CD4066B_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u7 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u7><u2 name="type">adc_bridge<field10 name="Enter value for in_low (default=1.0)">0</field10><field11 name="Enter value for in_high (default=2.0)">5</field11><field12 name="Enter Rise Delay (default=1.0e-9)" /><field13 name="Enter Fall Delay (default=1.0e-9)" /></u2><u6 name="type">dac_bridge<field14 name="Enter value for out_low (default=0.0)"> 0</field14><field15 name="Enter value for out_high (default=5.0)"> 5</field15><field16 name="Enter value for out_undef (default=0.5)" /><field17 name="Enter value for input load (default=1.0e-12)" /><field18 name="Enter the Rise Time (default=1.0e-9)" /><field19 name="Enter the Fall Time (default=1.0e-9)" /></u6><u5 name="type">dac_bridge<field20 name="Enter value for out_low (default=0.0)"> 0</field20><field21 name="Enter value for out_high (default=5.0)"> 5</field21><field22 name="Enter value for out_undef (default=0.5)" /><field23 name="Enter value for input load (default=1.0e-12)" /><field24 name="Enter the Rise Time (default=1.0e-9)" /><field25 name="Enter the Fall Time (default=1.0e-9)" /></u5></model><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field>100u</field><field>5u</field><field>1</field></m1><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field>100u</field><field>5u</field><field>1</field></m3><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field>100u</field><field>5u</field><field>1</field></m2><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field>100u</field><field>5u</field><field>1</field></m4><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field>100u</field><field>5u</field><field>1</field></m5></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4066B/NMOS-0.5um.lib b/library/SubcircuitLibrary/CD4066B/NMOS-0.5um.lib
new file mode 100644
index 00000000..2e6f4635
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4066B/NMOS-0.5um.lib
@@ -0,0 +1,6 @@
+.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 
++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 
++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 
++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 
++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 
++ NSUB=1.40E17 )
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4066B/PMOS-0.5um.lib b/library/SubcircuitLibrary/CD4066B/PMOS-0.5um.lib
new file mode 100644
index 00000000..848e8b05
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4066B/PMOS-0.5um.lib
@@ -0,0 +1,6 @@
+.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u 
++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 
++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 
++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 
++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 
++ NSUB=1.0E17 )
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4066B/analysis b/library/SubcircuitLibrary/CD4066B/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4066B/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file