SN74LS151 as 8:1 Selector/ multiplexer IC

8 files changed, 1133 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/SN74LS151/74151-cache.lib b/library/SubcircuitLibrary/SN74LS151/74151-cache.lib
new file mode 100644
index 00000000..63457e0b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS151/74151-cache.lib
@@ -0,0 +1,113 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS151/74151.cir b/library/SubcircuitLibrary/SN74LS151/74151.cir
new file mode 100644
index 00000000..b01b335b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS151/74151.cir
@@ -0,0 +1,35 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74151\74151.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 04/18/25 20:22:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U5  Net-_U1-Pad4_ Net-_U16-Pad1_ d_inverter		
+X1  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad5_ Net-_U11-Pad1_ 4_and		
+X2  Net-_U6-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad6_ Net-_U11-Pad2_ 4_and		
+X3  Net-_U2-Pad2_ Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad7_ Net-_U13-Pad2_ 4_and		
+X4  Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad8_ Net-_U14-Pad2_ 4_and		
+X5  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U8-Pad2_ Net-_U1-Pad9_ Net-_U12-Pad1_ 4_and		
+X6  Net-_U6-Pad2_ Net-_U3-Pad2_ Net-_U8-Pad2_ Net-_U1-Pad10_ Net-_U12-Pad2_ 4_and		
+X7  Net-_U2-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U1-Pad11_ Net-_U9-Pad2_ 4_and		
+X8  Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U1-Pad12_ Net-_U10-Pad2_ 4_and		
+U11  Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or		
+U13  Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or		
+U14  Net-_U13-Pad3_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_or		
+U12  Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_or		
+U9  Net-_U12-Pad3_ Net-_U9-Pad2_ Net-_U10-Pad1_ d_or		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or		
+U15  Net-_U14-Pad3_ Net-_U10-Pad3_ Net-_U15-Pad3_ d_or		
+U16  Net-_U16-Pad1_ Net-_U15-Pad3_ Net-_U1-Pad13_ d_and		
+U17  Net-_U1-Pad13_ Net-_U1-Pad14_ d_inverter		
+U2  Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter		
+U6  Net-_U2-Pad2_ Net-_U6-Pad2_ d_inverter		
+U3  Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter		
+U7  Net-_U3-Pad2_ Net-_U7-Pad2_ d_inverter		
+U4  Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter		
+U8  Net-_U4-Pad2_ Net-_U8-Pad2_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS151/74151.cir.out b/library/SubcircuitLibrary/SN74LS151/74151.cir.out
new file mode 100644
index 00000000..141a4401
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS151/74151.cir.out
@@ -0,0 +1,85 @@
+* c:\fossee\esim\library\subcircuitlibrary\74151\74151.cir
+
+.include 4_and.sub
+* u5  net-_u1-pad4_ net-_u16-pad1_ d_inverter
+x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad5_ net-_u11-pad1_ 4_and
+x2 net-_u6-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad6_ net-_u11-pad2_ 4_and
+x3 net-_u2-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u1-pad7_ net-_u13-pad2_ 4_and
+x4 net-_u6-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u1-pad8_ net-_u14-pad2_ 4_and
+x5 net-_u2-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u1-pad9_ net-_u12-pad1_ 4_and
+x6 net-_u6-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u1-pad10_ net-_u12-pad2_ 4_and
+x7 net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u1-pad11_ net-_u9-pad2_ 4_and
+x8 net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u1-pad12_ net-_u10-pad2_ 4_and
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or
+* u13  net-_u11-pad3_ net-_u13-pad2_ net-_u13-pad3_ d_or
+* u14  net-_u13-pad3_ net-_u14-pad2_ net-_u14-pad3_ d_or
+* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or
+* u9  net-_u12-pad3_ net-_u9-pad2_ net-_u10-pad1_ d_or
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or
+* u15  net-_u14-pad3_ net-_u10-pad3_ net-_u15-pad3_ d_or
+* u16  net-_u16-pad1_ net-_u15-pad3_ net-_u1-pad13_ d_and
+* u17  net-_u1-pad13_ net-_u1-pad14_ d_inverter
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u6  net-_u2-pad2_ net-_u6-pad2_ d_inverter
+* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u7  net-_u3-pad2_ net-_u7-pad2_ d_inverter
+* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u8  net-_u4-pad2_ net-_u8-pad2_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+a1 net-_u1-pad4_ net-_u16-pad1_ u5
+a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a3 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a4 [net-_u13-pad3_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a5 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a6 [net-_u12-pad3_ net-_u9-pad2_ ] net-_u10-pad1_ u9
+a7 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a8 [net-_u14-pad3_ net-_u10-pad3_ ] net-_u15-pad3_ u15
+a9 [net-_u16-pad1_ net-_u15-pad3_ ] net-_u1-pad13_ u16
+a10 net-_u1-pad13_ net-_u1-pad14_ u17
+a11 net-_u1-pad1_ net-_u2-pad2_ u2
+a12 net-_u2-pad2_ net-_u6-pad2_ u6
+a13 net-_u1-pad2_ net-_u3-pad2_ u3
+a14 net-_u3-pad2_ net-_u7-pad2_ u7
+a15 net-_u1-pad3_ net-_u4-pad2_ u4
+a16 net-_u4-pad2_ net-_u8-pad2_ u8
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS151/74151.pro b/library/SubcircuitLibrary/SN74LS151/74151.pro
new file mode 100644
index 00000000..ad9ee7a2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS151/74151.pro
@@ -0,0 +1,83 @@
+update=05/06/25 20:58:57
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60
diff --git a/library/SubcircuitLibrary/SN74LS151/74151.sch b/library/SubcircuitLibrary/SN74LS151/74151.sch
new file mode 100644
index 00000000..373289ec
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS151/74151.sch
@@ -0,0 +1,736 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U5
+U 1 1 680256E1
+P 2300 1200
+F 0 "U5" H 2300 1100 60  0000 C CNN
+F 1 "d_inverter" H 2300 1350 60  0000 C CNN
+F 2 "" H 2350 1150 60  0000 C CNN
+F 3 "" H 2350 1150 60  0000 C CNN
+	1    2300 1200
+	1    0    0    -1  
+$EndComp
+$Comp
+L 4_and X1
+U 1 1 68025716
+P 4050 1800
+F 0 "X1" H 4100 1750 60  0000 C CNN
+F 1 "4_and" H 4150 1900 60  0000 C CNN
+F 2 "" H 4050 1800 60  0000 C CNN
+F 3 "" H 4050 1800 60  0000 C CNN
+	1    4050 1800
+	1    0    0    -1  
+$EndComp
+$Comp
+L 4_and X2
+U 1 1 68025737
+P 4050 2300
+F 0 "X2" H 4100 2250 60  0000 C CNN
+F 1 "4_and" H 4150 2400 60  0000 C CNN
+F 2 "" H 4050 2300 60  0000 C CNN
+F 3 "" H 4050 2300 60  0000 C CNN
+	1    4050 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L 4_and X3
+U 1 1 68025752
+P 4050 2800
+F 0 "X3" H 4100 2750 60  0000 C CNN
+F 1 "4_and" H 4150 2900 60  0000 C CNN
+F 2 "" H 4050 2800 60  0000 C CNN
+F 3 "" H 4050 2800 60  0000 C CNN
+	1    4050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L 4_and X4
+U 1 1 68025775
+P 4050 3250
+F 0 "X4" H 4100 3200 60  0000 C CNN
+F 1 "4_and" H 4150 3350 60  0000 C CNN
+F 2 "" H 4050 3250 60  0000 C CNN
+F 3 "" H 4050 3250 60  0000 C CNN
+	1    4050 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L 4_and X5
+U 1 1 68025794
+P 4050 3750
+F 0 "X5" H 4100 3700 60  0000 C CNN
+F 1 "4_and" H 4150 3850 60  0000 C CNN
+F 2 "" H 4050 3750 60  0000 C CNN
+F 3 "" H 4050 3750 60  0000 C CNN
+	1    4050 3750
+	1    0    0    -1  
+$EndComp
+$Comp
+L 4_and X6
+U 1 1 680257C7
+P 4050 4250
+F 0 "X6" H 4100 4200 60  0000 C CNN
+F 1 "4_and" H 4150 4350 60  0000 C CNN
+F 2 "" H 4050 4250 60  0000 C CNN
+F 3 "" H 4050 4250 60  0000 C CNN
+	1    4050 4250
+	1    0    0    -1  
+$EndComp
+$Comp
+L 4_and X7
+U 1 1 680257F2
+P 4050 4750
+F 0 "X7" H 4100 4700 60  0000 C CNN
+F 1 "4_and" H 4150 4850 60  0000 C CNN
+F 2 "" H 4050 4750 60  0000 C CNN
+F 3 "" H 4050 4750 60  0000 C CNN
+	1    4050 4750
+	1    0    0    -1  
+$EndComp
+$Comp
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+F 0 "X8" H 4100 5200 60  0000 C CNN
+F 1 "4_and" H 4150 5350 60  0000 C CNN
+F 2 "" H 4050 5250 60  0000 C CNN
+F 3 "" H 4050 5250 60  0000 C CNN
+	1    4050 5250
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 6802584A
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+F 1 "d_or" H 6350 2650 60  0000 C CNN
+F 2 "" H 6350 2550 60  0000 C CNN
+F 3 "" H 6350 2550 60  0000 C CNN
+	1    6350 2550
+	1    0    0    -1  
+$EndComp
+$Comp
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+F 1 "d_or" H 6400 3150 60  0000 C CNN
+F 2 "" H 6400 3050 60  0000 C CNN
+F 3 "" H 6400 3050 60  0000 C CNN
+	1    6400 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U14
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+F 0 "U14" H 6400 3450 60  0000 C CNN
+F 1 "d_or" H 6400 3550 60  0000 C CNN
+F 2 "" H 6400 3450 60  0000 C CNN
+F 3 "" H 6400 3450 60  0000 C CNN
+	1    6400 3450
+	1    0    0    -1  
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+$Comp
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+F 2 "" H 6350 4100 60  0000 C CNN
+F 3 "" H 6350 4100 60  0000 C CNN
+	1    6350 4100
+	1    0    0    -1  
+$EndComp
+$Comp
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+F 2 "" H 6300 4450 60  0000 C CNN
+F 3 "" H 6300 4450 60  0000 C CNN
+	1    6300 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U10
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+F 1 "d_or" H 6300 4900 60  0000 C CNN
+F 2 "" H 6300 4800 60  0000 C CNN
+F 3 "" H 6300 4800 60  0000 C CNN
+	1    6300 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U15
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+F 1 "d_or" H 8350 3850 60  0000 C CNN
+F 2 "" H 8350 3750 60  0000 C CNN
+F 3 "" H 8350 3750 60  0000 C CNN
+	1    8350 3750
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U16
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+F 0 "U16" H 9500 3350 60  0000 C CNN
+F 1 "d_and" H 9550 3450 60  0000 C CNN
+F 2 "" H 9500 3350 60  0000 C CNN
+F 3 "" H 9500 3350 60  0000 C CNN
+	1    9500 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U17
+U 1 1 68025AF6
+P 10450 3600
+F 0 "U17" H 10450 3500 60  0000 C CNN
+F 1 "d_inverter" H 10450 3750 60  0000 C CNN
+F 2 "" H 10500 3550 60  0000 C CNN
+F 3 "" H 10500 3550 60  0000 C CNN
+	1    10450 3600
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 68025B39
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+F 0 "U2" H 1700 5550 60  0000 C CNN
+F 1 "d_inverter" H 1700 5800 60  0000 C CNN
+F 2 "" H 1750 5600 60  0000 C CNN
+F 3 "" H 1750 5600 60  0000 C CNN
+	1    1700 5650
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 68025BA0
+P 2450 5650
+F 0 "U6" H 2450 5550 60  0000 C CNN
+F 1 "d_inverter" H 2450 5800 60  0000 C CNN
+F 2 "" H 2500 5600 60  0000 C CNN
+F 3 "" H 2500 5600 60  0000 C CNN
+	1    2450 5650
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 68025BDD
+P 1700 6100
+F 0 "U3" H 1700 6000 60  0000 C CNN
+F 1 "d_inverter" H 1700 6250 60  0000 C CNN
+F 2 "" H 1750 6050 60  0000 C CNN
+F 3 "" H 1750 6050 60  0000 C CNN
+	1    1700 6100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 68025C1C
+P 2450 6150
+F 0 "U7" H 2450 6050 60  0000 C CNN
+F 1 "d_inverter" H 2450 6300 60  0000 C CNN
+F 2 "" H 2500 6100 60  0000 C CNN
+F 3 "" H 2500 6100 60  0000 C CNN
+	1    2450 6150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 68025C63
+P 1700 6600
+F 0 "U4" H 1700 6500 60  0000 C CNN
+F 1 "d_inverter" H 1700 6750 60  0000 C CNN
+F 2 "" H 1750 6550 60  0000 C CNN
+F 3 "" H 1750 6550 60  0000 C CNN
+	1    1700 6600
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 68025CB4
+P 2500 6600
+F 0 "U8" H 2500 6500 60  0000 C CNN
+F 1 "d_inverter" H 2500 6750 60  0000 C CNN
+F 2 "" H 2550 6550 60  0000 C CNN
+F 3 "" H 2550 6550 60  0000 C CNN
+	1    2500 6600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68025CFD
+P 1050 1200
+F 0 "U1" H 1100 1300 30  0000 C CNN
+F 1 "PORT" H 1050 1200 30  0000 C CNN
+F 2 "" H 1050 1200 60  0000 C CNN
+F 3 "" H 1050 1200 60  0000 C CNN
+	4    1050 1200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68025D54
+P 1050 1950
+F 0 "U1" H 1100 2050 30  0000 C CNN
+F 1 "PORT" H 1050 1950 30  0000 C CNN
+F 2 "" H 1050 1950 60  0000 C CNN
+F 3 "" H 1050 1950 60  0000 C CNN
+	5    1050 1950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68025DA7
+P 1050 2400
+F 0 "U1" H 1100 2500 30  0000 C CNN
+F 1 "PORT" H 1050 2400 30  0000 C CNN
+F 2 "" H 1050 2400 60  0000 C CNN
+F 3 "" H 1050 2400 60  0000 C CNN
+	6    1050 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68025DF8
+P 1050 2900
+F 0 "U1" H 1100 3000 30  0000 C CNN
+F 1 "PORT" H 1050 2900 30  0000 C CNN
+F 2 "" H 1050 2900 60  0000 C CNN
+F 3 "" H 1050 2900 60  0000 C CNN
+	7    1050 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 68025E53
+P 1050 3350
+F 0 "U1" H 1100 3450 30  0000 C CNN
+F 1 "PORT" H 1050 3350 30  0000 C CNN
+F 2 "" H 1050 3350 60  0000 C CNN
+F 3 "" H 1050 3350 60  0000 C CNN
+	8    1050 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68025EA4
+P 1050 3800
+F 0 "U1" H 1100 3900 30  0000 C CNN
+F 1 "PORT" H 1050 3800 30  0000 C CNN
+F 2 "" H 1050 3800 60  0000 C CNN
+F 3 "" H 1050 3800 60  0000 C CNN
+	9    1050 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 68025F03
+P 1050 4250
+F 0 "U1" H 1100 4350 30  0000 C CNN
+F 1 "PORT" H 1050 4250 30  0000 C CNN
+F 2 "" H 1050 4250 60  0000 C CNN
+F 3 "" H 1050 4250 60  0000 C CNN
+	10   1050 4250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 68025F64
+P 1050 4700
+F 0 "U1" H 1100 4800 30  0000 C CNN
+F 1 "PORT" H 1050 4700 30  0000 C CNN
+F 2 "" H 1050 4700 60  0000 C CNN
+F 3 "" H 1050 4700 60  0000 C CNN
+	11   1050 4700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 68025FBB
+P 1050 5250
+F 0 "U1" H 1100 5350 30  0000 C CNN
+F 1 "PORT" H 1050 5250 30  0000 C CNN
+F 2 "" H 1050 5250 60  0000 C CNN
+F 3 "" H 1050 5250 60  0000 C CNN
+	12   1050 5250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68026020
+P 950 5650
+F 0 "U1" H 1000 5750 30  0000 C CNN
+F 1 "PORT" H 950 5650 30  0000 C CNN
+F 2 "" H 950 5650 60  0000 C CNN
+F 3 "" H 950 5650 60  0000 C CNN
+	1    950  5650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6802607F
+P 950 6100
+F 0 "U1" H 1000 6200 30  0000 C CNN
+F 1 "PORT" H 950 6100 30  0000 C CNN
+F 2 "" H 950 6100 60  0000 C CNN
+F 3 "" H 950 6100 60  0000 C CNN
+	2    950  6100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 680260DC
+P 950 6600
+F 0 "U1" H 1000 6700 30  0000 C CNN
+F 1 "PORT" H 950 6600 30  0000 C CNN
+F 2 "" H 950 6600 60  0000 C CNN
+F 3 "" H 950 6600 60  0000 C CNN
+	3    950  6600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 68026141
+P 11000 3300
+F 0 "U1" H 11050 3400 30  0000 C CNN
+F 1 "PORT" H 11000 3300 30  0000 C CNN
+F 2 "" H 11000 3300 60  0000 C CNN
+F 3 "" H 11000 3300 60  0000 C CNN
+	13   11000 3300
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 14 1 680261B0
+P 11150 3600
+F 0 "U1" H 11200 3700 30  0000 C CNN
+F 1 "PORT" H 11150 3600 30  0000 C CNN
+F 2 "" H 11150 3600 60  0000 C CNN
+F 3 "" H 11150 3600 60  0000 C CNN
+	14   11150 3600
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	1300 1200 2000 1200
+Wire Wire Line
+	1300 1950 3650 1950
+Wire Wire Line
+	1300 2400 3650 2400
+Wire Wire Line
+	3650 2400 3650 2450
+Wire Wire Line
+	1300 2900 3650 2900
+Wire Wire Line
+	3650 2900 3650 2950
+Wire Wire Line
+	1300 3350 3650 3350
+Wire Wire Line
+	3650 3350 3650 3400
+Wire Wire Line
+	1300 3800 3450 3800
+Wire Wire Line
+	3450 3800 3450 3900
+Wire Wire Line
+	3450 3900 3650 3900
+Wire Wire Line
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+Wire Wire Line
+	3100 4250 3100 4400
+Wire Wire Line
+	3100 4400 3650 4400
+Wire Wire Line
+	1300 4700 2900 4700
+Wire Wire Line
+	2900 4700 2900 4900
+Wire Wire Line
+	2900 4900 3650 4900
+Wire Wire Line
+	1300 5250 2750 5250
+Wire Wire Line
+	2750 5250 2750 5350
+Wire Wire Line
+	2750 5350 3650 5350
+Wire Wire Line
+	3650 5350 3650 5400
+Wire Wire Line
+	1200 5650 1400 5650
+Wire Wire Line
+	1200 6100 1400 6100
+Wire Wire Line
+	1200 6600 1400 6600
+Wire Wire Line
+	2000 5650 2150 5650
+Wire Wire Line
+	2000 6100 2150 6100
+Wire Wire Line
+	2150 6100 2150 6150
+Wire Wire Line
+	2000 6600 2200 6600
+Wire Wire Line
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+Wire Wire Line
+	5900 1800 5900 2450
+Wire Wire Line
+	4550 2300 5650 2300
+Wire Wire Line
+	5650 2300 5650 2550
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	7250 2500 7250 2800
+Wire Wire Line
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+Wire Wire Line
+	5750 2800 5750 2950
+Wire Wire Line
+	5750 2950 5950 2950
+Wire Wire Line
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+Wire Wire Line
+	5300 2800 5300 3050
+Wire Wire Line
+	5300 3050 5950 3050
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	5950 3200 5950 3350
+Wire Wire Line
+	4550 3250 5650 3250
+Wire Wire Line
+	5650 3250 5650 3450
+Wire Wire Line
+	5650 3450 5950 3450
+Wire Wire Line
+	6850 3400 7900 3400
+Wire Wire Line
+	7900 3400 7900 3650
+Wire Wire Line
+	4550 3750 5900 3750
+Wire Wire Line
+	5900 3750 5900 4000
+Wire Wire Line
+	4500 4100 5900 4100
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	5850 4200 5850 4350
+Wire Wire Line
+	4550 4750 5350 4750
+Wire Wire Line
+	5350 4750 5350 4450
+Wire Wire Line
+	5350 4450 5850 4450
+Wire Wire Line
+	6750 4400 6900 4400
+Wire Wire Line
+	6900 4400 6900 4550
+Wire Wire Line
+	6900 4550 5850 4550
+Wire Wire Line
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+Wire Wire Line
+	4550 5250 5850 5250
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	9950 3300 10750 3300
+Wire Wire Line
+	10100 3300 10100 3600
+Wire Wire Line
+	10100 3600 10150 3600
+Connection ~ 10100 3300
+Wire Wire Line
+	10750 3600 10900 3600
+Wire Wire Line
+	2600 1200 9050 1200
+Wire Wire Line
+	9050 1200 9050 3250
+Wire Wire Line
+	2050 5650 2050 1650
+Wire Wire Line
+	2050 1650 3650 1650
+Connection ~ 2050 5650
+Wire Wire Line
+	3650 2650 2050 2650
+Connection ~ 2050 2650
+Wire Wire Line
+	3650 3600 2050 3600
+Connection ~ 2050 3600
+Wire Wire Line
+	3650 4600 2050 4600
+Connection ~ 2050 4600
+Wire Wire Line
+	2750 5650 3100 5650
+Wire Wire Line
+	3100 5650 3100 5400
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	2150 2150 3650 2150
+Wire Wire Line
+	3650 3100 2150 3100
+Wire Wire Line
+	2150 3100 2150 3150
+Connection ~ 2150 3150
+Wire Wire Line
+	3650 4100 2150 4100
+Connection ~ 2150 4100
+Wire Wire Line
+	3650 5100 2150 5100
+Connection ~ 2150 5100
+Wire Wire Line
+	2050 6100 2050 5850
+Wire Wire Line
+	2050 5850 2850 5850
+Connection ~ 2050 6100
+Wire Wire Line
+	2750 6150 3000 6150
+Wire Wire Line
+	2100 6600 2100 6250
+Wire Wire Line
+	2100 6250 3200 6250
+Connection ~ 2100 6600
+Wire Wire Line
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+Wire Wire Line
+	2850 5850 2850 1750
+Wire Wire Line
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+Wire Wire Line
+	2850 2250 3650 2250
+Connection ~ 2850 2250
+Wire Wire Line
+	2850 3700 3650 3700
+Connection ~ 2850 3700
+Wire Wire Line
+	2850 4200 3650 4200
+Connection ~ 2850 4200
+Wire Wire Line
+	3000 6150 3000 2750
+Wire Wire Line
+	3000 2750 3650 2750
+Wire Wire Line
+	3000 3200 3650 3200
+Connection ~ 3000 3200
+Wire Wire Line
+	3000 4700 3650 4700
+Connection ~ 3000 4700
+Wire Wire Line
+	3000 5200 3650 5200
+Connection ~ 3000 5200
+Wire Wire Line
+	3200 6250 3200 1850
+Wire Wire Line
+	3200 1850 3650 1850
+Wire Wire Line
+	3200 2350 3650 2350
+Connection ~ 3200 2350
+Wire Wire Line
+	3200 2850 3650 2850
+Connection ~ 3200 2850
+Wire Wire Line
+	3200 3300 3650 3300
+Connection ~ 3200 3300
+Wire Wire Line
+	3350 6600 3350 3950
+Wire Wire Line
+	3350 3950 3550 3950
+Wire Wire Line
+	3550 3950 3550 3800
+Wire Wire Line
+	3550 3800 3650 3800
+Wire Wire Line
+	3350 4300 3650 4300
+Connection ~ 3350 4300
+Wire Wire Line
+	3350 4800 3650 4800
+Connection ~ 3350 4800
+Wire Wire Line
+	3350 5300 3650 5300
+Connection ~ 3350 5300
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS151/74151.sub b/library/SubcircuitLibrary/SN74LS151/74151.sub
new file mode 100644
index 00000000..c53f323b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS151/74151.sub
@@ -0,0 +1,79 @@
+* Subcircuit 74151
+.subckt 74151 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
+* c:\fossee\esim\library\subcircuitlibrary\74151\74151.cir
+.include 4_and.sub
+* u5  net-_u1-pad4_ net-_u16-pad1_ d_inverter
+x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad5_ net-_u11-pad1_ 4_and
+x2 net-_u6-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad6_ net-_u11-pad2_ 4_and
+x3 net-_u2-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u1-pad7_ net-_u13-pad2_ 4_and
+x4 net-_u6-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u1-pad8_ net-_u14-pad2_ 4_and
+x5 net-_u2-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u1-pad9_ net-_u12-pad1_ 4_and
+x6 net-_u6-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u1-pad10_ net-_u12-pad2_ 4_and
+x7 net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u1-pad11_ net-_u9-pad2_ 4_and
+x8 net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u1-pad12_ net-_u10-pad2_ 4_and
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or
+* u13  net-_u11-pad3_ net-_u13-pad2_ net-_u13-pad3_ d_or
+* u14  net-_u13-pad3_ net-_u14-pad2_ net-_u14-pad3_ d_or
+* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or
+* u9  net-_u12-pad3_ net-_u9-pad2_ net-_u10-pad1_ d_or
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or
+* u15  net-_u14-pad3_ net-_u10-pad3_ net-_u15-pad3_ d_or
+* u16  net-_u16-pad1_ net-_u15-pad3_ net-_u1-pad13_ d_and
+* u17  net-_u1-pad13_ net-_u1-pad14_ d_inverter
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u6  net-_u2-pad2_ net-_u6-pad2_ d_inverter
+* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u7  net-_u3-pad2_ net-_u7-pad2_ d_inverter
+* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u8  net-_u4-pad2_ net-_u8-pad2_ d_inverter
+a1 net-_u1-pad4_ net-_u16-pad1_ u5
+a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a3 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a4 [net-_u13-pad3_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a5 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a6 [net-_u12-pad3_ net-_u9-pad2_ ] net-_u10-pad1_ u9
+a7 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a8 [net-_u14-pad3_ net-_u10-pad3_ ] net-_u15-pad3_ u15
+a9 [net-_u16-pad1_ net-_u15-pad3_ ] net-_u1-pad13_ u16
+a10 net-_u1-pad13_ net-_u1-pad14_ u17
+a11 net-_u1-pad1_ net-_u2-pad2_ u2
+a12 net-_u2-pad2_ net-_u6-pad2_ u6
+a13 net-_u1-pad2_ net-_u3-pad2_ u3
+a14 net-_u3-pad2_ net-_u7-pad2_ u7
+a15 net-_u1-pad3_ net-_u4-pad2_ u4
+a16 net-_u4-pad2_ net-_u8-pad2_ u8
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74151
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS151/74151_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS151/74151_Previous_Values.xml
new file mode 100644
index 00000000..8ebb72a7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS151/74151_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u5 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u5><u11 name="type">d_or<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u11><u13 name="type">d_or<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_or<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u14><u12 name="type">d_or<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u12><u9 name="type">d_or<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_or<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u10><u15 name="type">d_or<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u17><u2 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u2><u6 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u6><u3 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u3><u7 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u7><u4 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u4><u8 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x7><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x8></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS151/analysis b/library/SubcircuitLibrary/SN74LS151/analysis
new file mode 100644
index 00000000..5c9b0b46
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS151/analysis
@@ -0,0 +1 @@
+.tran 10e-03 20e-00 0e-03
\ No newline at end of file