diff options
| author | AmanShukla111 | 2025-06-01 19:47:54 +0530 |
|---|---|---|
| committer | AmanShukla111 | 2025-06-01 19:47:54 +0530 |
| commit | 3743b10a1a2598b910cce7245402abc435ab1de9 (patch) | |
| tree | 38b4e9109970249fca03cb65e02a11fc50d17cd2 | |
| parent | 5956f945cf4bd7a46b016c1cf1a60d96c586bc75 (diff) | |
| download | eSim-3743b10a1a2598b910cce7245402abc435ab1de9.tar.gz eSim-3743b10a1a2598b910cce7245402abc435ab1de9.tar.bz2 eSim-3743b10a1a2598b910cce7245402abc435ab1de9.zip | |
Adding 74HC157-Quad 2 input MUXs with enable
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/74HC157-cache.lib | 91 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/74HC157.cir | 20 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/74HC157.cir.out | 37 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/74HC157.pro | 73 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/74HC157.sch | 355 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/74HC157.sub | 31 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/74HC157_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/analysis | 1 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/mux-cache.lib | 94 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/mux.cir | 15 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/mux.cir.out | 28 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/mux.pro | 73 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/mux.sch | 167 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/mux.sub | 22 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/mux_Previous_Values.xml | 1 |
15 files changed, 1009 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74HC157/74HC157-cache.lib b/library/SubcircuitLibrary/74HC157/74HC157-cache.lib new file mode 100644 index 00000000..b3095e1d --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/74HC157-cache.lib @@ -0,0 +1,91 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# mux
+#
+DEF mux X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "mux" 0 150 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -200 350 200 -250 0 1 0 N
+X SEL 1 0 -450 200 U 50 50 1 1 I
+X 0 2 -400 200 200 R 50 50 1 1 I
+X 1 3 -400 -150 200 R 50 50 1 1 I
+X Z 4 400 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC157/74HC157.cir b/library/SubcircuitLibrary/74HC157/74HC157.cir new file mode 100644 index 00000000..e693accc --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/74HC157.cir @@ -0,0 +1,20 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC157\74HC157.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 5/10/2025 5:51:02 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad9_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U3-Pad1_ mux
+X2 Net-_U1-Pad9_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U4-Pad1_ mux
+X3 Net-_U1-Pad9_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U5-Pad1_ mux
+X4 Net-_U1-Pad9_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U6-Pad1_ mux
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT
+U3 Net-_U3-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad11_ d_and
+U4 Net-_U4-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad12_ d_and
+U5 Net-_U5-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad13_ d_and
+U6 Net-_U6-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad14_ d_and
+U2 Net-_U1-Pad10_ Net-_U2-Pad2_ d_inverter
+
+.end
diff --git a/library/SubcircuitLibrary/74HC157/74HC157.cir.out b/library/SubcircuitLibrary/74HC157/74HC157.cir.out new file mode 100644 index 00000000..ead8d438 --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/74HC157.cir.out @@ -0,0 +1,37 @@ +* c:\fossee\esim\library\subcircuitlibrary\74hc157\74hc157.cir
+
+.include mux.sub
+x1 net-_u1-pad9_ net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad1_ mux
+x2 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad1_ mux
+x3 net-_u1-pad9_ net-_u1-pad5_ net-_u1-pad6_ net-_u5-pad1_ mux
+x4 net-_u1-pad9_ net-_u1-pad7_ net-_u1-pad8_ net-_u6-pad1_ mux
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+* u3 net-_u3-pad1_ net-_u2-pad2_ net-_u1-pad11_ d_and
+* u4 net-_u4-pad1_ net-_u2-pad2_ net-_u1-pad12_ d_and
+* u5 net-_u5-pad1_ net-_u2-pad2_ net-_u1-pad13_ d_and
+* u6 net-_u6-pad1_ net-_u2-pad2_ net-_u1-pad14_ d_and
+* u2 net-_u1-pad10_ net-_u2-pad2_ d_inverter
+a1 [net-_u3-pad1_ net-_u2-pad2_ ] net-_u1-pad11_ u3
+a2 [net-_u4-pad1_ net-_u2-pad2_ ] net-_u1-pad12_ u4
+a3 [net-_u5-pad1_ net-_u2-pad2_ ] net-_u1-pad13_ u5
+a4 [net-_u6-pad1_ net-_u2-pad2_ ] net-_u1-pad14_ u6
+a5 net-_u1-pad10_ net-_u2-pad2_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC157/74HC157.pro b/library/SubcircuitLibrary/74HC157/74HC157.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/74HC157.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74HC157/74HC157.sch b/library/SubcircuitLibrary/74HC157/74HC157.sch new file mode 100644 index 00000000..22a97a51 --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/74HC157.sch @@ -0,0 +1,355 @@ +EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L mux X1
+U 1 1 681F40C5
+P 3750 1650
+F 0 "X1" H 3750 1650 60 0000 C CNN
+F 1 "mux" H 3750 1800 60 0000 C CNN
+F 2 "" H 3750 1650 60 0001 C CNN
+F 3 "" H 3750 1650 60 0001 C CNN
+ 1 3750 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L mux X2
+U 1 1 681F4106
+P 3750 2850
+F 0 "X2" H 3750 2850 60 0000 C CNN
+F 1 "mux" H 3750 3000 60 0000 C CNN
+F 2 "" H 3750 2850 60 0001 C CNN
+F 3 "" H 3750 2850 60 0001 C CNN
+ 1 3750 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L mux X3
+U 1 1 681F4155
+P 3750 4050
+F 0 "X3" H 3750 4050 60 0000 C CNN
+F 1 "mux" H 3750 4200 60 0000 C CNN
+F 2 "" H 3750 4050 60 0001 C CNN
+F 3 "" H 3750 4050 60 0001 C CNN
+ 1 3750 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L mux X4
+U 1 1 681F4232
+P 3750 5250
+F 0 "X4" H 3750 5250 60 0000 C CNN
+F 1 "mux" H 3750 5400 60 0000 C CNN
+F 2 "" H 3750 5250 60 0001 C CNN
+F 3 "" H 3750 5250 60 0001 C CNN
+ 1 3750 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 681F4317
+P 3750 6400
+F 0 "U1" H 3800 6500 30 0000 C CNN
+F 1 "PORT" H 3750 6400 30 0000 C CNN
+F 2 "" H 3750 6400 60 0000 C CNN
+F 3 "" H 3750 6400 60 0000 C CNN
+ 9 3750 6400
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 3750 5700 3750 6150
+Wire Wire Line
+ 3750 2100 2900 2100
+Wire Wire Line
+ 2900 2100 2900 5950
+Wire Wire Line
+ 2900 5950 3750 5950
+Connection ~ 3750 5950
+Wire Wire Line
+ 3750 3300 2900 3300
+Connection ~ 2900 3300
+Wire Wire Line
+ 3750 4500 2900 4500
+Connection ~ 2900 4500
+$Comp
+L PORT U1
+U 1 1 681F43D2
+P 3100 1450
+F 0 "U1" H 3150 1550 30 0000 C CNN
+F 1 "PORT" H 3100 1450 30 0000 C CNN
+F 2 "" H 3100 1450 60 0000 C CNN
+F 3 "" H 3100 1450 60 0000 C CNN
+ 1 3100 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 681F443D
+P 3100 1800
+F 0 "U1" H 3150 1900 30 0000 C CNN
+F 1 "PORT" H 3100 1800 30 0000 C CNN
+F 2 "" H 3100 1800 60 0000 C CNN
+F 3 "" H 3100 1800 60 0000 C CNN
+ 2 3100 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 681F44B6
+P 5800 1600
+F 0 "U1" H 5850 1700 30 0000 C CNN
+F 1 "PORT" H 5800 1600 30 0000 C CNN
+F 2 "" H 5800 1600 60 0000 C CNN
+F 3 "" H 5800 1600 60 0000 C CNN
+ 11 5800 1600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 681F4555
+P 3100 2650
+F 0 "U1" H 3150 2750 30 0000 C CNN
+F 1 "PORT" H 3100 2650 30 0000 C CNN
+F 2 "" H 3100 2650 60 0000 C CNN
+F 3 "" H 3100 2650 60 0000 C CNN
+ 3 3100 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 681F45D4
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 4 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 681F4659
+P 5800 2800
+F 0 "U1" H 5850 2900 30 0000 C CNN
+F 1 "PORT" H 5800 2800 30 0000 C CNN
+F 2 "" H 5800 2800 60 0000 C CNN
+F 3 "" H 5800 2800 60 0000 C CNN
+ 12 5800 2800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 681F46F8
+P 3100 3850
+F 0 "U1" H 3150 3950 30 0000 C CNN
+F 1 "PORT" H 3100 3850 30 0000 C CNN
+F 2 "" H 3100 3850 60 0000 C CNN
+F 3 "" H 3100 3850 60 0000 C CNN
+ 5 3100 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 681F4753
+P 3100 4200
+F 0 "U1" H 3150 4300 30 0000 C CNN
+F 1 "PORT" H 3100 4200 30 0000 C CNN
+F 2 "" H 3100 4200 60 0000 C CNN
+F 3 "" H 3100 4200 60 0000 C CNN
+ 6 3100 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 681F47D2
+P 5800 3950
+F 0 "U1" H 5850 4050 30 0000 C CNN
+F 1 "PORT" H 5800 3950 30 0000 C CNN
+F 2 "" H 5800 3950 60 0000 C CNN
+F 3 "" H 5800 3950 60 0000 C CNN
+ 13 5800 3950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 681F4881
+P 3100 5050
+F 0 "U1" H 3150 5150 30 0000 C CNN
+F 1 "PORT" H 3100 5050 30 0000 C CNN
+F 2 "" H 3100 5050 60 0000 C CNN
+F 3 "" H 3100 5050 60 0000 C CNN
+ 7 3100 5050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 681F48DC
+P 3100 5400
+F 0 "U1" H 3150 5500 30 0000 C CNN
+F 1 "PORT" H 3100 5400 30 0000 C CNN
+F 2 "" H 3100 5400 60 0000 C CNN
+F 3 "" H 3100 5400 60 0000 C CNN
+ 8 3100 5400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 681F49BC
+P 5800 5200
+F 0 "U1" H 5850 5300 30 0000 C CNN
+F 1 "PORT" H 5800 5200 30 0000 C CNN
+F 2 "" H 5800 5200 60 0000 C CNN
+F 3 "" H 5800 5200 60 0000 C CNN
+ 14 5800 5200
+ -1 0 0 1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 681F4B7E
+P 5100 1650
+F 0 "U3" H 5100 1650 60 0000 C CNN
+F 1 "d_and" H 5150 1750 60 0000 C CNN
+F 2 "" H 5100 1650 60 0000 C CNN
+F 3 "" H 5100 1650 60 0000 C CNN
+ 1 5100 1650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4150 1600 4150 1550
+Wire Wire Line
+ 4150 1550 4650 1550
+$Comp
+L d_and U4
+U 1 1 681F4C76
+P 5100 2850
+F 0 "U4" H 5100 2850 60 0000 C CNN
+F 1 "d_and" H 5150 2950 60 0000 C CNN
+F 2 "" H 5100 2850 60 0000 C CNN
+F 3 "" H 5100 2850 60 0000 C CNN
+ 1 5100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 681F4CFB
+P 5100 4000
+F 0 "U5" H 5100 4000 60 0000 C CNN
+F 1 "d_and" H 5150 4100 60 0000 C CNN
+F 2 "" H 5100 4000 60 0000 C CNN
+F 3 "" H 5100 4000 60 0000 C CNN
+ 1 5100 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U6
+U 1 1 681F4D6E
+P 5100 5250
+F 0 "U6" H 5100 5250 60 0000 C CNN
+F 1 "d_and" H 5150 5350 60 0000 C CNN
+F 2 "" H 5100 5250 60 0000 C CNN
+F 3 "" H 5100 5250 60 0000 C CNN
+ 1 5100 5250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4150 2800 4150 2750
+Wire Wire Line
+ 4150 2750 4650 2750
+Wire Wire Line
+ 4150 4000 4150 3900
+Wire Wire Line
+ 4150 3900 4650 3900
+Wire Wire Line
+ 4150 5200 4150 5150
+Wire Wire Line
+ 4150 5150 4650 5150
+$Comp
+L PORT U1
+U 10 1 681F4E58
+P 4950 6850
+F 0 "U1" H 5000 6950 30 0000 C CNN
+F 1 "PORT" H 4950 6850 30 0000 C CNN
+F 2 "" H 4950 6850 60 0000 C CNN
+F 3 "" H 4950 6850 60 0000 C CNN
+ 10 4950 6850
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 4350 6150 4350 1650
+Wire Wire Line
+ 4350 1650 4650 1650
+$Comp
+L d_inverter U2
+U 1 1 681F4FD2
+P 4650 6150
+F 0 "U2" H 4650 6050 60 0000 C CNN
+F 1 "d_inverter" H 4650 6300 60 0000 C CNN
+F 2 "" H 4700 6100 60 0000 C CNN
+F 3 "" H 4700 6100 60 0000 C CNN
+ 1 4650 6150
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4950 6150 4950 6600
+Wire Wire Line
+ 4650 2850 4350 2850
+Connection ~ 4350 2850
+Wire Wire Line
+ 4650 4000 4350 4000
+Connection ~ 4350 4000
+Wire Wire Line
+ 4650 5250 4350 5250
+Connection ~ 4350 5250
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC157/74HC157.sub b/library/SubcircuitLibrary/74HC157/74HC157.sub new file mode 100644 index 00000000..cebb4985 --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/74HC157.sub @@ -0,0 +1,31 @@ +* Subcircuit 74HC157
+.subckt 74HC157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_
+* c:\fossee\esim\library\subcircuitlibrary\74hc157\74hc157.cir
+.include mux.sub
+x1 net-_u1-pad9_ net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad1_ mux
+x2 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad1_ mux
+x3 net-_u1-pad9_ net-_u1-pad5_ net-_u1-pad6_ net-_u5-pad1_ mux
+x4 net-_u1-pad9_ net-_u1-pad7_ net-_u1-pad8_ net-_u6-pad1_ mux
+* u3 net-_u3-pad1_ net-_u2-pad2_ net-_u1-pad11_ d_and
+* u4 net-_u4-pad1_ net-_u2-pad2_ net-_u1-pad12_ d_and
+* u5 net-_u5-pad1_ net-_u2-pad2_ net-_u1-pad13_ d_and
+* u6 net-_u6-pad1_ net-_u2-pad2_ net-_u1-pad14_ d_and
+* u2 net-_u1-pad10_ net-_u2-pad2_ d_inverter
+a1 [net-_u3-pad1_ net-_u2-pad2_ ] net-_u1-pad11_ u3
+a2 [net-_u4-pad1_ net-_u2-pad2_ ] net-_u1-pad12_ u4
+a3 [net-_u5-pad1_ net-_u2-pad2_ ] net-_u1-pad13_ u5
+a4 [net-_u6-pad1_ net-_u2-pad2_ ] net-_u1-pad14_ u6
+a5 net-_u1-pad10_ net-_u2-pad2_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC157
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC157/74HC157_Previous_Values.xml b/library/SubcircuitLibrary/74HC157/74HC157_Previous_Values.xml new file mode 100644 index 00000000..a72a8ef0 --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/74HC157_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u6><u2 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\mux</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\mux</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\mux</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\mux</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC157/analysis b/library/SubcircuitLibrary/74HC157/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC157/mux-cache.lib b/library/SubcircuitLibrary/74HC157/mux-cache.lib new file mode 100644 index 00000000..86b09eb4 --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/mux-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC157/mux.cir b/library/SubcircuitLibrary/74HC157/mux.cir new file mode 100644 index 00000000..211b8ef8 --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/mux.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\mux\mux.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 3/7/2025 10:16:23 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_and
+U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U4-Pad3_ d_and
+U5 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad4_ d_or
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74HC157/mux.cir.out b/library/SubcircuitLibrary/74HC157/mux.cir.out new file mode 100644 index 00000000..d23ed61f --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/mux.cir.out @@ -0,0 +1,28 @@ +* c:\fossee\esim\library\subcircuitlibrary\mux\mux.cir
+
+* u3 net-_u1-pad1_ net-_u1-pad3_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+a2 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u4-pad3_ u4
+a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5
+a4 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC157/mux.pro b/library/SubcircuitLibrary/74HC157/mux.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/mux.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74HC157/mux.sch b/library/SubcircuitLibrary/74HC157/mux.sch new file mode 100644 index 00000000..22288031 --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/mux.sch @@ -0,0 +1,167 @@ +EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U3
+U 1 1 67CB20E3
+P 5000 3050
+F 0 "U3" H 5000 3050 60 0000 C CNN
+F 1 "d_and" H 5050 3150 60 0000 C CNN
+F 2 "" H 5000 3050 60 0000 C CNN
+F 3 "" H 5000 3050 60 0000 C CNN
+ 1 5000 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 67CB217D
+P 5000 3800
+F 0 "U4" H 5000 3800 60 0000 C CNN
+F 1 "d_and" H 5050 3900 60 0000 C CNN
+F 2 "" H 5000 3800 60 0000 C CNN
+F 3 "" H 5000 3800 60 0000 C CNN
+ 1 5000 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U5
+U 1 1 67CB21A2
+P 6600 3400
+F 0 "U5" H 6600 3400 60 0000 C CNN
+F 1 "d_or" H 6600 3500 60 0000 C CNN
+F 2 "" H 6600 3400 60 0000 C CNN
+F 3 "" H 6600 3400 60 0000 C CNN
+ 1 6600 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5450 3000 6150 3000
+Wire Wire Line
+ 6150 3000 6150 3300
+Wire Wire Line
+ 5450 3750 6150 3750
+Wire Wire Line
+ 6150 3750 6150 3400
+$Comp
+L d_inverter U2
+U 1 1 67CB21FF
+P 3050 3800
+F 0 "U2" H 3050 3700 60 0000 C CNN
+F 1 "d_inverter" H 3050 3950 60 0000 C CNN
+F 2 "" H 3100 3750 60 0000 C CNN
+F 3 "" H 3100 3750 60 0000 C CNN
+ 1 3050 3800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3350 3800 4550 3800
+$Comp
+L PORT U1
+U 1 1 67CB22E7
+P 1700 2750
+F 0 "U1" H 1750 2850 30 0000 C CNN
+F 1 "PORT" H 1700 2750 30 0000 C CNN
+F 2 "" H 1700 2750 60 0000 C CNN
+F 3 "" H 1700 2750 60 0000 C CNN
+ 1 1700 2750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1950 2750 4550 2750
+Wire Wire Line
+ 4550 2750 4550 2950
+Wire Wire Line
+ 2750 3800 2750 2750
+Connection ~ 2750 2750
+$Comp
+L PORT U1
+U 3 1 67CB23D9
+P 4100 3050
+F 0 "U1" H 4150 3150 30 0000 C CNN
+F 1 "PORT" H 4100 3050 30 0000 C CNN
+F 2 "" H 4100 3050 60 0000 C CNN
+F 3 "" H 4100 3050 60 0000 C CNN
+ 3 4100 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 67CB2470
+P 4000 3700
+F 0 "U1" H 4050 3800 30 0000 C CNN
+F 1 "PORT" H 4000 3700 30 0000 C CNN
+F 2 "" H 4000 3700 60 0000 C CNN
+F 3 "" H 4000 3700 60 0000 C CNN
+ 2 4000 3700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4350 3050 4550 3050
+Wire Wire Line
+ 4250 3700 4550 3700
+$Comp
+L PORT U1
+U 4 1 67CB24FC
+P 7400 3350
+F 0 "U1" H 7450 3450 30 0000 C CNN
+F 1 "PORT" H 7400 3350 30 0000 C CNN
+F 2 "" H 7400 3350 60 0000 C CNN
+F 3 "" H 7400 3350 60 0000 C CNN
+ 4 7400 3350
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7150 3350 7050 3350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC157/mux.sub b/library/SubcircuitLibrary/74HC157/mux.sub new file mode 100644 index 00000000..1c44b830 --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/mux.sub @@ -0,0 +1,22 @@ +* Subcircuit mux
+.subckt mux net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\fossee\esim\library\subcircuitlibrary\mux\mux.cir
+* u3 net-_u1-pad1_ net-_u1-pad3_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+a2 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u4-pad3_ u4
+a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5
+a4 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends mux
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC157/mux_Previous_Values.xml b/library/SubcircuitLibrary/74HC157/mux_Previous_Values.xml new file mode 100644 index 00000000..5ef4ab5b --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/mux_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u3 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_or<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file |