blob: f9f2e929423365f605faa93d8d179485d2a5baf0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nghdl_ha is
port (
i_bit1 : in std_logic_vector(0 downto 0);
i_bit2 : in std_logic_vector(0 downto 0);
o_sum : out std_logic_vector(0 downto 0);
o_carry : out std_logic_vector(0 downto 0)
);
end nghdl_ha;
architecture rtl of nghdl_ha is
begin
o_sum <= i_bit1 xor i_bit2;
o_carry <= i_bit1 and i_bit2;
end rtl;
|
