#!/usr/bin/env python """#!/usr/bin/python """ import re import sys import os #######Script start from here print "Arguement is :", sys.argv[1] fname = os.path.basename(sys.argv[1]) print "VHDL filename is :",fname home = os.path.expanduser("~") ###########Creating connection_info.txt file from vhdl file##################### read_vhdl = open(sys.argv[1],'r') vhdl_data = read_vhdl.readlines() read_vhdl.close() start_flag = -1 #Used for scaning part of data scan_data=[] #p=re.search('port(.*?)end',read_vhdl,re.M|re.I|re.DOTALL).group() for item in vhdl_data: if re.search('port',item,re.I): start_flag = 1 elif re.search("end",item,re.I): start_flag = 0 else: pass if start_flag == 1: item=re.sub("port", " ", item, flags=re.I) item=re.sub("\(", " ", item, flags=re.I) item=re.sub("\)", " ", item, flags=re.I) item=re.sub(";"," ",item,flags=re.I) scan_data.append(item.rstrip()) scan_data=filter(None, scan_data) elif start_flag == 0: break #print "Scan Data",scan_data port_info=[] for item in scan_data: print "Scan Data :",item if re.search("in",item,flags=re.I): if re.search("std_logic_vector",item,flags=re.I): temp=re.compile(r"\s*std_logic_vector\s*",flags=re.I) elif re.search("std_logic",item,flags=re.I): temp=re.compile(r"\s*std_logic\s*",flags=re.I) else: print "Please check your vhdl code for datatype of input port" sys.exit() elif re.search("out",item,flags=re.I): if re.search("std_logic_vector",item,flags=re.I): temp=re.compile(r"\s*std_logic_vector\s*",flags=re.I) elif re.search("std_logic",item,flags=re.I): temp=re.compile(r"\s*std_logic\s*",flags=re.I) else: print "Please check your vhdl code for datatype of output port" sys.exit() else: print "Please check the in/out direction of your port" sys.exit() lhs=temp.split(item)[0] rhs=temp.split(item)[1] bit_info=re.compile(r"\s*downto\s*",flags=re.I).split(rhs)[0] port_info.append(lhs+":"+str(int(bit_info)+int(1))) print "Port Info :",port_info #Open connection_info.txt file con_ifo=open('connection_info.txt','w') for item in port_info: word=item.split(':') con_ifo.write(word[0].strip()+' '+word[1].strip()+' '+word[2].strip()) con_ifo.write("\n") con_ifo.close() ############### Reading connection/port information############################# #Declaring input and output list input_list=[] output_list=[] #Reading connection_info.txt file for port infomation read_file=open('connection_info.txt','r') data=read_file.readlines() read_file.close() #Extracting input and output port list from data for line in data: if re.match(r'^\s*$', line): pass #print "Blank Line" else: in_items=re.findall("IN",line,re.MULTILINE|re.IGNORECASE) out_items=re.findall("OUT",line,re.MULTILINE|re.IGNORECASE) #print "Line",line if in_items: input_list.append(line.split()) #print "Found IN" else: pass #print "Not Found" if out_items: output_list.append(line.split()) #print "Found Out" else: pass print "Inout List :",input_list print "Output list",output_list input_port=[] output_port=[] #creating list of input and output port with its weight for input in input_list: input_port.append(input[0]+":"+input[2]) #print "Input List: ",input for output in output_list: output_port.append(output[0]+":"+output[2]) #print "Output List: ",output print "Output Port List : ",output_port print "Input Port List : ",input_port ######################Creating content for cfunc.mod file####################### print "Starting With cfunc.mod file" cfunc=open('cfunc.mod','w') print "Building content for cfunc.mod file" comment='''/* This is cfunc.mod file auto generated by gen_con_info.py Developed by Fahim at IIT Bombay */ \n ''' header=''' #include #include #include #include #include #include #include #include #include #include #include ''' function_open='''void cm_'''+fname.split('.')[0]+'''(ARGS) \n{''' digital_state_output=[] for item in output_port: digital_state_output.append("Digital_State_t *_op_"+item.split(':')[0]+", *_op_"+item.split(':')[0]+"_old;") var_section=''' // Declaring components of Client static int flag=0; FILE *log_client = NULL; log_client=fopen("client.log","a"); int socket_fd, bytes_recieved; char send_data[1024]; char recv_data[1024]; char *key_iter; struct hostent *host; struct sockaddr_in server_addr; double time_limit = PARAM(stop_time); int sock_port = 5000+PARAM(instance_id); ''' temp_input_var=[] for item in input_port: temp_input_var.append("char temp_"+item.split(':')[0]+"[1024];") #Start of INIT function init_start_function=''' if(INIT) { /* Allocate storage for output ports.And set the load for input ports */ ''' cm_event_alloc=[] cm_count_output=0 for item in output_port: cm_event_alloc.append("cm_event_alloc("+str(cm_count_output)+","+item.split(':')[1]+"*sizeof(Digital_State_t));") cm_count_output=cm_count_output+1 load_in_port=[] for item in input_port: load_in_port.append("for(Ii=0;Iih_addr); bzero(&(server_addr.sin_zero),8); ''' connect_server=''' printf("Client-Connecting to server \\n"); fprintf(log_client,"Client-Connecting to server \\n"); //Conneting to server int try_limit=10; while(try_limit>0) { if (connect(socket_fd, (struct sockaddr*)&server_addr,sizeof(struct sockaddr)) == -1) { sleep(1); try_limit--; if(try_limit==0) { fprintf(stderr,"Connect- Error:Tried to connect server on port , failed..giving up \\n"); fprintf(log_client,"Connect- Error:Tried to connect server on port , failed..giving up \\n"); exit(1); } } else { printf("Client-Connected to server \\n"); fprintf(log_client,"Client-Connected to server \\n"); break; } } ''' time_limit =''' if(TIME < time_limit) { //Formating data for sending it to client int Ii; ''' #Assign bit value to every input assign_data_to_input=[] for item in input_port: assign_data_to_input.append("\t\t\tfor(Ii=0;Ii "+item.split(':')[0]+",\n") for item in output_port: if output_port.index(item) == len(output_port) - 1: map.append("\t\t\t\t"+item.split(':')[0]+" => "+item.split(':')[0]+"\n") else: map.append("\t\t\t\t"+item.split(':')[0]+" => "+item.split(':')[0]+",\n") map.append("\t\t\t);") #testbench Clock tb_clk= "clk_s <= not clk_s after 5 us;\n\n" #Adding Process block for Vhpi process_Vhpi=[] process_Vhpi.append("\tprocess\n\t\tvariable sock_port : integer;\n\t\tbegin\n\t\tsock_port := sock_pkg_fun;\n\t\tVhpi_Initialize(sock_port);\n\t\twait until clk_s = '1';\n\t\twhile true loop\n\t\t\twait until clk_s = '0';\n\t\t\tVhpi_Listen;\n\t\t\twait for 1 us;\n\t\t\tVhpi_Send;\n\t\tend loop;\n\t\twait;\n\tend process;\n\n") #Adding process block process=[] process.append("\tprocess\n\n") for item in input_port: process.append("\t\tvariable "+item.split(':')[0]+"_v : VhpiString;\n") for item in output_port: process.append("\t\tvariable "+item.split(':')[0]+"_v : VhpiString;\n") process.append("\t\tvariable obj_ref : VhpiString;\n") process.append("\tbegin\n") process.append("\t\twhile true loop\n") process.append("\t\t\twait until clk_s = '0';\n\n") for item in input_port: process.append('\t\t\tobj_ref := Pack_String_To_Vhpi_String("'+item.split(':')[0]+'");\n') process.append('\t\t\tVhpi_Get_Port_Value(obj_ref,'+item.split(':')[0]+'_v,'+item.split(':')[1]+');\n') process.append('\t\t\tassert false report "Get port value '+item.split(':')[0]+' returns " &'+item.split(':')[0]+'_v severity note;\n') process.append('\t\t\t'+item.split(':')[0]+' <= Unpack_String('+item.split(':')[0]+'_v,'+item.split(':')[1]+');\n') process.append("\n") process.append('\t\t\twait for 1 us;\n') for item in output_port: process.append('\t\t\t'+item.split(':')[0]+'_v := Pack_String_To_Vhpi_String(Convert_SLV_To_String('+item.split(':')[0]+'));\n') process.append('\t\t\tobj_ref := Pack_String_To_Vhpi_String("'+item.split(':')[0]+'");\n') process.append('\t\t\tVhpi_Set_Port_Value(obj_ref,'+item.split(':')[0]+'_v,'+item.split(':')[1]+');\n') process.append('\t\t\tassert false report "Set port value '+item.split(':')[0]+' returns " &'+item.split(':')[0]+'_v severity note;\n') process.append("\n") process.append("\t\tend loop;\n") process.append("\tend process;\n\n") process.append("end architecture;") #Writing all the components to testbench file testbench.write(comment_vhdl) testbench.write(tb_header) testbench.write(tb_entity) testbench.write(arch) for item in components: testbench.write(item) for item in signals: testbench.write(item) testbench.write("\n\n") testbench.write("begin\n\n") for item in map: testbench.write(item) testbench.write("\n\t"+tb_clk) for item in process_Vhpi: testbench.write(item) for item in process: testbench.write(item) testbench.close() ##################################### Creating and writing components in start_server.sh ################################ start_server = open('start_server.sh','w') start_server.write("#!/bin/bash\n\n") start_server.write("###This server run ghdl testebench for infinite time till ngspice send END signal to stop it\n\n") start_server.write("#gcc -c ghdlserver.c\n") start_server.write("#ghdl -a Utility_Package.vhdl &&\n") start_server.write("#ghdl -a Vhpi_Package.vhdl &&\n") start_server.write("cd "+home+"/ngspice-nghdl/src/xspice/icm/ghdl/"+fname.split('.')[0]+"/DUTghdl/\n") start_server.write("chmod 775 sock_pkg_create.sh &&\n") start_server.write("./sock_pkg_create.sh $1 &&\n") start_server.write("ghdl -a sock_pkg.vhdl &&\n") start_server.write("ghdl -a "+fname+" &&\n") start_server.write("ghdl -a "+fname.split('.')[0]+"_tb.vhdl &&\n") start_server.write("ghdl -e -Wl,ghdlserver.o "+fname.split('.')[0]+"_tb &&\n") start_server.write("./"+fname.split('.')[0]+"_tb") start_server.close() ##################################### Creating and writing in sock_pkg_create.sh ######################################## sock_pkg_create = open('sock_pkg_create.sh','w') sock_pkg_create.write("#!/bin/bash\n\n") sock_pkg_create.write("##This file create sock_pkg_create.vhdl file and set the instance id from parameter based on parameter\n\n") sock_pkg_create.write("echo \"library ieee;\n") sock_pkg_create.write("package sock_pkg is\n") sock_pkg_create.write("\tfunction sock_pkg_fun return integer;\n") sock_pkg_create.write("end;\n\n") sock_pkg_create.write("\tpackage body sock_pkg is\n") sock_pkg_create.write("\t function sock_pkg_fun return integer is") sock_pkg_create.write("\t\tvariable sock_id : integer;\n") sock_pkg_create.write("\t\t\tbegin\n") sock_pkg_create.write("\t\t\t\tsock_id := $1;\n") sock_pkg_create.write("\t\t\t\treturn sock_id;\n") sock_pkg_create.write("\t\t\tend function;\n") sock_pkg_create.write("\t\tend package body;\" > sock_pkg.vhdl")