From d8423a5909a5bbac9b17761a1ea844cb2ca401a0 Mon Sep 17 00:00:00 2001 From: Bladen Martin Date: Tue, 14 Jul 2020 11:45:06 +0530 Subject: OS - independent with Windows compatability --- src/createKicadLibrary.py | 543 +++++----- src/model_generation.py | 2564 ++++++++++++++++++++------------------------- src/ngspice_ghdl.py | 32 +- 3 files changed, 1403 insertions(+), 1736 deletions(-) (limited to 'src') diff --git a/src/createKicadLibrary.py b/src/createKicadLibrary.py index 966c9d6..2b3e7d7 100644 --- a/src/createKicadLibrary.py +++ b/src/createKicadLibrary.py @@ -1,269 +1,274 @@ -from Appconfig import Appconfig -import re -import os -import xml.etree.cElementTree as ET -from PyQt4 import QtGui - - -class AutoSchematic(QtGui.QWidget): - - def __init__(self, modelname): - QtGui.QWidget.__init__(self) - self.modelname = modelname.split('.')[0] - self.template = Appconfig.kicad_lib_template.copy() - self.xml_loc = Appconfig.xml_loc - self.lib_loc = Appconfig.lib_loc - self.kicad_nghdl_lib = '/usr/share/kicad/library/eSim_Nghdl.lib' - self.parser = Appconfig.parser_nghdl - - def createKicadLibrary(self): - xmlFound = None - for root, dirs, files in os.walk(self.xml_loc): - if (str(self.modelname) + '.xml') in files: - xmlFound = root - print(xmlFound) - if xmlFound is None: - self.getPortInformation() - self.createXML() - self.createLib() - elif (xmlFound == self.xml_loc + '/Nghdl'): - print('Library already exists...') - ret = QtGui.QMessageBox.warning( - self, "Warning", '''Library files for this model ''' + - '''already exist. Do you want to overwrite it?
- If yes press ok, else cancel it and ''' + - '''change the name of your vhdl file.''', - QtGui.QMessageBox.Ok, QtGui.QMessageBox.Cancel - ) - if ret == QtGui.QMessageBox.Ok: - print("Overwriting existing libraries") - self.getPortInformation() - self.createXML() - self.removeOldLibrary() # Removes the exisitng library - self.createLib() - else: - print("Exiting Nghdl") - quit() - else: - print('Pre existing library...') - ret = QtGui.QMessageBox.critical( - self, "Error", '''A standard library already exists ''' + - '''with this name.
Please change the name ''' + - '''of your vhdl file and upload it again''', - QtGui.QMessageBox.Ok - ) - - # quit() - - def getPortInformation(self): - portInformation = PortInfo(self) - portInformation.getPortInfo() - self.portInfo = portInformation.bit_list - self.input_length = portInformation.input_len - - def createXML(self): - cwd = os.getcwd() - xmlDestination = os.path.join(self.xml_loc, 'Nghdl') - self.splitText = "" - for bit in self.portInfo[:-1]: - self.splitText += bit + "-V:" - self.splitText += self.portInfo[-1] + "-V" - - print("changing directory to ", xmlDestination) - os.chdir(xmlDestination) - - root = ET.Element("model") - ET.SubElement(root, "name").text = self.modelname - ET.SubElement(root, "type").text = "Nghdl" - ET.SubElement(root, "node_number").text = str(len(self.portInfo)) - ET.SubElement(root, "title").text = ( - "Add parameters for " + str(self.modelname)) - ET.SubElement(root, "split").text = self.splitText - param = ET.SubElement(root, "param") - ET.SubElement(param, "rise_delay", default="1.0e-9").text = ( - "Enter Rise Delay (default=1.0e-9)") - ET.SubElement(param, "fall_delay", default="1.0e-9").text = ( - "Enter Fall Delay (default=1.0e-9)") - ET.SubElement(param, "input_load", default="1.0e-12").text = ( - "Enter Input Load (default=1.0e-12)") - ET.SubElement(param, "instance_id", default="1").text = ( - "Enter Instance ID (Between 0-99)") - tree = ET.ElementTree(root) - tree.write(str(self.modelname) + '.xml') - print("Leaving the directory ", xmlDestination) - os.chdir(cwd) - - # Calculates the maximum between input and output ports - def findBlockSize(self): - ind = self.input_length - return max( - self.char_sum(self.portInfo[:ind]), - self.char_sum(self.portInfo[ind:]) - ) - - def char_sum(self, ls): - return sum([int(x) for x in ls]) - - def removeOldLibrary(self): - cwd = os.getcwd() - os.chdir(self.lib_loc) - print("Changing directory to ", self.lib_loc) - f = open(self.kicad_nghdl_lib) - lines = f.readlines() - f.close() - - output = [] - line_reading_flag = False - - for line in lines: - if line.startswith("DEF"): - if line.split()[1] == self.modelname: - line_reading_flag = True - if not line_reading_flag: - output.append(line) - if line.startswith("ENDDEF"): - line_reading_flag = False - - f = open(self.kicad_nghdl_lib, 'w') - for line in output: - f.write(line) - - os.chdir(cwd) - print("Leaving directory, ", self.lib_loc) - - def createLib(self): - self.dist_port = 100 # Distance between two ports - self.inc_size = 100 # Increment size of a block - cwd = os.getcwd() - os.chdir(self.lib_loc) - print("Changing directory to ", self.lib_loc) - - lib_file = open(self.kicad_nghdl_lib, "a") - line1 = self.template["start_def"] - line1 = line1.split() - line1 = [w.replace('comp_name', self.modelname) for w in line1] - self.template["start_def"] = ' '.join(line1) - if os.stat(self.kicad_nghdl_lib).st_size == 0: - lib_file.write("EESchema-LIBRARY Version 2.3" + "\n\n") - # lib_file.write("#encoding utf-8"+ "\n"+ "#"+ "\n" + - # "#test_compo" + "\n"+ "#"+ "\n") - lib_file.write( - self.template["start_def"] + "\n" + self.template["U_field"]+"\n" - ) - - line3 = self.template["comp_name_field"] - line3 = line3.split() - line3 = [w.replace('comp_name', self.modelname) for w in line3] - self.template["comp_name_field"] = ' '.join(line3) - - lib_file.write(self.template["comp_name_field"] + "\n") - - line4 = self.template["blank_field"] - line4_1 = line4[0] - line4_2 = line4[1] - line4_1 = line4_1.split() - line4_1 = [w.replace('blank_quotes', '""') for w in line4_1] - line4_2 = line4_2.split() - line4_2 = [w.replace('blank_quotes', '""') for w in line4_2] - line4[0] = ' '.join(line4_1) - line4[1] = ' '.join(line4_2) - self.template["blank_qoutes"] = line4 - - lib_file.write( - line4[0] + "\n" + line4[1] + "\n" + - self.template["start_draw"] + "\n" - ) - - draw_pos = self.template["draw_pos"] - draw_pos = draw_pos.split() - draw_pos[4] = str( - int(draw_pos[4]) - self.findBlockSize() * self.inc_size) - self.template["draw_pos"] = ' '.join(draw_pos) - - lib_file.write(self.template["draw_pos"]+"\n") - - input_port = self.template["input_port"] - input_port = input_port.split() - output_port = self.template["output_port"] - output_port = output_port.split() - inputs = self.portInfo[0: self.input_length] - outputs = self.portInfo[self.input_length:] - - print("INPUTS AND OUTPUTS ") - print(inputs) - print(outputs) - - inputs = self.char_sum(inputs) - outputs = self.char_sum(outputs) - - total = inputs+outputs - - port_list = [] - - for i in range(total): - if (i < inputs): - input_port[1] = "in" + str(i + 1) - input_port[2] = str(i + 1) - input_port[4] = str(int(input_port[4]) - self.dist_port) - input_list = ' '.join(input_port) - port_list.append(input_list) - - else: - output_port[1] = "out" + str(i - inputs + 1) - output_port[2] = str(i + 1) - output_port[4] = str(int(output_port[4]) - self.dist_port) - output_list = ' '.join(output_port) - port_list.append(output_list) - - for ports in port_list: - lib_file.write(ports+"\n") - lib_file.write( - self.template["end_draw"] + "\n" + - self.template["end_def"] + "\n\n\n" - ) - - os.chdir(cwd) - print('Leaving directory, ', self.lib_loc) - QtGui.QMessageBox.information( - self, "Library added", - '''Library details for this model is added to the ''' + - '''eSim_Nghdl.lib in the KiCad shared directory''', - QtGui.QMessageBox.Ok - ) - - -class PortInfo: - def __init__(self, model): - self.modelname = model.modelname - self.model_loc = model.parser.get('NGSPICE', 'DIGITAL_MODEL') - self.bit_list = [] - self.input_len = 0 - - def getPortInfo(self): - info_loc = os.path.join(self.model_loc, self.modelname+'/DUTghdl/') - input_list = [] - output_list = [] - read_file = open(info_loc + 'connection_info.txt', 'r') - data = read_file.readlines() - read_file.close() - - for line in data: - if re.match(r'^\s*$', line): - pass - else: - in_items = re.findall( - "IN", line, re.MULTILINE | re.IGNORECASE - ) - out_items = re.findall( - "OUT", line, re.MULTILINE | re.IGNORECASE - ) - if in_items: - input_list.append(line.split()) - if out_items: - output_list.append(line.split()) - - for in_list in input_list: - self.bit_list.append(in_list[2]) - self.input_len = len(self.bit_list) - for out_list in output_list: - self.bit_list.append(out_list[2]) +from Appconfig import Appconfig +import re +import os +import xml.etree.cElementTree as ET +from PyQt4 import QtGui + + +class AutoSchematic(QtGui.QWidget): + + def __init__(self, modelname): + QtGui.QWidget.__init__(self) + self.modelname = modelname.split('.')[0] + self.template = Appconfig.kicad_lib_template.copy() + self.xml_loc = Appconfig.xml_loc + self.lib_loc = Appconfig.lib_loc + if os.name == 'nt': + eSim_src = Appconfig.src_home + inst_dir = eSim_src.replace('\eSim', '') + self.kicad_nghdl_lib = inst_dir + '/KiCad/share/kicad/library/eSim_Nghdl.lib' + else: + self.kicad_nghdl_lib = '/usr/share/kicad/library/eSim_Nghdl.lib' + self.parser = Appconfig.parser_nghdl + + def createKicadLibrary(self): + xmlFound = None + for root, dirs, files in os.walk(self.xml_loc): + if (str(self.modelname) + '.xml') in files: + xmlFound = root + print(xmlFound) + if xmlFound is None: + self.getPortInformation() + self.createXML() + self.createLib() + elif (xmlFound == os.path.join(self.xml_loc, 'Nghdl')): + print('Library already exists...') + ret = QtGui.QMessageBox.warning( + self, "Warning", '''Library files for this model ''' + + '''already exist. Do you want to overwrite it?
+ If yes press ok, else cancel it and ''' + + '''change the name of your vhdl file.''', + QtGui.QMessageBox.Ok, QtGui.QMessageBox.Cancel + ) + if ret == QtGui.QMessageBox.Ok: + print("Overwriting existing libraries") + self.getPortInformation() + self.createXML() + self.removeOldLibrary() # Removes the exisitng library + self.createLib() + else: + print("Exiting Nghdl") + quit() + else: + print('Pre existing library...') + ret = QtGui.QMessageBox.critical( + self, "Error", '''A standard library already exists ''' + + '''with this name.
Please change the name ''' + + '''of your vhdl file and upload it again''', + QtGui.QMessageBox.Ok + ) + + # quit() + + def getPortInformation(self): + portInformation = PortInfo(self) + portInformation.getPortInfo() + self.portInfo = portInformation.bit_list + self.input_length = portInformation.input_len + + def createXML(self): + cwd = os.getcwd() + xmlDestination = os.path.join(self.xml_loc, 'Nghdl') + self.splitText = "" + for bit in self.portInfo[:-1]: + self.splitText += bit + "-V:" + self.splitText += self.portInfo[-1] + "-V" + + print("changing directory to ", xmlDestination) + os.chdir(xmlDestination) + + root = ET.Element("model") + ET.SubElement(root, "name").text = self.modelname + ET.SubElement(root, "type").text = "Nghdl" + ET.SubElement(root, "node_number").text = str(len(self.portInfo)) + ET.SubElement(root, "title").text = ( + "Add parameters for " + str(self.modelname)) + ET.SubElement(root, "split").text = self.splitText + param = ET.SubElement(root, "param") + ET.SubElement(param, "rise_delay", default="1.0e-9").text = ( + "Enter Rise Delay (default=1.0e-9)") + ET.SubElement(param, "fall_delay", default="1.0e-9").text = ( + "Enter Fall Delay (default=1.0e-9)") + ET.SubElement(param, "input_load", default="1.0e-12").text = ( + "Enter Input Load (default=1.0e-12)") + ET.SubElement(param, "instance_id", default="1").text = ( + "Enter Instance ID (Between 0-99)") + tree = ET.ElementTree(root) + tree.write(str(self.modelname) + '.xml') + print("Leaving the directory ", xmlDestination) + os.chdir(cwd) + + # Calculates the maximum between input and output ports + def findBlockSize(self): + ind = self.input_length + return max( + self.char_sum(self.portInfo[:ind]), + self.char_sum(self.portInfo[ind:]) + ) + + def char_sum(self, ls): + return sum([int(x) for x in ls]) + + def removeOldLibrary(self): + cwd = os.getcwd() + os.chdir(self.lib_loc) + print("Changing directory to ", self.lib_loc) + f = open(self.kicad_nghdl_lib) + lines = f.readlines() + f.close() + + output = [] + line_reading_flag = False + + for line in lines: + if line.startswith("DEF"): + if line.split()[1] == self.modelname: + line_reading_flag = True + if not line_reading_flag: + output.append(line) + if line.startswith("ENDDEF"): + line_reading_flag = False + + f = open(self.kicad_nghdl_lib, 'w') + for line in output: + f.write(line) + + os.chdir(cwd) + print("Leaving directory, ", self.lib_loc) + + def createLib(self): + self.dist_port = 100 # Distance between two ports + self.inc_size = 100 # Increment size of a block + cwd = os.getcwd() + os.chdir(self.lib_loc) + print("Changing directory to ", self.lib_loc) + + lib_file = open(self.kicad_nghdl_lib, "a") + line1 = self.template["start_def"] + line1 = line1.split() + line1 = [w.replace('comp_name', self.modelname) for w in line1] + self.template["start_def"] = ' '.join(line1) + if os.stat(self.kicad_nghdl_lib).st_size == 0: + lib_file.write("EESchema-LIBRARY Version 2.3" + "\n\n") + # lib_file.write("#encoding utf-8"+ "\n"+ "#"+ "\n" + + # "#test_compo" + "\n"+ "#"+ "\n") + lib_file.write( + self.template["start_def"] + "\n" + self.template["U_field"]+"\n" + ) + + line3 = self.template["comp_name_field"] + line3 = line3.split() + line3 = [w.replace('comp_name', self.modelname) for w in line3] + self.template["comp_name_field"] = ' '.join(line3) + + lib_file.write(self.template["comp_name_field"] + "\n") + + line4 = self.template["blank_field"] + line4_1 = line4[0] + line4_2 = line4[1] + line4_1 = line4_1.split() + line4_1 = [w.replace('blank_quotes', '""') for w in line4_1] + line4_2 = line4_2.split() + line4_2 = [w.replace('blank_quotes', '""') for w in line4_2] + line4[0] = ' '.join(line4_1) + line4[1] = ' '.join(line4_2) + self.template["blank_qoutes"] = line4 + + lib_file.write( + line4[0] + "\n" + line4[1] + "\n" + + self.template["start_draw"] + "\n" + ) + + draw_pos = self.template["draw_pos"] + draw_pos = draw_pos.split() + draw_pos[4] = str( + int(draw_pos[4]) - self.findBlockSize() * self.inc_size) + self.template["draw_pos"] = ' '.join(draw_pos) + + lib_file.write(self.template["draw_pos"]+"\n") + + input_port = self.template["input_port"] + input_port = input_port.split() + output_port = self.template["output_port"] + output_port = output_port.split() + inputs = self.portInfo[0: self.input_length] + outputs = self.portInfo[self.input_length:] + + print("INPUTS AND OUTPUTS ") + print(inputs) + print(outputs) + + inputs = self.char_sum(inputs) + outputs = self.char_sum(outputs) + + total = inputs+outputs + + port_list = [] + + for i in range(total): + if (i < inputs): + input_port[1] = "in" + str(i + 1) + input_port[2] = str(i + 1) + input_port[4] = str(int(input_port[4]) - self.dist_port) + input_list = ' '.join(input_port) + port_list.append(input_list) + + else: + output_port[1] = "out" + str(i - inputs + 1) + output_port[2] = str(i + 1) + output_port[4] = str(int(output_port[4]) - self.dist_port) + output_list = ' '.join(output_port) + port_list.append(output_list) + + for ports in port_list: + lib_file.write(ports+"\n") + lib_file.write( + self.template["end_draw"] + "\n" + + self.template["end_def"] + "\n\n\n" + ) + + os.chdir(cwd) + print('Leaving directory, ', self.lib_loc) + QtGui.QMessageBox.information( + self, "Library added", + '''Library details for this model is added to the ''' + + '''eSim_Nghdl.lib in the KiCad shared directory''', + QtGui.QMessageBox.Ok + ) + + +class PortInfo: + def __init__(self, model): + self.modelname = model.modelname + self.model_loc = model.parser.get('NGSPICE', 'DIGITAL_MODEL') + self.bit_list = [] + self.input_len = 0 + + def getPortInfo(self): + info_loc = os.path.join(self.model_loc, self.modelname+'/DUTghdl/') + input_list = [] + output_list = [] + read_file = open(info_loc + 'connection_info.txt', 'r') + data = read_file.readlines() + read_file.close() + + for line in data: + if re.match(r'^\s*$', line): + pass + else: + in_items = re.findall( + "IN", line, re.MULTILINE | re.IGNORECASE + ) + out_items = re.findall( + "OUT", line, re.MULTILINE | re.IGNORECASE + ) + if in_items: + input_list.append(line.split()) + if out_items: + output_list.append(line.split()) + + for in_list in input_list: + self.bit_list.append(in_list[2]) + self.input_len = len(self.bit_list) + for out_list in output_list: + self.bit_list.append(out_list[2]) diff --git a/src/model_generation.py b/src/model_generation.py index 305ced8..7baecc1 100644 --- a/src/model_generation.py +++ b/src/model_generation.py @@ -1,1450 +1,1114 @@ -#!/usr/bin/python3 - -import re -import os -from configparser import SafeConfigParser - - -class ModelGeneration: - - def __init__(self, file): - - # Script starts from here - print("Arguement is : ", file) - self.fname = os.path.basename(file) - print("VHDL filename is : ", self.fname) - self.home = os.path.expanduser("~") - self.parser = SafeConfigParser() - self.parser.read(os.path.join( - self.home, os.path.join('.nghdl', 'config.ini'))) - self.ngspice_home = self.parser.get('NGSPICE', 'NGSPICE_HOME') - self.release_dir = self.parser.get('NGSPICE', 'RELEASE') - self.src_home = self.parser.get('SRC', 'SRC_HOME') - self.licensefile = self.parser.get('SRC', 'LICENSE') - - # #### Creating connection_info.txt file from vhdl file #### # - read_vhdl = open(file, 'r') - vhdl_data = read_vhdl.readlines() - read_vhdl.close() - - start_flag = -1 # Used for scaning part of data - scan_data = [] - # p=re.search('port(.*?)end',read_vhdl,re.M|re.I|re.DOTALL).group() - - for item in vhdl_data: - if re.search('port', item, re.I): - start_flag = 1 - - elif re.search("end", item, re.I): - start_flag = 0 - - if start_flag == 1: - item = re.sub("port", " ", item, flags=re.I) - item = re.sub("\(", " ", item, flags=re.I) # noqa - item = re.sub("\)", " ", item, flags=re.I) # noqa - item = re.sub(";", " ", item, flags=re.I) - - scan_data.append(item.rstrip()) - scan_data = [_f for _f in scan_data if _f] - elif start_flag == 0: - break - - port_info = [] - self.port_vector_info = [] - - for item in scan_data: - print("Scan Data :", item) - if re.search("in", item, flags=re.I): - if re.search("std_logic_vector", item, flags=re.I): - temp = re.compile(r"\s*std_logic_vector\s*", flags=re.I) - elif re.search("std_logic", item, flags=re.I): - temp = re.compile(r"\s*std_logic\s*", flags=re.I) - else: - raise ValueError("Please check your vhdl " + - "code for datatype of input port") - elif re.search("out", item, flags=re.I): - if re.search("std_logic_vector", item, flags=re.I): - temp = re.compile(r"\s*std_logic_vector\s*", flags=re.I) - elif re.search("std_logic", item, flags=re.I): - temp = re.compile(r"\s*std_logic\s*", flags=re.I) - else: - raise ValueError("Please check your vhdl " + - "code for datatype of output port") - else: - raise ValueError( - "Please check the in/out direction of your port" - ) - - lhs = temp.split(item)[0] - rhs = temp.split(item)[1] - bit_info = re.compile(r"\s*downto\s*", flags=re.I).split(rhs)[0] - if bit_info: - port_info.append(lhs + ":" + str(int(bit_info) + int(1))) - self.port_vector_info.append(1) - else: - port_info.append(lhs + ":" + str(int(1))) - self.port_vector_info.append(0) - - print("Port Info :", port_info) - - # Open connection_info.txt file - con_ifo = open('connection_info.txt', 'w') - - for item in port_info: - word = item.split(':') - con_ifo.write( - word[0].strip() + ' ' + word[1].strip() + ' ' + word[2].strip() - ) - con_ifo.write("\n") - con_ifo.close() - - def readPortInfo(self): - - # ############## Reading connection/port information ############## # - - # Declaring input and output list - input_list = [] - output_list = [] - - # Reading connection_info.txt file for port infomation - read_file = open('connection_info.txt', 'r') - data = read_file.readlines() - read_file.close() - - # Extracting input and output port list from data - print("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx") - for line in data: - print(line) - if re.match(r'^\s*$', line): - pass - else: - in_items = re.findall( - "IN", line, re.MULTILINE | re.IGNORECASE - ) - out_items = re.findall( - "OUT", line, re.MULTILINE | re.IGNORECASE - ) - if in_items: - input_list.append(line.split()) - - if out_items: - output_list.append(line.split()) - - print("Inout List :", input_list) - print("Output list", output_list) - - self.input_port = [] - self.output_port = [] - - # creating list of input and output port with its weight - for input in input_list: - self.input_port.append(input[0]+":"+input[2]) - for output in output_list: - self.output_port.append(output[0]+":"+output[2]) - - print("Output Port List : ", self.output_port) - print("Input Port List : ", self.input_port) - -#08.June.2020 - BM - If OS is Windows, write Windows socket version of cfunc.mod, else write Linux(BSD) socket version - if os.name == 'nt': - def createCfuncModFile(self): - - # ## Creating content for cfunc.mod file ## # - - print("Starting With cfunc.mod file") - cfunc = open('cfunc.mod', 'w') - print("Building content for cfunc.mod file") - - comment = '''/* This is cfunc.mod file auto generated by gen_con_info.py - Developed by Fahim, Rahul at IIT Bombay */\n - ''' - - header = ''' - #include - #include - #include - #include - #include - #include - #include - #include - - #undef BOOLEAN - #include - ''' - - function_open = ( - '''void cm_''' + self.fname.split('.')[0] + '''(ARGS) \n{''') - - digital_state_output = [] - for item in self.output_port: - digital_state_output.append( - "Digital_State_t *_op_" + item.split(':')[0] + - ", *_op_" + item.split(':')[0] + "_old;" - ) - - var_section = ''' - // Declaring components of Client - FILE *log_client = NULL; - log_client=fopen("client.log","a"); - int bytes_recieved; - char send_data[1024]; - char recv_data[1024]; - char *key_iter; - struct hostent *host; - struct sockaddr_in server_addr; - int sock_port = 5000+PARAM(instance_id); - ''' - - temp_input_var = [] - for item in self.input_port: - temp_input_var.append( - "char temp_" + item.split(':')[0] + "[1024];" - ) - - # Start of INIT function - init_start_function = ''' - if(INIT) - { - /* Allocate storage for output ports ''' \ - '''and set the load for input ports */ - ''' - - cm_event_alloc = [] - cm_count_output = 0 - for item in self.output_port: - cm_event_alloc.append( - "cm_event_alloc(" + - str(cm_count_output) + "," + item.split(':')[1] + - "*sizeof(Digital_State_t));" - ) - cm_count_output = cm_count_output + 1 - - load_in_port = [] - for item in self.input_port: - load_in_port.append( - "for(Ii=0;Iih_addr); - bzero(&(server_addr.sin_zero),8); - - ''' - - connect_server = ''' - fprintf(log_client,"Client-Connecting to server \\n"); - - //Connecting to server - int try_limit=10; - while(try_limit>0) - { - if (connect(socket_fd, (struct sockaddr*)&server_addr,''' \ - '''sizeof(struct sockaddr)) == -1) - { - sleep(1); - try_limit--; - if(try_limit==0) - { - fprintf(stderr,"Connect- Error:Tried to connect server on port,''' \ - '''failed...giving up \\n"); - fprintf(log_client,"Connect- Error:Tried to connect server on ''' \ - '''port, failed...giving up \\n"); - exit(1); - } - } - else - { - printf("Client-Connected to server \\n"); - fprintf(log_client,"Client-Connected to server \\n"); - break; - } - } - ''' - - # Assign bit value to every input - assign_data_to_input = [] - for item in self.input_port: - assign_data_to_input.append("\tfor(Ii=0;Ii - #include - #include - #include - #include - #include - #include - #include - #include - #include - #include - ''' - - function_open = ( - '''void cm_''' + self.fname.split('.')[0] + '''(ARGS) \n{''') - - digital_state_output = [] - for item in self.output_port: - digital_state_output.append( - "Digital_State_t *_op_" + item.split(':')[0] + - ", *_op_" + item.split(':')[0] + "_old;" - ) - - var_section = ''' - // Declaring components of Client - FILE *log_client = NULL; - log_client=fopen("client.log","a"); - int socket_fd, bytes_recieved; - char send_data[1024]; - char recv_data[1024]; - char *key_iter; - struct hostent *host; - struct sockaddr_in server_addr; - int sock_port = 5000+PARAM(instance_id); - ''' - - temp_input_var = [] - for item in self.input_port: - temp_input_var.append( - "char temp_" + item.split(':')[0] + "[1024];" - ) - - # Start of INIT function - init_start_function = ''' - if(INIT) - { - /* Allocate storage for output ports ''' \ - '''and set the load for input ports */ - ''' - - cm_event_alloc = [] - cm_count_output = 0 - for item in self.output_port: - cm_event_alloc.append( - "cm_event_alloc(" + - str(cm_count_output) + "," + item.split(':')[1] + - "*sizeof(Digital_State_t));" - ) - cm_count_output = cm_count_output + 1 - - load_in_port = [] - for item in self.input_port: - load_in_port.append( - "for(Ii=0;Iih_addr); - bzero(&(server_addr.sin_zero),8); - ''' - - connect_server = ''' - fprintf(log_client,"Client-Connecting to server \\n"); - //Connecting to server - int try_limit=10; - while(try_limit>0) - { - if (connect(socket_fd, (struct sockaddr*)&server_addr,''' \ - '''sizeof(struct sockaddr)) == -1) - { - sleep(1); - try_limit--; - if(try_limit==0) - { - fprintf(stderr,"Connect- Error:Tried to connect server on port,''' \ - '''failed...giving up \\n"); - fprintf(log_client,"Connect- Error:Tried to connect server on ''' \ - '''port, failed...giving up \\n"); - exit(1); - } - } - else - { - printf("Client-Connected to server \\n"); - fprintf(log_client,"Client-Connected to server \\n"); - break; - } - } - ''' - - # Assign bit value to every input - assign_data_to_input = [] - for item in self.input_port: - assign_data_to_input.append("\tfor(Ii=0;Ii " + item.split(':')[0] + ",\n") - - for item in self.output_port: - if self.output_port.index(item) == len(self.output_port) - 1: - map.append("\t\t\t\t" + item.split(':')[0] + - " => " + item.split(':')[0] + "\n") - else: - map.append("\t\t\t\t" + item.split(':')[0] + - " => " + item.split(':')[0] + ",\n") - map.append("\t\t\t);") - - # Testbench Clock - tb_clk = "clk_s <= not clk_s after 5 us;\n\n" - - # Adding Process block for Vhpi - process_Vhpi = [] - process_Vhpi.append( - "process\n\t\tvariable sock_port : integer;" + - "\n\t\ttype string_ptr is access string;" + - "\n\t\tvariable sock_ip : string_ptr;" + - "\n\t\tbegin\n\t\tsock_port := sock_port_fun;" + - "\n\t\tsock_ip := new string'(sock_ip_fun);" + - "\n\t\tVhpi_Initialize(sock_port," + - "Pack_String_To_Vhpi_String(sock_ip.all));" + - "\n\t\twait until clk_s = '1';" + - "\n\t\twhile true loop\n\t\t\twait until clk_s = '0';" + - "\n\t\t\tVhpi_Listen;\n\t\t\twait for 1 us;\n\t\t\t" + - "Vhpi_Send;" + - "\n\t\tend loop;\n\t\twait;\n\tend process;\n\n" - ) - - # Adding process block - process = [] - process.append("\tprocess\n") - process.append("\t\tvariable count : integer:=0;\n") - - for item in self.input_port: - process.append( - "\t\tvariable " + item.split(':')[0] + "_v : VhpiString;\n" - ) - - for item in self.output_port: - process.append( - "\t\tvariable " + item.split(':')[0] + "_v : VhpiString;\n" - ) - - process.append("\t\tvariable obj_ref : VhpiString;\n") - process.append("\tbegin\n") - process.append("\t\twhile true loop\n") - process.append("\t\t\twait until clk_s = '0';\n\n") - - port_vector_count = 0 - - for item in self.input_port: - process.append( - '\t\t\tobj_ref := Pack_String_To_Vhpi_String("' + - item.split(':')[0] + '");\n' - ) - process.append( - '\t\t\tVhpi_Get_Port_Value(obj_ref,' + - item.split(':')[0] + '_v,' + item.split(':')[1] + ');\n' - ) - - if self.port_vector_info[port_vector_count]: - process.append( - '\t\t\t' + item.split(':')[0] + - ' <= Unpack_String(' + item.split(':')[0] + '_v,' + - item.split(':')[1] + ');\n' - ) - else: - process.append( - '\t\t\t' + item.split(':')[0] + - ' <= To_Std_Logic('+item.split(':')[0]+'_v'+');\n' - ) - - port_vector_count += 1 - process.append("\n") - - process.append('\t\t\twait for 1 us;\n') - - for item in self.output_port: - if self.port_vector_info[port_vector_count]: - process.append( - '\t\t\t' + item.split(':')[0] + - '_v := Pack_String_To_Vhpi_String' + - '(Convert_SLV_To_String(' + - item.split(':')[0]+'));\n' - ) - else: - process.append( - '\t\t\t' + item.split(':')[0] + - '_v := Pack_String_To_Vhpi_String(To_String(' + - item.split(':')[0]+'));\n' - ) - - port_vector_count += 1 - - process.append( - '\t\t\tobj_ref := Pack_String_To_Vhpi_String("' + - item.split(':')[0]+'");\n' - ) - process.append( - '\t\t\tVhpi_Set_Port_Value(obj_ref,' + - item.split(':')[0] + '_v,' + item.split(':')[1] + ');\n' - ) - process.append("\n") - - process.append( - '\t\t\treport "Iteration - "' + - "& integer'image(count) severity note;\n" - ) - process.append('\t\t\tcount := count + 1;\n') - process.append("\t\tend loop;\n") - process.append("\tend process;\n\n") - process.append("end architecture;") - - # Writing all the components to testbench file - testbench.write(comment_vhdl) - testbench.write(tb_header) - testbench.write(tb_entity) - testbench.write(arch) - - for item in components: - testbench.write(item) - - for item in signals: - testbench.write(item) - - testbench.write("\n\n") - - testbench.write("begin\n\n") - - for item in map: - testbench.write(item) - - testbench.write("\n\t"+tb_clk) - - for item in process_Vhpi: - testbench.write(item) - - for item in process: - testbench.write(item) - - testbench.close() - - def createServerScript(self): - - # ####### Creating and writing components in start_server.sh ####### # - self.digital_home = self.parser.get('NGSPICE', 'DIGITAL_MODEL') - - start_server = open('start_server.sh', 'w') - - start_server.write("#!/bin/bash\n\n") - start_server.write( - "###This server run ghdl testebench for infinite time till " + - "ngspice send END signal to stop it\n\n" - ) - #08.June.2020 - BM - Use correct path with respect to particular OS - if os.name == 'nt': - pathstr = self.digital_home + "/" + \ - self.fname.split('.')[0] + "/DUTghdl/" - pathstr = pathstr.replace("\\", "/") - start_server.write("cd "+pathstr+"\n") - else: - start_server.write("cd "+self.digital_home + - "/" + self.fname.split('.')[0] + "/DUTghdl/\n") - start_server.write("chmod 775 sock_pkg_create.sh &&\n") - start_server.write("./sock_pkg_create.sh $1 $2 &&\n") - start_server.write("ghdl -i *.vhdl &&\n") - start_server.write("ghdl -a *.vhdl &&\n") - start_server.write("ghdl -a "+self.fname+" &&\n") - start_server.write( - "ghdl -a "+self.fname.split('.')[0]+"_tb.vhdl &&\n" - ) - #08.June.2020 - BM - If OS i Windows, link server with libws2_32.a - if os.name == 'nt': - start_server.write("ghdl -e -Wl,ghdlserver.o " + - "-Wl,libws2_32.a " + self.fname.split('.')[0] + "_tb &&\n") - start_server.write("./"+self.fname.split('.')[0]+"_tb.exe") - else: - start_server.write("ghdl -e -Wl,ghdlserver.o " + - self.fname.split('.')[0] + "_tb &&\n") - start_server.write("./"+self.fname.split('.')[0]+"_tb") - - start_server.close() - - def createSockScript(self): - - # ########### Creating and writing in sock_pkg_create.sh ########### # - - sock_pkg_create = open('sock_pkg_create.sh', 'w') - - sock_pkg_create.write("#!/bin/bash\n\n") - sock_pkg_create.write( - "##This file creates sock_pkg.vhdl file and sets the port " + - "and ip from parameters passed to it\n\n" - ) - sock_pkg_create.write("echo \"library ieee;\n") - sock_pkg_create.write("package sock_pkg is\n") - sock_pkg_create.write("\tfunction sock_port_fun return integer;\n") - sock_pkg_create.write("\tfunction sock_ip_fun return string;\n") - sock_pkg_create.write("end;\n\n") - sock_pkg_create.write("package body sock_pkg is\n") - sock_pkg_create.write("\tfunction sock_port_fun return integer is\n") - sock_pkg_create.write("\t\tvariable sock_port : integer;\n") - sock_pkg_create.write("\t\t\tbegin\n") - sock_pkg_create.write("\t\t\t\tsock_port := $1;\n") - sock_pkg_create.write("\t\t\t\treturn sock_port;\n") - sock_pkg_create.write("\t\t\tend function;\n\n") - sock_pkg_create.write("\tfunction sock_ip_fun return string is\n") - sock_pkg_create.write("\t\ttype string_ptr is access string;\n") - sock_pkg_create.write("\t\tvariable sock_ip : string_ptr;\n") - sock_pkg_create.write("\t\t\tbegin\n") - sock_pkg_create.write('\t\t\t\tsock_ip := new string\'(\\"$2\\");\n') - sock_pkg_create.write("\t\t\t\treturn sock_ip.all;\n") - sock_pkg_create.write("\t\t\tend function;\n\n") - sock_pkg_create.write("\t\tend package body;\" > sock_pkg.vhdl") +#!/usr/bin/python3 + +import re +import os +from configparser import SafeConfigParser + + +class ModelGeneration: + + def __init__(self, file): + + # Script starts from here + print("Arguement is : ", file) + self.fname = os.path.basename(file) + print("VHDL filename is : ", self.fname) + self.home = os.path.expanduser("~") + self.parser = SafeConfigParser() + self.parser.read(os.path.join( + self.home, os.path.join('.nghdl', 'config.ini'))) + self.ngspice_home = self.parser.get('NGSPICE', 'NGSPICE_HOME') + self.release_dir = self.parser.get('NGSPICE', 'RELEASE') + self.src_home = self.parser.get('SRC', 'SRC_HOME') + self.licensefile = self.parser.get('SRC', 'LICENSE') + + # #### Creating connection_info.txt file from vhdl file #### # + read_vhdl = open(file, 'r') + vhdl_data = read_vhdl.readlines() + read_vhdl.close() + + start_flag = -1 # Used for scaning part of data + scan_data = [] + # p=re.search('port(.*?)end',read_vhdl,re.M|re.I|re.DOTALL).group() + + for item in vhdl_data: + if re.search('port', item, re.I): + start_flag = 1 + + elif re.search("end", item, re.I): + start_flag = 0 + + if start_flag == 1: + item = re.sub("port", " ", item, flags=re.I) + item = re.sub("\(", " ", item, flags=re.I) # noqa + item = re.sub("\)", " ", item, flags=re.I) # noqa + item = re.sub(";", " ", item, flags=re.I) + + scan_data.append(item.rstrip()) + scan_data = [_f for _f in scan_data if _f] + elif start_flag == 0: + break + + port_info = [] + self.port_vector_info = [] + + for item in scan_data: + print("Scan Data :", item) + if re.search("in", item, flags=re.I): + if re.search("std_logic_vector", item, flags=re.I): + temp = re.compile(r"\s*std_logic_vector\s*", flags=re.I) + elif re.search("std_logic", item, flags=re.I): + temp = re.compile(r"\s*std_logic\s*", flags=re.I) + else: + raise ValueError("Please check your vhdl " + + "code for datatype of input port") + elif re.search("out", item, flags=re.I): + if re.search("std_logic_vector", item, flags=re.I): + temp = re.compile(r"\s*std_logic_vector\s*", flags=re.I) + elif re.search("std_logic", item, flags=re.I): + temp = re.compile(r"\s*std_logic\s*", flags=re.I) + else: + raise ValueError("Please check your vhdl " + + "code for datatype of output port") + else: + raise ValueError( + "Please check the in/out direction of your port" + ) + + lhs = temp.split(item)[0] + rhs = temp.split(item)[1] + bit_info = re.compile(r"\s*downto\s*", flags=re.I).split(rhs)[0] + if bit_info: + port_info.append(lhs + ":" + str(int(bit_info) + int(1))) + self.port_vector_info.append(1) + else: + port_info.append(lhs + ":" + str(int(1))) + self.port_vector_info.append(0) + + print("Port Info :", port_info) + + # Open connection_info.txt file + con_ifo = open('connection_info.txt', 'w') + + for item in port_info: + word = item.split(':') + con_ifo.write( + word[0].strip() + ' ' + word[1].strip() + ' ' + word[2].strip() + ) + con_ifo.write("\n") + con_ifo.close() + + def readPortInfo(self): + + # ############## Reading connection/port information ############## # + + # Declaring input and output list + input_list = [] + output_list = [] + + # Reading connection_info.txt file for port infomation + read_file = open('connection_info.txt', 'r') + data = read_file.readlines() + read_file.close() + + # Extracting input and output port list from data + print("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx") + for line in data: + print(line) + if re.match(r'^\s*$', line): + pass + else: + in_items = re.findall( + "IN", line, re.MULTILINE | re.IGNORECASE + ) + out_items = re.findall( + "OUT", line, re.MULTILINE | re.IGNORECASE + ) + if in_items: + input_list.append(line.split()) + + if out_items: + output_list.append(line.split()) + + print("Inout List :", input_list) + print("Output list", output_list) + + self.input_port = [] + self.output_port = [] + + # creating list of input and output port with its weight + for input in input_list: + self.input_port.append(input[0]+":"+input[2]) + for output in output_list: + self.output_port.append(output[0]+":"+output[2]) + + print("Output Port List : ", self.output_port) + print("Input Port List : ", self.input_port) + + def createCfuncModFile(self): + + # ############## Creating content for cfunc.mod file ############## # + + print("Starting With cfunc.mod file") + cfunc = open('cfunc.mod', 'w') + print("Building content for cfunc.mod file") + + comment = '''/* This is cfunc.mod file auto generated by gen_con_info.py + Developed by Fahim, Rahul at IIT Bombay */\n + ''' + + header = ''' + #include + #include + #include + #include + #include + #include + #include + #include + + ''' + + if os.name == 'nt': + header += ''' + #undef BOOLEAN + #include + ''' + else: + header += ''' + #include + #include + #include + ''' + + function_open = ( + '''void cm_''' + self.fname.split('.')[0] + '''(ARGS) \n{''') + + digital_state_output = [] + for item in self.output_port: + digital_state_output.append( + "Digital_State_t *_op_" + item.split(':')[0] + + ", *_op_" + item.split(':')[0] + "_old;" + ) + + var_section = ''' + // Declaring components of Client + FILE *log_client = NULL; + log_client=fopen("client.log","a"); + int bytes_recieved; + char send_data[1024]; + char recv_data[1024]; + char *key_iter; + struct hostent *host; + struct sockaddr_in server_addr; + int sock_port = 5000+PARAM(instance_id); + ''' + + if os.name != 'nt': + var_section += ''' + int socket_fd; + ''' + + temp_input_var = [] + for item in self.input_port: + temp_input_var.append( + "char temp_" + item.split(':')[0] + "[1024];" + ) + + # Start of INIT function + init_start_function = ''' + if(INIT) + { + /* Allocate storage for output ports ''' \ + '''and set the load for input ports */ + ''' + + cm_event_alloc = [] + cm_count_output = 0 + for item in self.output_port: + cm_event_alloc.append( + "cm_event_alloc(" + + str(cm_count_output) + "," + item.split(':')[1] + + "*sizeof(Digital_State_t));" + ) + cm_count_output = cm_count_output + 1 + + load_in_port = [] + for item in self.input_port: + load_in_port.append( + "for(Ii=0;Iih_addr); + bzero(&(server_addr.sin_zero),8); + + ''' + + connect_server = ''' + fprintf(log_client,"Client-Connecting to server \\n"); + + //Connecting to server + int try_limit=10; + while(try_limit>0) + { + if (connect(socket_fd, (struct sockaddr*)&server_addr,''' \ + '''sizeof(struct sockaddr)) == -1) + { + sleep(1); + try_limit--; + if(try_limit==0) + { + fprintf(stderr,"Connect- Error:Tried to connect server on port,''' \ + '''failed...giving up \\n"); + fprintf(log_client,"Connect- Error:Tried to connect server on ''' \ + '''port, failed...giving up \\n"); + exit(1); + } + } + else + { + printf("Client-Connected to server \\n"); + fprintf(log_client,"Client-Connected to server \\n"); + break; + } + } + ''' + + # Assign bit value to every input + assign_data_to_input = [] + for item in self.input_port: + assign_data_to_input.append("\tfor(Ii=0;Ii " + item.split(':')[0] + ",\n") + + for item in self.output_port: + if self.output_port.index(item) == len(self.output_port) - 1: + map.append("\t\t\t\t" + item.split(':')[0] + + " => " + item.split(':')[0] + "\n") + else: + map.append("\t\t\t\t" + item.split(':')[0] + + " => " + item.split(':')[0] + ",\n") + map.append("\t\t\t);") + + # Testbench Clock + tb_clk = "clk_s <= not clk_s after 5 us;\n\n" + + # Adding Process block for Vhpi + process_Vhpi = [] + process_Vhpi.append( + "process\n\t\tvariable sock_port : integer;" + + "\n\t\ttype string_ptr is access string;" + + "\n\t\tvariable sock_ip : string_ptr;" + + "\n\t\tbegin\n\t\tsock_port := sock_port_fun;" + + "\n\t\tsock_ip := new string'(sock_ip_fun);" + + "\n\t\tVhpi_Initialize(sock_port," + + "Pack_String_To_Vhpi_String(sock_ip.all));" + + "\n\t\twait until clk_s = '1';" + + "\n\t\twhile true loop\n\t\t\twait until clk_s = '0';" + + "\n\t\t\tVhpi_Listen;\n\t\t\twait for 1 us;\n\t\t\t" + + "Vhpi_Send;" + + "\n\t\tend loop;\n\t\twait;\n\tend process;\n\n" + ) + + # Adding process block + process = [] + process.append("\tprocess\n") + process.append("\t\tvariable count : integer:=0;\n") + + for item in self.input_port: + process.append( + "\t\tvariable " + item.split(':')[0] + "_v : VhpiString;\n" + ) + + for item in self.output_port: + process.append( + "\t\tvariable " + item.split(':')[0] + "_v : VhpiString;\n" + ) + + process.append("\t\tvariable obj_ref : VhpiString;\n") + process.append("\tbegin\n") + process.append("\t\twhile true loop\n") + process.append("\t\t\twait until clk_s = '0';\n\n") + + port_vector_count = 0 + + for item in self.input_port: + process.append( + '\t\t\tobj_ref := Pack_String_To_Vhpi_String("' + + item.split(':')[0] + '");\n' + ) + process.append( + '\t\t\tVhpi_Get_Port_Value(obj_ref,' + + item.split(':')[0] + '_v,' + item.split(':')[1] + ');\n' + ) + + if self.port_vector_info[port_vector_count]: + process.append( + '\t\t\t' + item.split(':')[0] + + ' <= Unpack_String(' + item.split(':')[0] + '_v,' + + item.split(':')[1] + ');\n' + ) + else: + process.append( + '\t\t\t' + item.split(':')[0] + + ' <= To_Std_Logic('+item.split(':')[0]+'_v'+');\n' + ) + + port_vector_count += 1 + process.append("\n") + + process.append('\t\t\twait for 1 us;\n') + + for item in self.output_port: + if self.port_vector_info[port_vector_count]: + process.append( + '\t\t\t' + item.split(':')[0] + + '_v := Pack_String_To_Vhpi_String' + + '(Convert_SLV_To_String(' + + item.split(':')[0]+'));\n' + ) + else: + process.append( + '\t\t\t' + item.split(':')[0] + + '_v := Pack_String_To_Vhpi_String(To_String(' + + item.split(':')[0]+'));\n' + ) + + port_vector_count += 1 + + process.append( + '\t\t\tobj_ref := Pack_String_To_Vhpi_String("' + + item.split(':')[0]+'");\n' + ) + process.append( + '\t\t\tVhpi_Set_Port_Value(obj_ref,' + + item.split(':')[0] + '_v,' + item.split(':')[1] + ');\n' + ) + process.append("\n") + + process.append( + '\t\t\treport "Iteration - "' + + "& integer'image(count) severity note;\n" + ) + process.append('\t\t\tcount := count + 1;\n') + process.append("\t\tend loop;\n") + process.append("\tend process;\n\n") + process.append("end architecture;") + + # Writing all the components to testbench file + testbench.write(comment_vhdl) + testbench.write(tb_header) + testbench.write(tb_entity) + testbench.write(arch) + + for item in components: + testbench.write(item) + + for item in signals: + testbench.write(item) + + testbench.write("\n\n") + + testbench.write("begin\n\n") + + for item in map: + testbench.write(item) + + testbench.write("\n\t"+tb_clk) + + for item in process_Vhpi: + testbench.write(item) + + for item in process: + testbench.write(item) + + testbench.close() + + def createServerScript(self): + + # ####### Creating and writing components in start_server.sh ####### # + self.digital_home = self.parser.get('NGSPICE', 'DIGITAL_MODEL') + + start_server = open('start_server.sh', 'w') + + start_server.write("#!/bin/bash\n\n") + start_server.write( + "###This server run ghdl testebench for infinite time till " + + "ngspice send END signal to stop it\n\n" + ) + + if os.name == 'nt': + pathstr = self.digital_home + "/" + \ + self.fname.split('.')[0] + "/DUTghdl/" + pathstr = pathstr.replace("\\", "/") + start_server.write("cd "+pathstr+"\n") + else: + start_server.write("cd "+self.digital_home + + "/" + self.fname.split('.')[0] + "/DUTghdl/\n") + + start_server.write("chmod 775 sock_pkg_create.sh &&\n") + start_server.write("./sock_pkg_create.sh $1 $2 &&\n") + start_server.write("ghdl -i *.vhdl &&\n") + start_server.write("ghdl -a *.vhdl &&\n") + start_server.write("ghdl -a "+self.fname+" &&\n") + start_server.write( + "ghdl -a "+self.fname.split('.')[0]+"_tb.vhdl &&\n" + ) + + if os.name == 'nt': + start_server.write("ghdl -e -Wl,ghdlserver.o " + + "-Wl,libws2_32.a " + self.fname.split('.')[0] + "_tb &&\n") + start_server.write("./"+self.fname.split('.')[0]+"_tb.exe") + else: + start_server.write("ghdl -e -Wl,ghdlserver.o " + + self.fname.split('.')[0] + "_tb &&\n") + start_server.write("./"+self.fname.split('.')[0]+"_tb") + + start_server.close() + + def createSockScript(self): + + # ########### Creating and writing in sock_pkg_create.sh ########### # + + sock_pkg_create = open('sock_pkg_create.sh', 'w') + + sock_pkg_create.write("#!/bin/bash\n\n") + sock_pkg_create.write( + "##This file creates sock_pkg.vhdl file and sets the port " + + "and ip from parameters passed to it\n\n" + ) + sock_pkg_create.write("echo \"library ieee;\n") + sock_pkg_create.write("package sock_pkg is\n") + sock_pkg_create.write("\tfunction sock_port_fun return integer;\n") + sock_pkg_create.write("\tfunction sock_ip_fun return string;\n") + sock_pkg_create.write("end;\n\n") + sock_pkg_create.write("package body sock_pkg is\n") + sock_pkg_create.write("\tfunction sock_port_fun return integer is\n") + sock_pkg_create.write("\t\tvariable sock_port : integer;\n") + sock_pkg_create.write("\t\t\tbegin\n") + sock_pkg_create.write("\t\t\t\tsock_port := $1;\n") + sock_pkg_create.write("\t\t\t\treturn sock_port;\n") + sock_pkg_create.write("\t\t\tend function;\n\n") + sock_pkg_create.write("\tfunction sock_ip_fun return string is\n") + sock_pkg_create.write("\t\ttype string_ptr is access string;\n") + sock_pkg_create.write("\t\tvariable sock_ip : string_ptr;\n") + sock_pkg_create.write("\t\t\tbegin\n") + sock_pkg_create.write('\t\t\t\tsock_ip := new string\'(\\"$2\\");\n') + sock_pkg_create.write("\t\t\t\treturn sock_ip.all;\n") + sock_pkg_create.write("\t\t\tend function;\n\n") + sock_pkg_create.write("\t\tend package body;\" > sock_pkg.vhdl") diff --git a/src/ngspice_ghdl.py b/src/ngspice_ghdl.py index 06921ad..e873555 100755 --- a/src/ngspice_ghdl.py +++ b/src/ngspice_ghdl.py @@ -2,15 +2,14 @@ # This file create the gui to install code model in the ngspice. -#08.June.2020 - Bladen Martin - Added if-else constructs to make code OS independent# import os +import sys import shutil import subprocess -import sys -from configparser import SafeConfigParser -from PyQt4 import QtCore from PyQt4 import QtGui +from PyQt4 import QtCore +from configparser import SafeConfigParser from Appconfig import Appconfig from createKicadLibrary import AutoSchematic from model_generation import ModelGeneration @@ -141,7 +140,6 @@ class Mainwindow(QtGui.QWidget): ) if ret == QtGui.QMessageBox.Ok: print("Overwriting existing model " + self.modelname) - #08.June.2020 - BM - Delete existing model directory if os.name == 'nt': cmd = "rmdir " + self.modelname + "/s /q" else: @@ -219,16 +217,18 @@ class Mainwindow(QtGui.QWidget): "/src/ghdlserver/Utility_Package.vhdl", path + "/DUTghdl/") shutil.copy(os.path.join(self.home, self.src_home) + "/src/ghdlserver/Vhpi_Package.vhdl", path + "/DUTghdl/") - #08.June.2020 - BM - If OS is Windows, copy C library libws2_32.a to DUTghl be linked with server by GHDL + if os.name == 'nt': shutil.copy(os.path.join(self.home, self.src_home) + "/src/ghdlserver/libws2_32.a", path + "/DUTghdl/") + for file in self.file_list: shutil.copy(str(file), path + "/DUTghdl/") + os.chdir(path + "/DUTghdl") - #08.June.2020 - BM - Run following commands as per OS. Use bash.exe provided by MSYS for Windows if os.name == 'nt': - self.msys_bin = self.parser.get('COMPILER', 'MSYS_HOME') #path to msys bin directory where bash is located + # path to msys bin directory where bash is located + self.msys_bin = self.parser.get('COMPILER', 'MSYS_HOME') subprocess.call(self.msys_bin+"/bash.exe " + path + "/DUTghdl/compile.sh", shell=True) subprocess.call(self.msys_bin+"/bash.exe -c " + @@ -239,11 +239,9 @@ class Mainwindow(QtGui.QWidget): subprocess.call("bash " + path + "/DUTghdl/compile.sh", shell=True) subprocess.call("chmod a+x start_server.sh", shell=True) subprocess.call("chmod a+x sock_pkg_create.sh", shell=True) + os.remove("compile.sh") os.remove("ghdlserver.c") - # os.remove("ghdlserver.h") - # os.remove("Utility_Package.vhdl") - # os.remove("Vhpi_Package.vhdl") # Slot to redirect stdout and stderr to window console @QtCore.pyqtSlot() @@ -259,17 +257,17 @@ class Mainwindow(QtGui.QWidget): def runMake(self): print("run Make Called") self.release_home = self.parser.get('NGSPICE', 'RELEASE') - #08.June.2020 - BM - Changed make location to .../ngspice-nghdl/release/src/xspice/icm path_icm = os.path.join(self.release_home, "src/xspice/icm") - print(path_icm) os.chdir(path_icm) + try: - #08.June.2020 - BM - Use make.exe provided by MSYS for Windows if os.name == 'nt': - self.msys_bin = self.parser.get('COMPILER', 'MSYS_HOME') #path to msys bin directory where make is located - cmd = self.msys_bin+"\make.exe" + # path to msys bin directory where make is located + self.msys_bin = self.parser.get('COMPILER', 'MSYS_HOME') + cmd = self.msys_bin+"\\make.exe" else: cmd = " make" + print("Running Make command in " + path_icm) path = os.getcwd() # noqa self.process = QtCore.QProcess(self) @@ -284,7 +282,7 @@ class Mainwindow(QtGui.QWidget): try: if os.name == 'nt': self.msys_bin = self.parser.get('COMPILER', 'MSYS_HOME') - cmd = self.msys_bin+"\make.exe install" + cmd = self.msys_bin+"\\make.exe install" else: cmd = " make install" print("Running Make Install") -- cgit