From 5deac9027a851c497c6aebfb9b74c491b598e944 Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Thu, 20 Feb 2020 15:19:54 +0530 Subject: restructured code - pyinstaller --- src/Appconfig.py | 2 +- src/model_generation.py | 1976 ++++++++++++++++++++++++----------------------- src/ngspice_ghdl.py | 25 +- 3 files changed, 1015 insertions(+), 988 deletions(-) (limited to 'src') diff --git a/src/Appconfig.py b/src/Appconfig.py index 8ad0a77..8cf63a2 100644 --- a/src/Appconfig.py +++ b/src/Appconfig.py @@ -9,7 +9,7 @@ class Appconfig: parser_esim.read(os.path.join(home, os.path.join('.esim', 'config.ini'))) try: src_home = parser_esim.get('eSim', 'eSim_HOME') - xml_loc = os.path.join(src_home, 'src/modelParamXML') + xml_loc = os.path.join(src_home, 'library/modelParamXML') lib_loc = os.path.expanduser('~') except BaseException: pass diff --git a/src/model_generation.py b/src/model_generation.py index 445143b..dd6eea2 100644 --- a/src/model_generation.py +++ b/src/model_generation.py @@ -1,1010 +1,1032 @@ #!/usr/bin/python3 import re -import sys import os -# Script start from here -print("Arguement is :", sys.argv[1]) -fname = os.path.basename(sys.argv[1]) -print("VHDL filename is :", fname) -home = os.path.expanduser("~") - -# #### Creating connection_info.txt file from vhdl file #### # -read_vhdl = open(sys.argv[1], 'r') -vhdl_data = read_vhdl.readlines() -read_vhdl.close() - -start_flag = -1 # Used for scaning part of data -scan_data = [] -# p=re.search('port(.*?)end',read_vhdl,re.M|re.I|re.DOTALL).group() - -for item in vhdl_data: - if re.search('port', item, re.I): - start_flag = 1 - - elif re.search("end", item, re.I): - start_flag = 0 - - if start_flag == 1: - item = re.sub("port", " ", item, flags=re.I) - item = re.sub("\(", " ", item, flags=re.I) # noqa - item = re.sub("\)", " ", item, flags=re.I) # noqa - item = re.sub(";", " ", item, flags=re.I) - - scan_data.append(item.rstrip()) - scan_data = [_f for _f in scan_data if _f] - elif start_flag == 0: - break - -port_info = [] -port_vector_info = [] - -for item in scan_data: - print("Scan Data :", item) - if re.search("in", item, flags=re.I): - if re.search("std_logic_vector", item, flags=re.I): - temp = re.compile(r"\s*std_logic_vector\s*", flags=re.I) - elif re.search("std_logic", item, flags=re.I): - temp = re.compile(r"\s*std_logic\s*", flags=re.I) - else: - print("Please check your vhdl code for datatype of input port") - sys.exit() - elif re.search("out", item, flags=re.I): - if re.search("std_logic_vector", item, flags=re.I): - temp = re.compile(r"\s*std_logic_vector\s*", flags=re.I) - elif re.search("std_logic", item, flags=re.I): - temp = re.compile(r"\s*std_logic\s*", flags=re.I) - else: - print("Please check your vhdl code for datatype of output port") - sys.exit() - else: - print("Please check the in/out direction of your port") - sys.exit() - - lhs = temp.split(item)[0] - rhs = temp.split(item)[1] - bit_info = re.compile(r"\s*downto\s*", flags=re.I).split(rhs)[0] - if bit_info: - port_info.append(lhs + ":" + str(int(bit_info) + int(1))) - port_vector_info.append(1) - else: - port_info.append(lhs + ":" + str(int(1))) - port_vector_info.append(0) - -print("Port Info :", port_info) - -# Open connection_info.txt file -con_ifo = open('connection_info.txt', 'w') - -for item in port_info: - word = item.split(':') - con_ifo.write( - word[0].strip() + ' ' + word[1].strip() + ' ' + word[2].strip() - ) - con_ifo.write("\n") -con_ifo.close() - - -# ################## Reading connection/port information ################## # - -# Declaring input and output list -input_list = [] -output_list = [] - -# Reading connection_info.txt file for port infomation -read_file = open('connection_info.txt', 'r') -data = read_file.readlines() -read_file.close() - -# Extracting input and output port list from data -print("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx") -for line in data: - print(line) - if re.match(r'^\s*$', line): - pass - else: - in_items = re.findall( - "IN", line, re.MULTILINE | re.IGNORECASE - ) - out_items = re.findall( - "OUT", line, re.MULTILINE | re.IGNORECASE - ) - if in_items: - input_list.append(line.split()) - else: - pass - # print("Not Found") - if out_items: - output_list.append(line.split()) - # print("Found Out") - else: - pass +class ModelGeneration: + + def __init__(self, file): + + # Script starts from here + print("Arguement is : ", file) + self.fname = os.path.basename(file) + print("VHDL filename is : ", self.fname) + self.home = os.path.expanduser("~") + + # #### Creating connection_info.txt file from vhdl file #### # + read_vhdl = open(file, 'r') + vhdl_data = read_vhdl.readlines() + read_vhdl.close() + + start_flag = -1 # Used for scaning part of data + scan_data = [] + # p=re.search('port(.*?)end',read_vhdl,re.M|re.I|re.DOTALL).group() + + for item in vhdl_data: + if re.search('port', item, re.I): + start_flag = 1 + + elif re.search("end", item, re.I): + start_flag = 0 + + if start_flag == 1: + item = re.sub("port", " ", item, flags=re.I) + item = re.sub("\(", " ", item, flags=re.I) # noqa + item = re.sub("\)", " ", item, flags=re.I) # noqa + item = re.sub(";", " ", item, flags=re.I) + + scan_data.append(item.rstrip()) + scan_data = [_f for _f in scan_data if _f] + elif start_flag == 0: + break + + port_info = [] + self.port_vector_info = [] + + for item in scan_data: + print("Scan Data :", item) + if re.search("in", item, flags=re.I): + if re.search("std_logic_vector", item, flags=re.I): + temp = re.compile(r"\s*std_logic_vector\s*", flags=re.I) + elif re.search("std_logic", item, flags=re.I): + temp = re.compile(r"\s*std_logic\s*", flags=re.I) + else: + raise ValueError("Please check your vhdl " + + "code for datatype of input port") + elif re.search("out", item, flags=re.I): + if re.search("std_logic_vector", item, flags=re.I): + temp = re.compile(r"\s*std_logic_vector\s*", flags=re.I) + elif re.search("std_logic", item, flags=re.I): + temp = re.compile(r"\s*std_logic\s*", flags=re.I) + else: + raise ValueError("Please check your vhdl " + + "code for datatype of output port") + else: + raise ValueError( + "Please check the in/out direction of your port" + ) + + lhs = temp.split(item)[0] + rhs = temp.split(item)[1] + bit_info = re.compile(r"\s*downto\s*", flags=re.I).split(rhs)[0] + if bit_info: + port_info.append(lhs + ":" + str(int(bit_info) + int(1))) + self.port_vector_info.append(1) + else: + port_info.append(lhs + ":" + str(int(1))) + self.port_vector_info.append(0) + + print("Port Info :", port_info) -print("Inout List :", input_list) -print("Output list", output_list) -input_port = [] -output_port = [] + # Open connection_info.txt file + con_ifo = open('connection_info.txt', 'w') -# creating list of input and output port with its weight -for input in input_list: - input_port.append(input[0]+":"+input[2]) -for output in output_list: - output_port.append(output[0]+":"+output[2]) + for item in port_info: + word = item.split(':') + con_ifo.write( + word[0].strip() + ' ' + word[1].strip() + ' ' + word[2].strip() + ) + con_ifo.write("\n") + con_ifo.close() -print("Output Port List : ", output_port) -print("Input Port List : ", input_port) + def readPortInfo(self): + # ############## Reading connection/port information ############## # -# ################## Creating content for cfunc.mod file ################## # + # Declaring input and output list + input_list = [] + output_list = [] -print("Starting With cfunc.mod file") -cfunc = open('cfunc.mod', 'w') -print("Building content for cfunc.mod file") + # Reading connection_info.txt file for port infomation + read_file = open('connection_info.txt', 'r') + data = read_file.readlines() + read_file.close() -comment = '''/* This is cfunc.mod file auto generated by gen_con_info.py -Developed by Fahim, Rahul at IIT Bombay */\n + # Extracting input and output port list from data + print("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx") + for line in data: + print(line) + if re.match(r'^\s*$', line): + pass + else: + in_items = re.findall( + "IN", line, re.MULTILINE | re.IGNORECASE + ) + out_items = re.findall( + "OUT", line, re.MULTILINE | re.IGNORECASE + ) + if in_items: + input_list.append(line.split()) + + if out_items: + output_list.append(line.split()) + + print("Inout List :", input_list) + print("Output list", output_list) + + self.input_port = [] + self.output_port = [] + + # creating list of input and output port with its weight + for input in input_list: + self.input_port.append(input[0]+":"+input[2]) + for output in output_list: + self.output_port.append(output[0]+":"+output[2]) + + print("Output Port List : ", self.output_port) + print("Input Port List : ", self.input_port) + + def createCfuncModFile(self): + + # ############## Creating content for cfunc.mod file ############## # + + print("Starting With cfunc.mod file") + cfunc = open('cfunc.mod', 'w') + print("Building content for cfunc.mod file") + + comment = '''/* This is cfunc.mod file auto generated by gen_con_info.py + Developed by Fahim, Rahul at IIT Bombay */\n + ''' + + header = ''' + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include ''' -header = ''' -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -''' - -function_open = ( - '''void cm_''' + fname.split('.')[0] + '''(ARGS) \n{''') - -digital_state_output = [] -for item in output_port: - digital_state_output.append( - "Digital_State_t *_op_" + item.split(':')[0] + - ", *_op_" + item.split(':')[0] + "_old;" - ) - - -var_section = ''' - // Declaring components of Client - FILE *log_client = NULL; - log_client=fopen("client.log","a"); - int socket_fd, bytes_recieved; - char send_data[1024]; - char recv_data[1024]; - char *key_iter; - struct hostent *host; - struct sockaddr_in server_addr; - int sock_port = 5000+PARAM(instance_id); -''' - -temp_input_var = [] -for item in input_port: - temp_input_var.append( - "char temp_" + item.split(':')[0] + "[1024];" - ) - -# Start of INIT function -init_start_function = ''' - if(INIT) - { - /* Allocate storage for output ports ''' \ - '''and set the load for input ports */ -''' - -cm_event_alloc = [] -cm_count_output = 0 -for item in output_port: - cm_event_alloc.append( - "cm_event_alloc(" + - str(cm_count_output) + "," + item.split(':')[1] + - "*sizeof(Digital_State_t));" - ) - cm_count_output = cm_count_output + 1 - -load_in_port = [] -for item in input_port: - load_in_port.append( - "for(Ii=0;Iih_addr); - bzero(&(server_addr.sin_zero),8); - -''' - -connect_server = ''' - fprintf(log_client,"Client-Connecting to server \\n"); - - //Connecting to server - int try_limit=10; - while(try_limit>0) - { - if (connect(socket_fd, (struct sockaddr*)&server_addr,''' \ - '''sizeof(struct sockaddr)) == -1) - { - sleep(1); - try_limit--; - if(try_limit==0) + create_socket = ''' + //Creating socket for client + if ((socket_fd = socket(AF_INET, SOCK_STREAM, 0)) == -1) { - fprintf(stderr,"Connect- Error:Tried to connect server on port,''' \ - '''failed...giving up \\n"); - fprintf(log_client,"Connect- Error:Tried to connect server on ''' \ - '''port, failed...giving up \\n"); + perror("Client - Error while creating client Socket "); + fprintf(log_client,"Error while creating client socket \\n"); exit(1); } - } - else - { - printf("Client-Connected to server \\n"); - fprintf(log_client,"Client-Connected to server \\n"); - break; - } - } -''' - -# Assign bit value to every input -assign_data_to_input = [] -for item in input_port: - assign_data_to_input.append("\tfor(Ii=0;Iih_addr); + bzero(&(server_addr.sin_zero),8); + + ''' + + connect_server = ''' + fprintf(log_client,"Client-Connecting to server \\n"); + + //Connecting to server + int try_limit=10; + while(try_limit>0) + { + if (connect(socket_fd, (struct sockaddr*)&server_addr,''' \ + '''sizeof(struct sockaddr)) == -1) + { + sleep(1); + try_limit--; + if(try_limit==0) + { + fprintf(stderr,"Connect- Error:Tried to connect server on port,''' \ + '''failed...giving up \\n"); + fprintf(log_client,"Connect- Error:Tried to connect server on ''' \ + '''port, failed...giving up \\n"); + exit(1); + } + } + else + { + printf("Client-Connected to server \\n"); + fprintf(log_client,"Client-Connected to server \\n"); + break; + } + } + ''' + + # Assign bit value to every input + assign_data_to_input = [] + for item in self.input_port: + assign_data_to_input.append("\tfor(Ii=0;Ii " + item.split(':')[0] + ",\n") + + for item in self.output_port: + if self.output_port.index(item) == len(self.output_port) - 1: + map.append("\t\t\t\t" + item.split(':')[0] + + " => " + item.split(':')[0] + "\n") + else: + map.append("\t\t\t\t" + item.split(':')[0] + + " => " + item.split(':')[0] + ",\n") + map.append("\t\t\t);") + + # Testbench Clock + tb_clk = "clk_s <= not clk_s after 5 us;\n\n" + + # Adding Process block for Vhpi + process_Vhpi = [] + process_Vhpi.append( + "process\n\t\tvariable sock_port : integer;" + + "\n\t\ttype string_ptr is access string;" + + "\n\t\tvariable sock_ip : string_ptr;" + + "\n\t\tbegin\n\t\tsock_port := sock_port_fun;" + + "\n\t\tsock_ip := new string'(sock_ip_fun);" + + "\n\t\tVhpi_Initialize(sock_port," + + "Pack_String_To_Vhpi_String(sock_ip.all));" + + "\n\t\twait until clk_s = '1';" + + "\n\t\twhile true loop\n\t\t\twait until clk_s = '0';" + + "\n\t\t\tVhpi_Listen;\n\t\t\twait for 1 us;\n\t\t\t" + + "Vhpi_Send;" + + "\n\t\tend loop;\n\t\twait;\n\tend process;\n\n" ) - else: - signals.append("\tsignal " + item.split(':')[0] + ": std_logic;\n") - port_vector_count += 1 - - # if item.split(":")[1] != '1': - # signals.append("\tsignal "+item.split(':')[0]+": - # std_logic_vector("+str(int(item.split(':')[1]) - - # int(1))+" downto 0);\n") - # else: - # signals.append("\tsignal "+item.split(':')[0]+": - # std_logic_vector("+str(int(item.split(':')[1]) - - # int(1))+" downto 0);\n") - - -for item in output_port: - if port_vector_info[port_vector_count]: - signals.append( - "\tsignal " + item.split(':')[0] + ": std_logic_vector(" + - str(int(item.split(':')[1]) - int(1)) + " downto 0);\n" + + # Adding process block + process = [] + process.append("\tprocess\n") + process.append("\t\tvariable count : integer:=0;\n") + + for item in self.input_port: + process.append( + "\t\tvariable " + item.split(':')[0] + "_v : VhpiString;\n" + ) + + for item in self.output_port: + process.append( + "\t\tvariable " + item.split(':')[0] + "_v : VhpiString;\n" + ) + + process.append("\t\tvariable obj_ref : VhpiString;\n") + process.append("\tbegin\n") + process.append("\t\twhile true loop\n") + process.append("\t\t\twait until clk_s = '0';\n\n") + + port_vector_count = 0 + + for item in self.input_port: + process.append( + '\t\t\tobj_ref := Pack_String_To_Vhpi_String("' + + item.split(':')[0] + '");\n' + ) + process.append( + '\t\t\tVhpi_Get_Port_Value(obj_ref,' + + item.split(':')[0] + '_v,' + item.split(':')[1] + ');\n' + ) + + if self.port_vector_info[port_vector_count]: + process.append( + '\t\t\t' + item.split(':')[0] + + ' <= Unpack_String(' + item.split(':')[0] + '_v,' + + item.split(':')[1] + ');\n' + ) + else: + process.append( + '\t\t\t' + item.split(':')[0] + + ' <= To_Std_Logic('+item.split(':')[0]+'_v'+');\n' + ) + + port_vector_count += 1 + process.append("\n") + + process.append('\t\t\twait for 1 us;\n') + + for item in self.output_port: + if self.port_vector_info[port_vector_count]: + process.append( + '\t\t\t' + item.split(':')[0] + + '_v := Pack_String_To_Vhpi_String' + + '(Convert_SLV_To_String(' + + item.split(':')[0]+'));\n' + ) + else: + process.append( + '\t\t\t' + item.split(':')[0] + + '_v := Pack_String_To_Vhpi_String(To_String(' + + item.split(':')[0]+'));\n' + ) + + port_vector_count += 1 + + process.append( + '\t\t\tobj_ref := Pack_String_To_Vhpi_String("' + + item.split(':')[0]+'");\n' + ) + process.append( + '\t\t\tVhpi_Set_Port_Value(obj_ref,' + + item.split(':')[0] + '_v,' + item.split(':')[1] + ');\n' + ) + process.append("\n") + + process.append( + '\t\t\treport "Iteration - "' + + "& integer'image(count) severity note;\n" ) - else: - signals.append("\tsignal " + item.split(':')[0] + ": std_logic;\n") - port_vector_count += 1 - # if item.split(":")[1] != '1': - # signals.append("\tsignal "+item.split(':')[0]+": - # std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0);\n") - # else: - # signals.append("\tsignal "+item.split(':')[0]+": - # std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0);\n") - -# Adding mapping part -map = [] -map.append("\tu1 : " + fname.split('.')[0] + " port map(\n") - -for item in input_port: - map.append( - "\t\t\t\t" + item.split(':')[0] + " => " + item.split(':')[0] + ",\n" - ) - -for item in output_port: - if output_port.index(item) == len(output_port) - 1: - map.append( - "\t\t\t\t" + item.split(':')[0] + " => " + item.split(':')[0] + "\n" + process.append('\t\t\tcount := count + 1;\n') + process.append("\t\tend loop;\n") + process.append("\tend process;\n\n") + process.append("end architecture;") + + # Writing all the components to testbench file + testbench.write(comment_vhdl) + testbench.write(tb_header) + testbench.write(tb_entity) + testbench.write(arch) + + for item in components: + testbench.write(item) + + for item in signals: + testbench.write(item) + + testbench.write("\n\n") + + testbench.write("begin\n\n") + + for item in map: + testbench.write(item) + + testbench.write("\n\t"+tb_clk) + + for item in process_Vhpi: + testbench.write(item) + + for item in process: + testbench.write(item) + + testbench.close() + + def createServerScript(self): + + # ####### Creating and writing components in start_server.sh ####### # + + start_server = open('start_server.sh', 'w') + + start_server.write("#!/bin/bash\n\n") + start_server.write( + "###This server run ghdl testebench for infinite time till " + + "ngspice send END signal to stop it\n\n" ) - else: - map.append( - "\t\t\t\t" + item.split(':')[0] + " => " + item.split(':')[0] + ",\n" + start_server.write( + "cd "+self.home+"/ngspice-nghdl/src/xspice/icm/ghdl/" + + self.fname.split('.')[0]+"/DUTghdl/\n" ) -map.append("\t\t\t);") - - -# Testbench Clock -tb_clk = "clk_s <= not clk_s after 5 us;\n\n" - -# Adding Process block for Vhpi -process_Vhpi = [] -process_Vhpi.append( - "process\n\t\tvariable sock_port : integer;" + - "\n\t\ttype string_ptr is access string;" + - "\n\t\tvariable sock_ip : string_ptr;" + - "\n\t\tbegin\n\t\tsock_port := sock_port_fun;" + - "\n\t\tsock_ip := new string'(sock_ip_fun);" + - "\n\t\tVhpi_Initialize(sock_port," + - "Pack_String_To_Vhpi_String(sock_ip.all));" + - "\n\t\twait until clk_s = '1';" + - "\n\t\twhile true loop\n\t\t\twait until clk_s = '0';" + - "\n\t\t\tVhpi_Listen;\n\t\t\twait for 1 us;\n\t\t\t" + - "Vhpi_Send;" + - "\n\t\tend loop;\n\t\twait;\n\tend process;\n\n" -) - -# Adding process block -process = [] -process.append("\tprocess\n") -process.append("\t\tvariable count : integer:=0;\n") - -for item in input_port: - process.append("\t\tvariable " + item.split(':')[0] + "_v : VhpiString;\n") - -for item in output_port: - process.append("\t\tvariable " + item.split(':')[0] + "_v : VhpiString;\n") - -process.append("\t\tvariable obj_ref : VhpiString;\n") -process.append("\tbegin\n") -process.append("\t\twhile true loop\n") -process.append("\t\t\twait until clk_s = '0';\n\n") - -port_vector_count = 0 - -for item in input_port: - process.append( - '\t\t\tobj_ref := Pack_String_To_Vhpi_String("' + - item.split(':')[0] + '");\n' - ) - process.append( - '\t\t\tVhpi_Get_Port_Value(obj_ref,' + - item.split(':')[0] + '_v,' + item.split(':')[1] + ');\n' - ) - - if port_vector_info[port_vector_count]: - process.append( - '\t\t\t' + item.split(':')[0] + - ' <= Unpack_String(' + item.split(':')[0] + '_v,' + - item.split(':')[1] + ');\n' + start_server.write("chmod 775 sock_pkg_create.sh &&\n") + start_server.write("./sock_pkg_create.sh $1 $2 &&\n") + start_server.write("ghdl -a sock_pkg.vhdl &&\n") + start_server.write("ghdl -a "+self.fname+" &&\n") + start_server.write( + "ghdl -a "+self.fname.split('.')[0]+"_tb.vhdl &&\n" ) - else: - process.append( - '\t\t\t' + item.split(':')[0] + - ' <= To_Std_Logic('+item.split(':')[0]+'_v'+');\n' + start_server.write( + "ghdl -e -Wl,ghdlserver.o " + self.fname.split('.')[0] + "_tb &&\n" ) + start_server.write("./"+self.fname.split('.')[0]+"_tb") - port_vector_count += 1 - process.append("\n") + start_server.close() -process.append('\t\t\twait for 1 us;\n') + def createSockScript(self): -for item in output_port: - if port_vector_info[port_vector_count]: - process.append( - '\t\t\t' + item.split(':')[0] + - '_v := Pack_String_To_Vhpi_String' + - '(Convert_SLV_To_String(' + - item.split(':')[0]+'));\n' - ) - else: - process.append( - '\t\t\t' + item.split(':')[0] + - '_v := Pack_String_To_Vhpi_String(To_String(' + - item.split(':')[0]+'));\n' - ) + # ########### Creating and writing in sock_pkg_create.sh ########### # - port_vector_count += 1 - - process.append( - '\t\t\tobj_ref := Pack_String_To_Vhpi_String("' + - item.split(':')[0]+'");\n' - ) - process.append( - '\t\t\tVhpi_Set_Port_Value(obj_ref,' + - item.split(':')[0] + '_v,' + item.split(':')[1] + ');\n' - ) - process.append("\n") - -process.append( - '\t\t\treport "Iteration - "' + - "& integer'image(count) severity note;\n" -) -process.append('\t\t\tcount := count + 1;\n') -process.append("\t\tend loop;\n") -process.append("\tend process;\n\n") -process.append("end architecture;") - -# Writing all the components to testbench file -testbench.write(comment_vhdl) -testbench.write(tb_header) -testbench.write(tb_entity) -testbench.write(arch) - -for item in components: - testbench.write(item) - -for item in signals: - testbench.write(item) - -testbench.write("\n\n") - -testbench.write("begin\n\n") - -for item in map: - testbench.write(item) - -testbench.write("\n\t"+tb_clk) - -for item in process_Vhpi: - testbench.write(item) - -for item in process: - testbench.write(item) - - -testbench.close() - - -# ########### Creating and writing components in start_server.sh ########### # - -start_server = open('start_server.sh', 'w') - -start_server.write("#!/bin/bash\n\n") -start_server.write( - "###This server run ghdl testebench for infinite time till " + - "ngspice send END signal to stop it\n\n" -) -start_server.write( - "cd "+home+"/ngspice-nghdl/src/xspice/icm/ghdl/" + - fname.split('.')[0]+"/DUTghdl/\n" -) -start_server.write("chmod 775 sock_pkg_create.sh &&\n") -start_server.write("./sock_pkg_create.sh $1 $2 &&\n") -start_server.write("ghdl -a sock_pkg.vhdl &&\n") -start_server.write("ghdl -a "+fname+" &&\n") -start_server.write("ghdl -a "+fname.split('.')[0]+"_tb.vhdl &&\n") -start_server.write("ghdl -e -Wl,ghdlserver.o "+fname.split('.')[0]+"_tb &&\n") -start_server.write("./"+fname.split('.')[0]+"_tb") - -start_server.close() - - -# ############### Creating and writing in sock_pkg_create.sh ############### # - -sock_pkg_create = open('sock_pkg_create.sh', 'w') - -sock_pkg_create.write("#!/bin/bash\n\n") -sock_pkg_create.write( - "##This file creates sock_pkg.vhdl file and sets the port " + - "and ip from parameters passed to it\n\n" -) -sock_pkg_create.write("echo \"library ieee;\n") -sock_pkg_create.write("package sock_pkg is\n") -sock_pkg_create.write("\tfunction sock_port_fun return integer;\n") -sock_pkg_create.write("\tfunction sock_ip_fun return string;\n") -sock_pkg_create.write("end;\n\n") -sock_pkg_create.write("package body sock_pkg is\n") -sock_pkg_create.write("\tfunction sock_port_fun return integer is\n") -sock_pkg_create.write("\t\tvariable sock_port : integer;\n") -sock_pkg_create.write("\t\t\tbegin\n") -sock_pkg_create.write("\t\t\t\tsock_port := $1;\n") -sock_pkg_create.write("\t\t\t\treturn sock_port;\n") -sock_pkg_create.write("\t\t\tend function;\n\n") -sock_pkg_create.write("\tfunction sock_ip_fun return string is\n") -sock_pkg_create.write("\t\ttype string_ptr is access string;\n") -sock_pkg_create.write("\t\tvariable sock_ip : string_ptr;\n") -sock_pkg_create.write("\t\t\tbegin\n") -sock_pkg_create.write('\t\t\t\tsock_ip := new string\'(\\"$2\\");\n') -sock_pkg_create.write("\t\t\t\treturn sock_ip.all;\n") -sock_pkg_create.write("\t\t\tend function;\n\n") -sock_pkg_create.write("\t\tend package body;\" > sock_pkg.vhdl") + sock_pkg_create = open('sock_pkg_create.sh', 'w') + + sock_pkg_create.write("#!/bin/bash\n\n") + sock_pkg_create.write( + "##This file creates sock_pkg.vhdl file and sets the port " + + "and ip from parameters passed to it\n\n" + ) + sock_pkg_create.write("echo \"library ieee;\n") + sock_pkg_create.write("package sock_pkg is\n") + sock_pkg_create.write("\tfunction sock_port_fun return integer;\n") + sock_pkg_create.write("\tfunction sock_ip_fun return string;\n") + sock_pkg_create.write("end;\n\n") + sock_pkg_create.write("package body sock_pkg is\n") + sock_pkg_create.write("\tfunction sock_port_fun return integer is\n") + sock_pkg_create.write("\t\tvariable sock_port : integer;\n") + sock_pkg_create.write("\t\t\tbegin\n") + sock_pkg_create.write("\t\t\t\tsock_port := $1;\n") + sock_pkg_create.write("\t\t\t\treturn sock_port;\n") + sock_pkg_create.write("\t\t\tend function;\n\n") + sock_pkg_create.write("\tfunction sock_ip_fun return string is\n") + sock_pkg_create.write("\t\ttype string_ptr is access string;\n") + sock_pkg_create.write("\t\tvariable sock_ip : string_ptr;\n") + sock_pkg_create.write("\t\t\tbegin\n") + sock_pkg_create.write('\t\t\t\tsock_ip := new string\'(\\"$2\\");\n') + sock_pkg_create.write("\t\t\t\treturn sock_ip.all;\n") + sock_pkg_create.write("\t\t\tend function;\n\n") + sock_pkg_create.write("\t\tend package body;\" > sock_pkg.vhdl") diff --git a/src/ngspice_ghdl.py b/src/ngspice_ghdl.py index 8fc5549..9991793 100755 --- a/src/ngspice_ghdl.py +++ b/src/ngspice_ghdl.py @@ -12,6 +12,7 @@ from PyQt4 import QtCore from configparser import SafeConfigParser from Appconfig import Appconfig from createKicadLibrary import AutoSchematic +from model_generation import ModelGeneration class Mainwindow(QtGui.QWidget): @@ -20,7 +21,6 @@ class Mainwindow(QtGui.QWidget): # super(Mainwindow, self).__init__() QtGui.QMainWindow.__init__(self) print("Initializing..........") - print("running with Python version:", sys.version_info[0]) self.home = os.path.expanduser("~") # Reading all variables from config.ini @@ -86,7 +86,7 @@ class Mainwindow(QtGui.QWidget): except BaseException: pass print("Close button clicked") - quit() + sys.exit() def browseFile(self): print("Browse button clicked") @@ -149,7 +149,7 @@ class Mainwindow(QtGui.QWidget): os.mkdir(self.modelname) else: print("Exiting application") - quit() + sys.exit() else: print("Creating model " + self.modelname + " directory") os.mkdir(self.modelname) @@ -177,11 +177,16 @@ class Mainwindow(QtGui.QWidget): print("Create Model Files Called") os.chdir(self.cur_dir) print("Current Working directory changed to " + self.cur_dir) - cmd = ("python3 " + self.src_home + - "/src/model_generation.py " + str(self.ledit.text())) - stdouterr = subprocess.Popen(cmd, shell=True) - stdouterr.wait() - print(stdouterr) + + # Generate model corresponding to the uploaded VHDL file + model = ModelGeneration(str(self.ledit.text())) + model.readPortInfo() + model.createCfuncModFile() + model.createIfSpecFile() + model.createTestbench() + model.createServerScript() + model.createSockScript() + # Moving file to model directory path = os.path.join(self.digital_home, self.modelname) shutil.move("cfunc.mod", path) @@ -247,7 +252,7 @@ class Mainwindow(QtGui.QWidget): print("make command process pid ---------- >", self.process.pid()) except BaseException: print("There is error in 'make' ") - quit() + sys.exit() def runMakeInstall(self): print("run Make Install Called") @@ -271,7 +276,7 @@ class Mainwindow(QtGui.QWidget): except BaseException: print("There is error in 'make install' ") - quit() + sys.exit() def createSchematicLib(self): if Appconfig.esimFlag == 1: -- cgit