From eb95026ab9007631eb8e2a1c54dcd38fabcb60ad Mon Sep 17 00:00:00 2001 From: saurabhb17 Date: Wed, 18 Dec 2019 15:13:23 +0530 Subject: Examples Restructered --- Example/README.md | 9 --- Example/bin_to_gray/bin_to_gray.vhdl | 21 ------ .../bin_to_gray/bin_to_gray.vhdl | 21 ++++++ Example/combinational_logic/counter/counter.vhdl | 30 ++++++++ .../counter/updown_counter.vhdl | 32 ++++++++ Example/combinational_logic/decoder/decoder.vhdl | 50 +++++++++++++ .../full_adder/full_adder_sl.vhdl | 19 +++++ .../full_adder/full_adder_sl_slv.vhdl | 19 +++++ .../full_adder/full_adder_slv.vhdl | 19 +++++ .../full_adder/full_adder_structural.vhdl | 87 ++++++++++++++++++++++ .../combinational_logic/half_adder/half_adder.vhdl | 18 +++++ Example/combinational_logic/mux-demux/demux.vhdl | 32 ++++++++ Example/combinational_logic/mux-demux/mux.vhdl | 30 ++++++++ Example/counter/up_counter.vhdl | 34 --------- Example/counter/up_counter_slv.vhdl | 24 ------ Example/decoder/decoder.vhdl | 50 ------------- Example/full_adder/full_adder_sl.vhdl | 19 ----- Example/full_adder/full_adder_sl_slv.vhdl | 19 ----- Example/full_adder/full_adder_slv.vhdl | 19 ----- Example/full_adder/full_adder_structural.vhdl | 87 ---------------------- Example/half_adder/half_adder.vhdl | 18 ----- Example/logic_gates/and_gate.vhdl | 33 ++++++++ Example/logic_gates/inverter.vhdl | 14 ++++ Example/logic_gates/inverter_gate.vhdl | 14 ---- Example/logic_gates/nand_gate.vhdl | 33 ++++++++ Example/logic_gates/nor_gate.vhdl | 13 ++++ Example/logic_gates/or_gate.vhdl | 13 ++++ Example/mux-demux/demux.vhdl | 32 -------- Example/mux-demux/mux.vhdl | 30 -------- 29 files changed, 463 insertions(+), 376 deletions(-) delete mode 100644 Example/README.md delete mode 100644 Example/bin_to_gray/bin_to_gray.vhdl create mode 100644 Example/combinational_logic/bin_to_gray/bin_to_gray.vhdl create mode 100644 Example/combinational_logic/counter/counter.vhdl create mode 100644 Example/combinational_logic/counter/updown_counter.vhdl create mode 100644 Example/combinational_logic/decoder/decoder.vhdl create mode 100644 Example/combinational_logic/full_adder/full_adder_sl.vhdl create mode 100644 Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl create mode 100644 Example/combinational_logic/full_adder/full_adder_slv.vhdl create mode 100644 Example/combinational_logic/full_adder/full_adder_structural.vhdl create mode 100644 Example/combinational_logic/half_adder/half_adder.vhdl create mode 100644 Example/combinational_logic/mux-demux/demux.vhdl create mode 100644 Example/combinational_logic/mux-demux/mux.vhdl delete mode 100644 Example/counter/up_counter.vhdl delete mode 100644 Example/counter/up_counter_slv.vhdl delete mode 100644 Example/decoder/decoder.vhdl delete mode 100644 Example/full_adder/full_adder_sl.vhdl delete mode 100644 Example/full_adder/full_adder_sl_slv.vhdl delete mode 100644 Example/full_adder/full_adder_slv.vhdl delete mode 100644 Example/full_adder/full_adder_structural.vhdl delete mode 100644 Example/half_adder/half_adder.vhdl create mode 100644 Example/logic_gates/and_gate.vhdl create mode 100644 Example/logic_gates/inverter.vhdl delete mode 100644 Example/logic_gates/inverter_gate.vhdl create mode 100644 Example/logic_gates/nand_gate.vhdl create mode 100644 Example/logic_gates/nor_gate.vhdl create mode 100644 Example/logic_gates/or_gate.vhdl delete mode 100644 Example/mux-demux/demux.vhdl delete mode 100644 Example/mux-demux/mux.vhdl (limited to 'Example') diff --git a/Example/README.md b/Example/README.md deleted file mode 100644 index e3eb0cf..0000000 --- a/Example/README.md +++ /dev/null @@ -1,9 +0,0 @@ -Instructions on how to use the examples provided here: -1. Go to eSim main window -> Click on NGHDL icon from the left toolbar, click on the 'browse' button, go to ../nghdl/Example/ and locate which example you wish to simulate. -2. After opening the directory of desired example, locate the vhdl file , click on the "Open" button at the bottom of "Open File" window. -3. Click on 'upload' button in the NGHDL pop-up window. File will be processed in the backend for few seconds. Now exit the NGHDL window. -4. Open the desired example in eSim using the Open Project button, double click on it when the project is loaded in the "Projects" window. -5. Click on the "Simulation" button on eSim Main window. - -NGHDL feature is still under development. More examples will be added by eSim team along the way. -If you have a good command on VHDL and electronics, please feel free to contribute. diff --git a/Example/bin_to_gray/bin_to_gray.vhdl b/Example/bin_to_gray/bin_to_gray.vhdl deleted file mode 100644 index d6045e8..0000000 --- a/Example/bin_to_gray/bin_to_gray.vhdl +++ /dev/null @@ -1,21 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - -entity bin_to_gray is -port( - bin : in std_logic_vector(3 downto 0); - G : out std_logic_vector(3 downto 0) - ); -end bin_to_gray; - - -architecture gate_level of bin_to_gray is - -begin - -G(3) <= bin(3); -G(2) <= bin(3) xor bin(2); -G(1) <= bin(2) xor bin(1); -G(0) <= bin(1) xor bin(0); - -end gate_level; \ No newline at end of file diff --git a/Example/combinational_logic/bin_to_gray/bin_to_gray.vhdl b/Example/combinational_logic/bin_to_gray/bin_to_gray.vhdl new file mode 100644 index 0000000..d6045e8 --- /dev/null +++ b/Example/combinational_logic/bin_to_gray/bin_to_gray.vhdl @@ -0,0 +1,21 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +entity bin_to_gray is +port( + bin : in std_logic_vector(3 downto 0); + G : out std_logic_vector(3 downto 0) + ); +end bin_to_gray; + + +architecture gate_level of bin_to_gray is + +begin + +G(3) <= bin(3); +G(2) <= bin(3) xor bin(2); +G(1) <= bin(2) xor bin(1); +G(0) <= bin(1) xor bin(0); + +end gate_level; \ No newline at end of file diff --git a/Example/combinational_logic/counter/counter.vhdl b/Example/combinational_logic/counter/counter.vhdl new file mode 100644 index 0000000..ba14df8 --- /dev/null +++ b/Example/combinational_logic/counter/counter.vhdl @@ -0,0 +1,30 @@ +library ieee; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity counter is +port(C : in std_logic; + CLR : in std_logic; + Q : out std_logic_vector(3 downto 0)); +end counter; + +architecture bhv of counter is + + signal tmp: std_logic_vector(3 downto 0); + begin + process (C, CLR) + + begin + if (CLR='1') then + tmp <= "0000"; + + elsif (C'event and C='1') then + tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length)); + + end if; + + end process; + Q <= tmp; + +end bhv; \ No newline at end of file diff --git a/Example/combinational_logic/counter/updown_counter.vhdl b/Example/combinational_logic/counter/updown_counter.vhdl new file mode 100644 index 0000000..922ee67 --- /dev/null +++ b/Example/combinational_logic/counter/updown_counter.vhdl @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + + +entity updown_counter is + Port ( clk: in std_logic; + reset: in std_logic; + up_down: in std_logic; + counter: out std_logic_vector(3 downto 0) + ); +end updown_counter; + +architecture Behavioral of updown_counter is +signal tmp: std_logic_vector(3 downto 0); +begin + +process(clk,reset) +begin + if(reset='1') then + tmp <= "0000"; + elsif(clk'event and clk='1') then + if(up_down='1') then + tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)-1), tmp'length)); + else + tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)+1), tmp'length)); + end if; + end if; +end process; + counter <= std_logic_vector(tmp); + +end Behavioral; \ No newline at end of file diff --git a/Example/combinational_logic/decoder/decoder.vhdl b/Example/combinational_logic/decoder/decoder.vhdl new file mode 100644 index 0000000..e429ec9 --- /dev/null +++ b/Example/combinational_logic/decoder/decoder.vhdl @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity decoder is +port ( + p : in std_logic_vector(4 downto 0); + d : out std_logic_vector(31 downto 0) + ); +end decoder; + +architecture behav of decoder is + +begin + +with p select +d<="00000000000000000000000000000001" when "00000", +"00000000000000000000000000000010" when "00001", +"00000000000000000000000000000100" when "00010", +"00000000000000000000000000001000" when "00011", +"00000000000000000000000000010000" when "00100", +"00000000000000000000000000100000" when "00101", +"00000000000000000000000001000000" when "00110", +"00000000000000000000000010000000" when "00111", +"00000000000000000000000100000000" when "01000", +"00000000000000000000001000000000" when "01001", +"00000000000000000000010000000000" when "01010", +"00000000000000000000100000000000" when "01011", +"00000000000000000001000000000000" when "01100", +"00000000000000000010000000000000" when "01101", +"00000000000000000100000000000000" when "01110", +"00000000000000001000000000000000" when "01111", +"00000000000000010000000000000000" when "10000", +"00000000000000100000000000000000" when "10001", +"00000000000001000000000000000000" when "10010", +"00000000000010000000000000000000" when "10011", +"00000000000100000000000000000000" when "10100", +"00000000001000000000000000000000" when "10101", +"00000000010000000000000000000000" when "10110", +"00000000100000000000000000000000" when "10111", +"00000001000000000000000000000000" when "11000", +"00000010000000000000000000000000" when "11001", +"00000100000000000000000000000000" when "11010", +"00001000000000000000000000000000" when "11011", +"00010000000000000000000000000000" when "11100", +"00100000000000000000000000000000" when "11101", +"01000000000000000000000000000000" when "11110", +"10000000000000000000000000000000" when "11111", +"00000000000000000000000000000000" when others; + +end behav; diff --git a/Example/combinational_logic/full_adder/full_adder_sl.vhdl b/Example/combinational_logic/full_adder/full_adder_sl.vhdl new file mode 100644 index 0000000..e830563 --- /dev/null +++ b/Example/combinational_logic/full_adder/full_adder_sl.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity full_adder_sl is + port ( + i_bit1 : in std_logic; + i_bit2 : in std_logic; + i_bit3 : in std_logic; + o_sum : out std_logic; + o_carry : out std_logic + ); +end full_adder_sl; + +architecture rtl of full_adder_sl is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3; + o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); +end rtl; \ No newline at end of file diff --git a/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl new file mode 100644 index 0000000..7de9c1b --- /dev/null +++ b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity full_adder_sl_slv is + port ( + i_bit1 : in std_logic; + i_bit2 : in std_logic; + i_bit3 : in std_logic_vector(0 downto 0); + o_sum : out std_logic; + o_carry : out std_logic_vector(0 downto 0) + ); +end full_adder_sl_slv; + +architecture rtl of full_adder_sl_slv is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3(0); + o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1); +end rtl; \ No newline at end of file diff --git a/Example/combinational_logic/full_adder/full_adder_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_slv.vhdl new file mode 100644 index 0000000..a0495f0 --- /dev/null +++ b/Example/combinational_logic/full_adder/full_adder_slv.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity full_adder_slv is + port ( + i_bit1 : in std_logic_vector(0 downto 0); + i_bit2 : in std_logic_vector(0 downto 0); + i_bit3 : in std_logic_vector(0 downto 0); + o_sum : out std_logic_vector(0 downto 0); + o_carry : out std_logic_vector(0 downto 0) + ); +end full_adder_slv; + +architecture rtl of full_adder_slv is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3; + o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); +end rtl; diff --git a/Example/combinational_logic/full_adder/full_adder_structural.vhdl b/Example/combinational_logic/full_adder/full_adder_structural.vhdl new file mode 100644 index 0000000..eb06a3d --- /dev/null +++ b/Example/combinational_logic/full_adder/full_adder_structural.vhdl @@ -0,0 +1,87 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity full_adder_structural is +port(a: in std_logic; + b: in std_logic; + cin: in std_logic; + sum: out std_logic; + carry: out std_logic); +end full_adder_structural; + +library ieee; +use ieee.std_logic_1164.all; + +entity andgate is +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end andgate; + +architecture e1 of andgate is +begin +z <= a and b; +end e1; + +library ieee; +use ieee.std_logic_1164.all; + +entity xorgate is +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end xorgate; + +architecture e2 of xorgate is +begin +z <= a xor b; +end e2; + +library ieee; +use ieee.std_logic_1164.all; + +entity orgate is +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end orgate; + +architecture e3 of orgate is +begin +z <= a or b; +end e3; + + + +architecture structural of full_adder_structural is + +component andgate +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end component; + +component xorgate +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end component; + +component orgate +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end component; + +signal c1,c2,c3: std_logic; + +begin + +u1 : xorgate port map(a,b,c1); +u2 : xorgate port map(c1,cin,sum); +u3 : andgate port map(c1,cin,c2); +u4 : andgate port map(a,b,c3); +u5 : orgate port map(c2,c3,carry); + + +end structural; \ No newline at end of file diff --git a/Example/combinational_logic/half_adder/half_adder.vhdl b/Example/combinational_logic/half_adder/half_adder.vhdl new file mode 100644 index 0000000..71ef1cc --- /dev/null +++ b/Example/combinational_logic/half_adder/half_adder.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity half_adder is + port ( + i_bit0 : in std_logic_vector(0 downto 0); + i_bit1 : in std_logic_vector(0 downto 0); + o_sum : out std_logic_vector(0 downto 0); + o_carry : out std_logic_vector(0 downto 0) + ); +end half_adder; + +architecture rtl of half_adder is +begin + o_sum <= i_bit0 xor i_bit1; + o_carry <= i_bit0 and i_bit1; +end rtl; diff --git a/Example/combinational_logic/mux-demux/demux.vhdl b/Example/combinational_logic/mux-demux/demux.vhdl new file mode 100644 index 0000000..e73c196 --- /dev/null +++ b/Example/combinational_logic/mux-demux/demux.vhdl @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity demux is + port( + + F : in STD_LOGIC_vector(0 downto 0); + S0: in STD_LOGIC_vector(0 downto 0); + S1: in STD_LOGIC_vector(0 downto 0); + A: out STD_LOGIC_vector(0 downto 0); + B: out STD_LOGIC_vector(0 downto 0); + C: out STD_LOGIC_vector(0 downto 0); + D: out STD_LOGIC_vector(0 downto 0) + ); +end demux; + +architecture bhv of demux is +begin +process (F,S0,S1) is +begin + if (S0 ="0" and S1 = "0") then + A <= F; + elsif (S0 ="1" and S1 = "0") then + B <= F; + elsif (S0 ="0" and S1 = "1") then + C <= F; + else + D <= F; + end if; + +end process; +end bhv; diff --git a/Example/combinational_logic/mux-demux/mux.vhdl b/Example/combinational_logic/mux-demux/mux.vhdl new file mode 100644 index 0000000..b72e287 --- /dev/null +++ b/Example/combinational_logic/mux-demux/mux.vhdl @@ -0,0 +1,30 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity mux is + port(A : in std_logic; + B : in std_logic; + C : in std_logic; + D : in std_logic; + S0 : in std_logic; + S1 : in std_logic; + Z: out std_logic); +end mux; + +architecture bhv of mux is +begin +process (A,B,C,D,S0,S1) is +begin + if (S0 ='0' and S1 = '0') then + Z <= A; + elsif (S0 ='0' and S1 = '1') then + Z <= B; + elsif (S0 ='1' and S1 = '0') then + Z <= C; + else + Z <= D; + end if; + +end process; +end bhv; + diff --git a/Example/counter/up_counter.vhdl b/Example/counter/up_counter.vhdl deleted file mode 100644 index bd27fcf..0000000 --- a/Example/counter/up_counter.vhdl +++ /dev/null @@ -1,34 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity up_counter is - port(Clock : in std_logic; - CLR : in std_logic; - Q : out std_logic_vector(3 downto 0)); -end up_counter; - -architecture beh of up_counter is - signal tmp: unsigned(3 downto 0) := "0000"; - - --------------- Other ways to initialize -------------- - -- signal tmp: unsigned(3 downto 0) := x"0"; - -- signal tmp: unsigned(3 downto 0) := (others => '0'); - ------------------------------------------------------- - - begin - process (Clock, CLR) - begin - if (CLR='1') then - tmp <= "0000"; - elsif (Clock'event and Clock='1') then - if tmp="1111" then - tmp <= x"0"; - else - tmp <= tmp +1; - end if; - end if; - end process; - - Q <= std_logic_vector (tmp); -end beh; \ No newline at end of file diff --git a/Example/counter/up_counter_slv.vhdl b/Example/counter/up_counter_slv.vhdl deleted file mode 100644 index afef463..0000000 --- a/Example/counter/up_counter_slv.vhdl +++ /dev/null @@ -1,24 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity up_counter_slv is -port(C : in std_logic; - CLR : in std_logic; - Q : out std_logic_vector(3 downto 0)); -end up_counter_slv; - -architecture bhv of up_counter_slv is - signal tmp: std_logic_vector(3 downto 0); - begin - process (C, CLR) - begin - if (CLR='1') then - tmp <= "0000"; - elsif (C'event and C='1') then - tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length)); - end if; - end process; - Q <= tmp; - -end bhv; \ No newline at end of file diff --git a/Example/decoder/decoder.vhdl b/Example/decoder/decoder.vhdl deleted file mode 100644 index e429ec9..0000000 --- a/Example/decoder/decoder.vhdl +++ /dev/null @@ -1,50 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity decoder is -port ( - p : in std_logic_vector(4 downto 0); - d : out std_logic_vector(31 downto 0) - ); -end decoder; - -architecture behav of decoder is - -begin - -with p select -d<="00000000000000000000000000000001" when "00000", -"00000000000000000000000000000010" when "00001", -"00000000000000000000000000000100" when "00010", -"00000000000000000000000000001000" when "00011", -"00000000000000000000000000010000" when "00100", -"00000000000000000000000000100000" when "00101", -"00000000000000000000000001000000" when "00110", -"00000000000000000000000010000000" when "00111", -"00000000000000000000000100000000" when "01000", -"00000000000000000000001000000000" when "01001", -"00000000000000000000010000000000" when "01010", -"00000000000000000000100000000000" when "01011", -"00000000000000000001000000000000" when "01100", -"00000000000000000010000000000000" when "01101", -"00000000000000000100000000000000" when "01110", -"00000000000000001000000000000000" when "01111", -"00000000000000010000000000000000" when "10000", -"00000000000000100000000000000000" when "10001", -"00000000000001000000000000000000" when "10010", -"00000000000010000000000000000000" when "10011", -"00000000000100000000000000000000" when "10100", -"00000000001000000000000000000000" when "10101", -"00000000010000000000000000000000" when "10110", -"00000000100000000000000000000000" when "10111", -"00000001000000000000000000000000" when "11000", -"00000010000000000000000000000000" when "11001", -"00000100000000000000000000000000" when "11010", -"00001000000000000000000000000000" when "11011", -"00010000000000000000000000000000" when "11100", -"00100000000000000000000000000000" when "11101", -"01000000000000000000000000000000" when "11110", -"10000000000000000000000000000000" when "11111", -"00000000000000000000000000000000" when others; - -end behav; diff --git a/Example/full_adder/full_adder_sl.vhdl b/Example/full_adder/full_adder_sl.vhdl deleted file mode 100644 index e830563..0000000 --- a/Example/full_adder/full_adder_sl.vhdl +++ /dev/null @@ -1,19 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity full_adder_sl is - port ( - i_bit1 : in std_logic; - i_bit2 : in std_logic; - i_bit3 : in std_logic; - o_sum : out std_logic; - o_carry : out std_logic - ); -end full_adder_sl; - -architecture rtl of full_adder_sl is -begin - o_sum <= i_bit1 xor i_bit2 xor i_bit3; - o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); -end rtl; \ No newline at end of file diff --git a/Example/full_adder/full_adder_sl_slv.vhdl b/Example/full_adder/full_adder_sl_slv.vhdl deleted file mode 100644 index 7de9c1b..0000000 --- a/Example/full_adder/full_adder_sl_slv.vhdl +++ /dev/null @@ -1,19 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity full_adder_sl_slv is - port ( - i_bit1 : in std_logic; - i_bit2 : in std_logic; - i_bit3 : in std_logic_vector(0 downto 0); - o_sum : out std_logic; - o_carry : out std_logic_vector(0 downto 0) - ); -end full_adder_sl_slv; - -architecture rtl of full_adder_sl_slv is -begin - o_sum <= i_bit1 xor i_bit2 xor i_bit3(0); - o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1); -end rtl; \ No newline at end of file diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/full_adder/full_adder_slv.vhdl deleted file mode 100644 index a0495f0..0000000 --- a/Example/full_adder/full_adder_slv.vhdl +++ /dev/null @@ -1,19 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity full_adder_slv is - port ( - i_bit1 : in std_logic_vector(0 downto 0); - i_bit2 : in std_logic_vector(0 downto 0); - i_bit3 : in std_logic_vector(0 downto 0); - o_sum : out std_logic_vector(0 downto 0); - o_carry : out std_logic_vector(0 downto 0) - ); -end full_adder_slv; - -architecture rtl of full_adder_slv is -begin - o_sum <= i_bit1 xor i_bit2 xor i_bit3; - o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); -end rtl; diff --git a/Example/full_adder/full_adder_structural.vhdl b/Example/full_adder/full_adder_structural.vhdl deleted file mode 100644 index eb06a3d..0000000 --- a/Example/full_adder/full_adder_structural.vhdl +++ /dev/null @@ -1,87 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity full_adder_structural is -port(a: in std_logic; - b: in std_logic; - cin: in std_logic; - sum: out std_logic; - carry: out std_logic); -end full_adder_structural; - -library ieee; -use ieee.std_logic_1164.all; - -entity andgate is -port(a: in std_logic; - b: in std_logic; - z: out std_logic); -end andgate; - -architecture e1 of andgate is -begin -z <= a and b; -end e1; - -library ieee; -use ieee.std_logic_1164.all; - -entity xorgate is -port(a: in std_logic; - b: in std_logic; - z: out std_logic); -end xorgate; - -architecture e2 of xorgate is -begin -z <= a xor b; -end e2; - -library ieee; -use ieee.std_logic_1164.all; - -entity orgate is -port(a: in std_logic; - b: in std_logic; - z: out std_logic); -end orgate; - -architecture e3 of orgate is -begin -z <= a or b; -end e3; - - - -architecture structural of full_adder_structural is - -component andgate -port(a: in std_logic; - b: in std_logic; - z: out std_logic); -end component; - -component xorgate -port(a: in std_logic; - b: in std_logic; - z: out std_logic); -end component; - -component orgate -port(a: in std_logic; - b: in std_logic; - z: out std_logic); -end component; - -signal c1,c2,c3: std_logic; - -begin - -u1 : xorgate port map(a,b,c1); -u2 : xorgate port map(c1,cin,sum); -u3 : andgate port map(c1,cin,c2); -u4 : andgate port map(a,b,c3); -u5 : orgate port map(c2,c3,carry); - - -end structural; \ No newline at end of file diff --git a/Example/half_adder/half_adder.vhdl b/Example/half_adder/half_adder.vhdl deleted file mode 100644 index 71ef1cc..0000000 --- a/Example/half_adder/half_adder.vhdl +++ /dev/null @@ -1,18 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity half_adder is - port ( - i_bit0 : in std_logic_vector(0 downto 0); - i_bit1 : in std_logic_vector(0 downto 0); - o_sum : out std_logic_vector(0 downto 0); - o_carry : out std_logic_vector(0 downto 0) - ); -end half_adder; - -architecture rtl of half_adder is -begin - o_sum <= i_bit0 xor i_bit1; - o_carry <= i_bit0 and i_bit1; -end rtl; diff --git a/Example/logic_gates/and_gate.vhdl b/Example/logic_gates/and_gate.vhdl new file mode 100644 index 0000000..689bcba --- /dev/null +++ b/Example/logic_gates/and_gate.vhdl @@ -0,0 +1,33 @@ +library ieee; + +use ieee.std_logic_1164.all; + +entity and_gate is + +port( a: in std_logic; + b: in std_logic; + c: out std_logic +); + +end and_gate; + +architecture beh of and_gate is + + begin + + process(a, b) + + begin + + if (a='1' and b='1') then + c <= '1'; + + else + + c <= '0'; + + end if; + + end process; + +end beh; diff --git a/Example/logic_gates/inverter.vhdl b/Example/logic_gates/inverter.vhdl new file mode 100644 index 0000000..ee2d830 --- /dev/null +++ b/Example/logic_gates/inverter.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity inverter is + port ( i: in std_logic; + o: out std_logic); +end inverter; + +architecture beh of inverter is +begin + o <= not i; +end beh; + + diff --git a/Example/logic_gates/inverter_gate.vhdl b/Example/logic_gates/inverter_gate.vhdl deleted file mode 100644 index 9825917..0000000 --- a/Example/logic_gates/inverter_gate.vhdl +++ /dev/null @@ -1,14 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity inverter_gate is - port ( i: in std_logic; - o: out std_logic); -end inverter_gate; - -architecture beh of inverter_gate is -begin - o <= not i; -end beh; - - diff --git a/Example/logic_gates/nand_gate.vhdl b/Example/logic_gates/nand_gate.vhdl new file mode 100644 index 0000000..3736285 --- /dev/null +++ b/Example/logic_gates/nand_gate.vhdl @@ -0,0 +1,33 @@ +library ieee; + +use ieee.std_logic_1164.all; + +entity nand_gate is + +port( a: in std_logic; + b: in std_logic; + c: out std_logic +); + +end nand_gate; + +architecture beh of nand_gate is + + begin + + process(a, b) + + begin + + if (a='1' and b='1') then + c <= '0'; + + else + + c <= '1'; + + end if; + + end process; + +end beh; diff --git a/Example/logic_gates/nor_gate.vhdl b/Example/logic_gates/nor_gate.vhdl new file mode 100644 index 0000000..0dcdab0 --- /dev/null +++ b/Example/logic_gates/nor_gate.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity nor_gate is + port (a : in std_logic; + b : in std_logic; + c : out std_logic); +end nor_gate; + +architecture rtl of nor_gate is + begin + c <= a nor b; +end rtl; diff --git a/Example/logic_gates/or_gate.vhdl b/Example/logic_gates/or_gate.vhdl new file mode 100644 index 0000000..d470c3d --- /dev/null +++ b/Example/logic_gates/or_gate.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity or_gate is + Port ( a : in STD_LOGIC; + b : in STD_LOGIC; + c : out STD_LOGIC); +end or_gate; + +architecture behavioral of or_gate is +begin +c <= a or b; +end behavioral; diff --git a/Example/mux-demux/demux.vhdl b/Example/mux-demux/demux.vhdl deleted file mode 100644 index e73c196..0000000 --- a/Example/mux-demux/demux.vhdl +++ /dev/null @@ -1,32 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -entity demux is - port( - - F : in STD_LOGIC_vector(0 downto 0); - S0: in STD_LOGIC_vector(0 downto 0); - S1: in STD_LOGIC_vector(0 downto 0); - A: out STD_LOGIC_vector(0 downto 0); - B: out STD_LOGIC_vector(0 downto 0); - C: out STD_LOGIC_vector(0 downto 0); - D: out STD_LOGIC_vector(0 downto 0) - ); -end demux; - -architecture bhv of demux is -begin -process (F,S0,S1) is -begin - if (S0 ="0" and S1 = "0") then - A <= F; - elsif (S0 ="1" and S1 = "0") then - B <= F; - elsif (S0 ="0" and S1 = "1") then - C <= F; - else - D <= F; - end if; - -end process; -end bhv; diff --git a/Example/mux-demux/mux.vhdl b/Example/mux-demux/mux.vhdl deleted file mode 100644 index b72e287..0000000 --- a/Example/mux-demux/mux.vhdl +++ /dev/null @@ -1,30 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -entity mux is - port(A : in std_logic; - B : in std_logic; - C : in std_logic; - D : in std_logic; - S0 : in std_logic; - S1 : in std_logic; - Z: out std_logic); -end mux; - -architecture bhv of mux is -begin -process (A,B,C,D,S0,S1) is -begin - if (S0 ='0' and S1 = '0') then - Z <= A; - elsif (S0 ='0' and S1 = '1') then - Z <= B; - elsif (S0 ='1' and S1 = '0') then - Z <= C; - else - Z <= D; - end if; - -end process; -end bhv; - -- cgit