From a81c4ecb38dc18f36688113c6fa1b28a84802183 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:52:11 +0530
Subject: Update and rename trial_fa.vhdl to full_adder.vhdl

---
 Example/full_adder/full_adder.vhdl | 19 +++++++++++++++++++
 Example/full_adder/trial_fa.vhdl   | 19 -------------------
 2 files changed, 19 insertions(+), 19 deletions(-)
 create mode 100644 Example/full_adder/full_adder.vhdl
 delete mode 100644 Example/full_adder/trial_fa.vhdl

(limited to 'Example')

diff --git a/Example/full_adder/full_adder.vhdl b/Example/full_adder/full_adder.vhdl
new file mode 100644
index 0000000..745fac3
--- /dev/null
+++ b/Example/full_adder/full_adder.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder is
+  port (
+    i_bit1  : in std_logic_vector(0 downto 0);
+    i_bit2  : in std_logic_vector(0 downto 0);
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end full_adder;
+ 
+architecture rtl of full_adder is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
diff --git a/Example/full_adder/trial_fa.vhdl b/Example/full_adder/trial_fa.vhdl
deleted file mode 100644
index 6357aa2..0000000
--- a/Example/full_adder/trial_fa.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity trial_fa is
-  port (
-    i_bit1  : in std_logic_vector(0 downto 0);
-    i_bit2  : in std_logic_vector(0 downto 0);
-    i_bit3  : in std_logic_vector(0 downto 0);
-    o_sum   : out std_logic_vector(0 downto 0);
-    o_carry : out std_logic_vector(0 downto 0)
-    );
-end trial_fa;
- 
-architecture rtl of trial_fa is
-begin
-  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
-  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
-end rtl;
\ No newline at end of file
-- 
cgit