From d239a1c81f01e8a76344b9ee20ab30fc49615672 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:46:27 +0530
Subject: Create readme.md

---
 Example/half_adder/readme.md | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 Example/half_adder/readme.md

(limited to 'Example')

diff --git a/Example/half_adder/readme.md b/Example/half_adder/readme.md
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/Example/half_adder/readme.md
@@ -0,0 +1 @@
+
-- 
cgit 


From c3ef8e2a074372ddb0fe4686b51f446117b0fd29 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:46:49 +0530
Subject: Create readme.md

---
 Example/full_adder/readme.md | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 Example/full_adder/readme.md

(limited to 'Example')

diff --git a/Example/full_adder/readme.md b/Example/full_adder/readme.md
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/Example/full_adder/readme.md
@@ -0,0 +1 @@
+
-- 
cgit 


From f166e8d1bc872bbf7425da95defecae920b2e39e Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:47:10 +0530
Subject: Create readme.md

---
 Example/demux/readme.md | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 Example/demux/readme.md

(limited to 'Example')

diff --git a/Example/demux/readme.md b/Example/demux/readme.md
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/Example/demux/readme.md
@@ -0,0 +1 @@
+
-- 
cgit 


From 3bc50a214b4dbac28cbe980f631ec9ac4c6735fc Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:47:45 +0530
Subject: Add files via upload

---
 Example/full_adder/trial_ha.vhdl | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Example/full_adder/trial_ha.vhdl

(limited to 'Example')

diff --git a/Example/full_adder/trial_ha.vhdl b/Example/full_adder/trial_ha.vhdl
new file mode 100644
index 0000000..30e7938
--- /dev/null
+++ b/Example/full_adder/trial_ha.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity trial_ha is
+  port (
+    i_bit  : in std_logic_vector(1 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end trial_ha;
+ 
+architecture rtl of trial_ha is
+begin
+  o_sum   <= i_bit(0) xor i_bit(1);
+  o_carry <= i_bit(0) and i_bit(1);
+end rtl;
\ No newline at end of file
-- 
cgit 


From bfd56aecafe2cbc0693aaa2adf514f2270843969 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:48:12 +0530
Subject: Add files via upload

---
 Example/half_adder/trial_ha.vhdl | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Example/half_adder/trial_ha.vhdl

(limited to 'Example')

diff --git a/Example/half_adder/trial_ha.vhdl b/Example/half_adder/trial_ha.vhdl
new file mode 100644
index 0000000..30e7938
--- /dev/null
+++ b/Example/half_adder/trial_ha.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity trial_ha is
+  port (
+    i_bit  : in std_logic_vector(1 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end trial_ha;
+ 
+architecture rtl of trial_ha is
+begin
+  o_sum   <= i_bit(0) xor i_bit(1);
+  o_carry <= i_bit(0) and i_bit(1);
+end rtl;
\ No newline at end of file
-- 
cgit 


From b4168eaf495fdfb1d36df115f5f2d0ae74b7fbaa Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:48:47 +0530
Subject: Delete readme.md

---
 Example/half_adder/readme.md | 1 -
 1 file changed, 1 deletion(-)
 delete mode 100644 Example/half_adder/readme.md

(limited to 'Example')

diff --git a/Example/half_adder/readme.md b/Example/half_adder/readme.md
deleted file mode 100644
index 8b13789..0000000
--- a/Example/half_adder/readme.md
+++ /dev/null
@@ -1 +0,0 @@
-
-- 
cgit 


From e3076fbf6c6eb5f1aab8eef8ceaa3870ec1ea6a9 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:50:26 +0530
Subject: Update and rename trial_ha.vhdl to half_adder.vhdl

---
 Example/half_adder/half_adder.vhdl | 18 ++++++++++++++++++
 Example/half_adder/trial_ha.vhdl   | 17 -----------------
 2 files changed, 18 insertions(+), 17 deletions(-)
 create mode 100644 Example/half_adder/half_adder.vhdl
 delete mode 100644 Example/half_adder/trial_ha.vhdl

(limited to 'Example')

diff --git a/Example/half_adder/half_adder.vhdl b/Example/half_adder/half_adder.vhdl
new file mode 100644
index 0000000..71ef1cc
--- /dev/null
+++ b/Example/half_adder/half_adder.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity half_adder is
+  port (
+    i_bit0  : in std_logic_vector(0 downto 0);
+    i_bit1  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end half_adder;
+ 
+architecture rtl of half_adder is
+begin
+  o_sum   <= i_bit0 xor i_bit1;
+  o_carry <= i_bit0 and i_bit1;
+end rtl;
diff --git a/Example/half_adder/trial_ha.vhdl b/Example/half_adder/trial_ha.vhdl
deleted file mode 100644
index 30e7938..0000000
--- a/Example/half_adder/trial_ha.vhdl
+++ /dev/null
@@ -1,17 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity trial_ha is
-  port (
-    i_bit  : in std_logic_vector(1 downto 0);
-    o_sum   : out std_logic_vector(0 downto 0);
-    o_carry : out std_logic_vector(0 downto 0)
-    );
-end trial_ha;
- 
-architecture rtl of trial_ha is
-begin
-  o_sum   <= i_bit(0) xor i_bit(1);
-  o_carry <= i_bit(0) and i_bit(1);
-end rtl;
\ No newline at end of file
-- 
cgit 


From 9300750cc60402eb73595173af696cea6345b9ca Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:50:46 +0530
Subject: Delete readme.md

---
 Example/full_adder/readme.md | 1 -
 1 file changed, 1 deletion(-)
 delete mode 100644 Example/full_adder/readme.md

(limited to 'Example')

diff --git a/Example/full_adder/readme.md b/Example/full_adder/readme.md
deleted file mode 100644
index 8b13789..0000000
--- a/Example/full_adder/readme.md
+++ /dev/null
@@ -1 +0,0 @@
-
-- 
cgit 


From aa538a95b5ff747ad9fa3455ac2a6c88dcb0becb Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:51:11 +0530
Subject: Add files via upload

---
 Example/full_adder/trial_fa.vhdl | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Example/full_adder/trial_fa.vhdl

(limited to 'Example')

diff --git a/Example/full_adder/trial_fa.vhdl b/Example/full_adder/trial_fa.vhdl
new file mode 100644
index 0000000..6357aa2
--- /dev/null
+++ b/Example/full_adder/trial_fa.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity trial_fa is
+  port (
+    i_bit1  : in std_logic_vector(0 downto 0);
+    i_bit2  : in std_logic_vector(0 downto 0);
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end trial_fa;
+ 
+architecture rtl of trial_fa is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
\ No newline at end of file
-- 
cgit 


From 26543fb77ba71c77292547f64b24d1fb0658ec72 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:51:28 +0530
Subject: Delete trial_ha.vhdl

---
 Example/full_adder/trial_ha.vhdl | 17 -----------------
 1 file changed, 17 deletions(-)
 delete mode 100644 Example/full_adder/trial_ha.vhdl

(limited to 'Example')

diff --git a/Example/full_adder/trial_ha.vhdl b/Example/full_adder/trial_ha.vhdl
deleted file mode 100644
index 30e7938..0000000
--- a/Example/full_adder/trial_ha.vhdl
+++ /dev/null
@@ -1,17 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity trial_ha is
-  port (
-    i_bit  : in std_logic_vector(1 downto 0);
-    o_sum   : out std_logic_vector(0 downto 0);
-    o_carry : out std_logic_vector(0 downto 0)
-    );
-end trial_ha;
- 
-architecture rtl of trial_ha is
-begin
-  o_sum   <= i_bit(0) xor i_bit(1);
-  o_carry <= i_bit(0) and i_bit(1);
-end rtl;
\ No newline at end of file
-- 
cgit 


From a81c4ecb38dc18f36688113c6fa1b28a84802183 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:52:11 +0530
Subject: Update and rename trial_fa.vhdl to full_adder.vhdl

---
 Example/full_adder/full_adder.vhdl | 19 +++++++++++++++++++
 Example/full_adder/trial_fa.vhdl   | 19 -------------------
 2 files changed, 19 insertions(+), 19 deletions(-)
 create mode 100644 Example/full_adder/full_adder.vhdl
 delete mode 100644 Example/full_adder/trial_fa.vhdl

(limited to 'Example')

diff --git a/Example/full_adder/full_adder.vhdl b/Example/full_adder/full_adder.vhdl
new file mode 100644
index 0000000..745fac3
--- /dev/null
+++ b/Example/full_adder/full_adder.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder is
+  port (
+    i_bit1  : in std_logic_vector(0 downto 0);
+    i_bit2  : in std_logic_vector(0 downto 0);
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end full_adder;
+ 
+architecture rtl of full_adder is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
diff --git a/Example/full_adder/trial_fa.vhdl b/Example/full_adder/trial_fa.vhdl
deleted file mode 100644
index 6357aa2..0000000
--- a/Example/full_adder/trial_fa.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity trial_fa is
-  port (
-    i_bit1  : in std_logic_vector(0 downto 0);
-    i_bit2  : in std_logic_vector(0 downto 0);
-    i_bit3  : in std_logic_vector(0 downto 0);
-    o_sum   : out std_logic_vector(0 downto 0);
-    o_carry : out std_logic_vector(0 downto 0)
-    );
-end trial_fa;
- 
-architecture rtl of trial_fa is
-begin
-  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
-  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
-end rtl;
\ No newline at end of file
-- 
cgit 


From 8a4061e6b4aae0664e69cc09b28697742936149a Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:52:35 +0530
Subject: Add files via upload

---
 Example/demux/t_demux.vhdl | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 Example/demux/t_demux.vhdl

(limited to 'Example')

diff --git a/Example/demux/t_demux.vhdl b/Example/demux/t_demux.vhdl
new file mode 100644
index 0000000..1e1f0bd
--- /dev/null
+++ b/Example/demux/t_demux.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity t_demux is
+ port(
+
+ F : in STD_LOGIC_vector(0 downto 0);
+ S0: in STD_LOGIC_vector(0 downto 0);
+ S1: in STD_LOGIC_vector(0 downto 0);
+ A: out STD_LOGIC_vector(0 downto 0);
+ B: out STD_LOGIC_vector(0 downto 0);
+ C: out STD_LOGIC_vector(0 downto 0);
+ D: out STD_LOGIC_vector(0 downto 0)
+ );
+end t_demux;
+
+architecture bhv of t_demux is
+begin
+process (F,S0,S1) is
+begin
+ if (S0 ="0" and S1 = "0") then
+ A <= F;
+ elsif (S0 ="1" and S1 = "0") then
+ B <= F;
+ elsif (S0 ="0" and S1 = "1") then
+ C <= F;
+ else
+ D <= F;
+ end if;
+
+end process;
+end bhv;
\ No newline at end of file
-- 
cgit 


From 9e80e87f39b65b91824e46c131fa98987a7e25f0 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:52:54 +0530
Subject: Delete readme.md

---
 Example/demux/readme.md | 1 -
 1 file changed, 1 deletion(-)
 delete mode 100644 Example/demux/readme.md

(limited to 'Example')

diff --git a/Example/demux/readme.md b/Example/demux/readme.md
deleted file mode 100644
index 8b13789..0000000
--- a/Example/demux/readme.md
+++ /dev/null
@@ -1 +0,0 @@
-
-- 
cgit 


From 42d57e78441f4b38ada6ff230cf6789a80faa4c0 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:53:28 +0530
Subject: Update and rename t_demux.vhdl to demux.vhdl

---
 Example/demux/demux.vhdl   | 32 ++++++++++++++++++++++++++++++++
 Example/demux/t_demux.vhdl | 32 --------------------------------
 2 files changed, 32 insertions(+), 32 deletions(-)
 create mode 100644 Example/demux/demux.vhdl
 delete mode 100644 Example/demux/t_demux.vhdl

(limited to 'Example')

diff --git a/Example/demux/demux.vhdl b/Example/demux/demux.vhdl
new file mode 100644
index 0000000..e73c196
--- /dev/null
+++ b/Example/demux/demux.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity demux is
+ port(
+
+ F : in STD_LOGIC_vector(0 downto 0);
+ S0: in STD_LOGIC_vector(0 downto 0);
+ S1: in STD_LOGIC_vector(0 downto 0);
+ A: out STD_LOGIC_vector(0 downto 0);
+ B: out STD_LOGIC_vector(0 downto 0);
+ C: out STD_LOGIC_vector(0 downto 0);
+ D: out STD_LOGIC_vector(0 downto 0)
+ );
+end demux;
+
+architecture bhv of demux is
+begin
+process (F,S0,S1) is
+begin
+ if (S0 ="0" and S1 = "0") then
+ A <= F;
+ elsif (S0 ="1" and S1 = "0") then
+ B <= F;
+ elsif (S0 ="0" and S1 = "1") then
+ C <= F;
+ else
+ D <= F;
+ end if;
+
+end process;
+end bhv;
diff --git a/Example/demux/t_demux.vhdl b/Example/demux/t_demux.vhdl
deleted file mode 100644
index 1e1f0bd..0000000
--- a/Example/demux/t_demux.vhdl
+++ /dev/null
@@ -1,32 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity t_demux is
- port(
-
- F : in STD_LOGIC_vector(0 downto 0);
- S0: in STD_LOGIC_vector(0 downto 0);
- S1: in STD_LOGIC_vector(0 downto 0);
- A: out STD_LOGIC_vector(0 downto 0);
- B: out STD_LOGIC_vector(0 downto 0);
- C: out STD_LOGIC_vector(0 downto 0);
- D: out STD_LOGIC_vector(0 downto 0)
- );
-end t_demux;
-
-architecture bhv of t_demux is
-begin
-process (F,S0,S1) is
-begin
- if (S0 ="0" and S1 = "0") then
- A <= F;
- elsif (S0 ="1" and S1 = "0") then
- B <= F;
- elsif (S0 ="0" and S1 = "1") then
- C <= F;
- else
- D <= F;
- end if;
-
-end process;
-end bhv;
\ No newline at end of file
-- 
cgit 


From a6394b20adf8176755d6f16e86550a8ffb14b5a7 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Sun, 7 Jul 2019 18:39:16 +0530
Subject: Update and rename full_adder.vhdl to full_adder_slv.vhdl

---
 Example/full_adder/full_adder.vhdl     | 19 -------------------
 Example/full_adder/full_adder_slv.vhdl | 19 +++++++++++++++++++
 2 files changed, 19 insertions(+), 19 deletions(-)
 delete mode 100644 Example/full_adder/full_adder.vhdl
 create mode 100644 Example/full_adder/full_adder_slv.vhdl

(limited to 'Example')

diff --git a/Example/full_adder/full_adder.vhdl b/Example/full_adder/full_adder.vhdl
deleted file mode 100644
index 745fac3..0000000
--- a/Example/full_adder/full_adder.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity full_adder is
-  port (
-    i_bit1  : in std_logic_vector(0 downto 0);
-    i_bit2  : in std_logic_vector(0 downto 0);
-    i_bit3  : in std_logic_vector(0 downto 0);
-    o_sum   : out std_logic_vector(0 downto 0);
-    o_carry : out std_logic_vector(0 downto 0)
-    );
-end full_adder;
- 
-architecture rtl of full_adder is
-begin
-  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
-  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
-end rtl;
diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/full_adder/full_adder_slv.vhdl
new file mode 100644
index 0000000..a0495f0
--- /dev/null
+++ b/Example/full_adder/full_adder_slv.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_slv is
+  port (
+    i_bit1  : in std_logic_vector(0 downto 0);
+    i_bit2  : in std_logic_vector(0 downto 0);
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end full_adder_slv;
+ 
+architecture rtl of full_adder_slv is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
-- 
cgit 


From 7193220d6958627f268aec77efb9f6baf6ee4a9c Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Sun, 7 Jul 2019 18:47:08 +0530
Subject: std_logic with std_logic_vector

---
 Example/full_adder/full_adder_sl_slv.vhdl | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Example/full_adder/full_adder_sl_slv.vhdl

(limited to 'Example')

diff --git a/Example/full_adder/full_adder_sl_slv.vhdl b/Example/full_adder/full_adder_sl_slv.vhdl
new file mode 100644
index 0000000..7de9c1b
--- /dev/null
+++ b/Example/full_adder/full_adder_sl_slv.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_sl_slv is
+  port (
+    i_bit1  : in std_logic;
+    i_bit2  : in std_logic;
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic;
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end full_adder_sl_slv;
+ 
+architecture rtl of full_adder_sl_slv is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3(0);
+  o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1);
+end rtl;
\ No newline at end of file
-- 
cgit 


From 45f2669e5ba6760c6adaacb564c0799d54a11052 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Sun, 7 Jul 2019 18:48:17 +0530
Subject: std_logic_vector

---
 Example/full_adder/full_adder_sl.vhdl  | 19 +++++++++++++++++++
 Example/full_adder/full_adder_slv.vhdl | 19 -------------------
 2 files changed, 19 insertions(+), 19 deletions(-)
 create mode 100644 Example/full_adder/full_adder_sl.vhdl
 delete mode 100644 Example/full_adder/full_adder_slv.vhdl

(limited to 'Example')

diff --git a/Example/full_adder/full_adder_sl.vhdl b/Example/full_adder/full_adder_sl.vhdl
new file mode 100644
index 0000000..a0495f0
--- /dev/null
+++ b/Example/full_adder/full_adder_sl.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_slv is
+  port (
+    i_bit1  : in std_logic_vector(0 downto 0);
+    i_bit2  : in std_logic_vector(0 downto 0);
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end full_adder_slv;
+ 
+architecture rtl of full_adder_slv is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/full_adder/full_adder_slv.vhdl
deleted file mode 100644
index a0495f0..0000000
--- a/Example/full_adder/full_adder_slv.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity full_adder_slv is
-  port (
-    i_bit1  : in std_logic_vector(0 downto 0);
-    i_bit2  : in std_logic_vector(0 downto 0);
-    i_bit3  : in std_logic_vector(0 downto 0);
-    o_sum   : out std_logic_vector(0 downto 0);
-    o_carry : out std_logic_vector(0 downto 0)
-    );
-end full_adder_slv;
- 
-architecture rtl of full_adder_slv is
-begin
-  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
-  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
-end rtl;
-- 
cgit 


From 385d1b79fa4d4a4c9fe39f72cd87d53b247704d4 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Sun, 7 Jul 2019 18:48:39 +0530
Subject: std_logic_vector

---
 Example/full_adder/full_adder_sl.vhdl  | 19 -------------------
 Example/full_adder/full_adder_slv.vhdl | 19 +++++++++++++++++++
 2 files changed, 19 insertions(+), 19 deletions(-)
 delete mode 100644 Example/full_adder/full_adder_sl.vhdl
 create mode 100644 Example/full_adder/full_adder_slv.vhdl

(limited to 'Example')

diff --git a/Example/full_adder/full_adder_sl.vhdl b/Example/full_adder/full_adder_sl.vhdl
deleted file mode 100644
index a0495f0..0000000
--- a/Example/full_adder/full_adder_sl.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity full_adder_slv is
-  port (
-    i_bit1  : in std_logic_vector(0 downto 0);
-    i_bit2  : in std_logic_vector(0 downto 0);
-    i_bit3  : in std_logic_vector(0 downto 0);
-    o_sum   : out std_logic_vector(0 downto 0);
-    o_carry : out std_logic_vector(0 downto 0)
-    );
-end full_adder_slv;
- 
-architecture rtl of full_adder_slv is
-begin
-  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
-  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
-end rtl;
diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/full_adder/full_adder_slv.vhdl
new file mode 100644
index 0000000..a0495f0
--- /dev/null
+++ b/Example/full_adder/full_adder_slv.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_slv is
+  port (
+    i_bit1  : in std_logic_vector(0 downto 0);
+    i_bit2  : in std_logic_vector(0 downto 0);
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end full_adder_slv;
+ 
+architecture rtl of full_adder_slv is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
-- 
cgit 


From 0f8995a96904608b5e7a596d30547225f92e83be Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Sun, 7 Jul 2019 18:51:12 +0530
Subject: std_logic

---
 Example/full_adder/full_adder_sl.vhdl | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Example/full_adder/full_adder_sl.vhdl

(limited to 'Example')

diff --git a/Example/full_adder/full_adder_sl.vhdl b/Example/full_adder/full_adder_sl.vhdl
new file mode 100644
index 0000000..e830563
--- /dev/null
+++ b/Example/full_adder/full_adder_sl.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_sl is
+  port (
+    i_bit1  : in std_logic;
+    i_bit2  : in std_logic;
+    i_bit3  : in std_logic;
+    o_sum   : out std_logic;
+    o_carry : out std_logic
+    );
+end full_adder_sl;
+ 
+architecture rtl of full_adder_sl is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
\ No newline at end of file
-- 
cgit 


From a9586e8be49a37bbf4bd20580ab6ad4763544c12 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Wed, 10 Jul 2019 21:51:10 +0530
Subject: structural style

---
 Example/full_adder/full_adder_structural.vhdl | 87 +++++++++++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 Example/full_adder/full_adder_structural.vhdl

(limited to 'Example')

diff --git a/Example/full_adder/full_adder_structural.vhdl b/Example/full_adder/full_adder_structural.vhdl
new file mode 100644
index 0000000..eb06a3d
--- /dev/null
+++ b/Example/full_adder/full_adder_structural.vhdl
@@ -0,0 +1,87 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity full_adder_structural is
+port(a: in std_logic;
+	 b: in std_logic;
+     cin: in std_logic;
+     sum: out std_logic;
+     carry: out std_logic);
+end full_adder_structural;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity andgate is
+port(a: in std_logic;
+     b: in std_logic;
+     z: out std_logic);
+end andgate;
+
+architecture e1 of andgate is
+begin
+z <= a and b;
+end e1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xorgate is
+port(a: in std_logic;
+     b: in std_logic;
+     z: out std_logic);
+end xorgate;
+
+architecture e2 of xorgate is
+begin
+z <= a xor b;
+end e2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity orgate is
+port(a: in std_logic;
+     b: in std_logic;
+     z: out std_logic);
+end orgate;
+
+architecture e3 of orgate is
+begin
+z <= a or b;
+end e3;
+
+
+
+architecture structural of full_adder_structural is
+
+component andgate
+port(a: in std_logic;
+     b: in std_logic;
+     z: out std_logic);
+end component;
+
+component xorgate
+port(a: in std_logic;
+	 b: in std_logic;
+     z: out std_logic);
+end component;
+
+component orgate
+port(a: in std_logic;
+	 b: in std_logic;
+     z: out std_logic);
+end component;
+
+signal c1,c2,c3: std_logic;
+
+begin
+
+u1 : xorgate port map(a,b,c1);
+u2 : xorgate port map(c1,cin,sum);
+u3 : andgate port map(c1,cin,c2);
+u4 : andgate port map(a,b,c3);
+u5 : orgate port map(c2,c3,carry);
+
+
+end structural;
\ No newline at end of file
-- 
cgit 


From f8d3dbc8c0f1c59a0546998cb9365e5c291dca07 Mon Sep 17 00:00:00 2001
From: fossee
Date: Tue, 3 Sep 2019 11:07:32 +0530
Subject: added examples and modified server

---
 Example/2-bit-inverter/inverter.vhdl         |   6 +-
 Example/bin_to_gray/bin_to_gray.vhdl         |  21 +++++++
 Example/counter/counter.o                    | Bin 0 -> 7512 bytes
 Example/counter/counter.vhdl                 |  22 +++++++
 Example/counter/work-obj93.cf                |   4 ++
 Example/decoder/decoder.vhdl                 |  50 ++++++++++++++++
 Example/esim_trial_xor/esim_trial_xor.vhdl   |  15 +++++
 Example/fa_SL/full_adder_sl.vhdl             |  19 ++++++
 Example/fa_SL_SLV/full_adder_sl_slv.vhdl     |  19 ++++++
 Example/nghdl_half_adder/nghdl_ha.vhdl       |  22 +++++++
 Example/struct_fa/full_adder_structural.vhdl |  85 +++++++++++++++++++++++++++
 Example/trial_demux/t_demux.vhdl             |  32 ++++++++++
 Example/trial_fa/trial_fa.vhdl               |  19 ++++++
 13 files changed, 311 insertions(+), 3 deletions(-)
 create mode 100644 Example/bin_to_gray/bin_to_gray.vhdl
 create mode 100644 Example/counter/counter.o
 create mode 100644 Example/counter/counter.vhdl
 create mode 100644 Example/counter/work-obj93.cf
 create mode 100644 Example/decoder/decoder.vhdl
 create mode 100644 Example/esim_trial_xor/esim_trial_xor.vhdl
 create mode 100644 Example/fa_SL/full_adder_sl.vhdl
 create mode 100644 Example/fa_SL_SLV/full_adder_sl_slv.vhdl
 create mode 100644 Example/nghdl_half_adder/nghdl_ha.vhdl
 create mode 100644 Example/struct_fa/full_adder_structural.vhdl
 create mode 100644 Example/trial_demux/t_demux.vhdl
 create mode 100644 Example/trial_fa/trial_fa.vhdl

(limited to 'Example')

diff --git a/Example/2-bit-inverter/inverter.vhdl b/Example/2-bit-inverter/inverter.vhdl
index 9d65b8d..7eb3c67 100644
--- a/Example/2-bit-inverter/inverter.vhdl
+++ b/Example/2-bit-inverter/inverter.vhdl
@@ -2,13 +2,13 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 entity inverter is
-    port ( i: in std_logic_vector(1 downto 0);
-           o: out std_logic_vector(1 downto 0));
+    port ( i: in std_logic_vector(0 downto 0);
+           o: out std_logic_vector(0 downto 0));
 end inverter;
 
 architecture inverter_beh of inverter is
 begin
     o <= not i;
-end architecture;
+end inverter_beh;
 
 
diff --git a/Example/bin_to_gray/bin_to_gray.vhdl b/Example/bin_to_gray/bin_to_gray.vhdl
new file mode 100644
index 0000000..542f7ec
--- /dev/null
+++ b/Example/bin_to_gray/bin_to_gray.vhdl
@@ -0,0 +1,21 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+entity bin_to_gray is
+port(   
+		bin : in std_logic_vector(3 downto 0);  -- binary input
+        G   : out std_logic_vector(3 downto 0)  -- gray code output
+    );
+end bin_to_gray;
+
+
+architecture gate_level of bin_to_gray is 
+
+begin
+
+G(3) <= bin(3);
+G(2) <= bin(3) xor bin(2);
+G(1) <= bin(2) xor bin(1);
+G(0) <= bin(1) xor bin(0);
+
+end gate_level;
\ No newline at end of file
diff --git a/Example/counter/counter.o b/Example/counter/counter.o
new file mode 100644
index 0000000..442cc73
Binary files /dev/null and b/Example/counter/counter.o differ
diff --git a/Example/counter/counter.vhdl b/Example/counter/counter.vhdl
new file mode 100644
index 0000000..6e16138
--- /dev/null
+++ b/Example/counter/counter.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter is
+port(C : in std_logic;
+     CLR : in std_logic;
+     Q : out std_logic_vector(3 downto 0));
+end counter;
+architecture bhv of counter is
+signal tmp: std_logic_vector(3 downto 0);
+begin
+process (C, CLR)
+begin
+if (CLR='1') then
+tmp <= "0000";
+elsif (C'event and C='1') then
+tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length));
+end if;
+end process;
+Q <= tmp;
+end bhv;
\ No newline at end of file
diff --git a/Example/counter/work-obj93.cf b/Example/counter/work-obj93.cf
new file mode 100644
index 0000000..46d4772
--- /dev/null
+++ b/Example/counter/work-obj93.cf
@@ -0,0 +1,4 @@
+v 4
+file . "counter.vhdl" "849ecbdf1a2a5f5cd553b9ca6594e4a3ae1e214a" "20190710170933.911":
+  entity counter at 1( 0) + 0 on 13;
+  architecture bhv of counter at 11( 229) + 0 on 14;
diff --git a/Example/decoder/decoder.vhdl b/Example/decoder/decoder.vhdl
new file mode 100644
index 0000000..e429ec9
--- /dev/null
+++ b/Example/decoder/decoder.vhdl
@@ -0,0 +1,50 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity decoder is 
+port (
+		p : in std_logic_vector(4 downto 0);
+      	d : out std_logic_vector(31 downto 0)
+     );
+end decoder;
+
+architecture behav of decoder is
+
+begin
+
+with p select
+d<="00000000000000000000000000000001" when "00000",
+"00000000000000000000000000000010" when "00001",
+"00000000000000000000000000000100" when "00010",
+"00000000000000000000000000001000" when "00011",
+"00000000000000000000000000010000" when "00100",
+"00000000000000000000000000100000" when "00101",
+"00000000000000000000000001000000" when "00110",
+"00000000000000000000000010000000" when "00111",
+"00000000000000000000000100000000" when "01000",
+"00000000000000000000001000000000" when "01001",
+"00000000000000000000010000000000" when "01010",
+"00000000000000000000100000000000" when "01011",
+"00000000000000000001000000000000" when "01100",
+"00000000000000000010000000000000" when "01101",
+"00000000000000000100000000000000" when "01110",
+"00000000000000001000000000000000" when "01111",
+"00000000000000010000000000000000" when "10000",
+"00000000000000100000000000000000" when "10001",
+"00000000000001000000000000000000" when "10010",
+"00000000000010000000000000000000" when "10011",
+"00000000000100000000000000000000" when "10100",
+"00000000001000000000000000000000" when "10101",
+"00000000010000000000000000000000" when "10110",
+"00000000100000000000000000000000" when "10111",
+"00000001000000000000000000000000" when "11000",
+"00000010000000000000000000000000" when "11001",
+"00000100000000000000000000000000" when "11010",
+"00001000000000000000000000000000" when "11011",
+"00010000000000000000000000000000" when "11100",
+"00100000000000000000000000000000" when "11101",
+"01000000000000000000000000000000" when "11110",
+"10000000000000000000000000000000" when "11111",
+"00000000000000000000000000000000" when others;
+
+end behav;
diff --git a/Example/esim_trial_xor/esim_trial_xor.vhdl b/Example/esim_trial_xor/esim_trial_xor.vhdl
new file mode 100644
index 0000000..ff9190c
--- /dev/null
+++ b/Example/esim_trial_xor/esim_trial_xor.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity esim_trial_xor is
+       port (a : in  std_logic_vector(0 downto 0); 
+             b : in  std_logic_vector(0 downto 0);
+             c : out std_logic_vector(0 downto 0)); 
+     end esim_trial_xor;
+     
+     architecture rtl of esim_trial_xor is
+     begin
+        
+        c <= a xor b;
+        
+     end rtl;
diff --git a/Example/fa_SL/full_adder_sl.vhdl b/Example/fa_SL/full_adder_sl.vhdl
new file mode 100644
index 0000000..e830563
--- /dev/null
+++ b/Example/fa_SL/full_adder_sl.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_sl is
+  port (
+    i_bit1  : in std_logic;
+    i_bit2  : in std_logic;
+    i_bit3  : in std_logic;
+    o_sum   : out std_logic;
+    o_carry : out std_logic
+    );
+end full_adder_sl;
+ 
+architecture rtl of full_adder_sl is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
\ No newline at end of file
diff --git a/Example/fa_SL_SLV/full_adder_sl_slv.vhdl b/Example/fa_SL_SLV/full_adder_sl_slv.vhdl
new file mode 100644
index 0000000..7de9c1b
--- /dev/null
+++ b/Example/fa_SL_SLV/full_adder_sl_slv.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_sl_slv is
+  port (
+    i_bit1  : in std_logic;
+    i_bit2  : in std_logic;
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic;
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end full_adder_sl_slv;
+ 
+architecture rtl of full_adder_sl_slv is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3(0);
+  o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1);
+end rtl;
\ No newline at end of file
diff --git a/Example/nghdl_half_adder/nghdl_ha.vhdl b/Example/nghdl_half_adder/nghdl_ha.vhdl
new file mode 100644
index 0000000..f9f2e92
--- /dev/null
+++ b/Example/nghdl_half_adder/nghdl_ha.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity nghdl_ha is
+port (
+    	i_bit1  : in std_logic_vector(0 downto 0);
+	    i_bit2  : in std_logic_vector(0 downto 0);
+    	o_sum   : out std_logic_vector(0 downto 0);
+    	o_carry : out std_logic_vector(0 downto 0)
+    );
+end nghdl_ha;
+ 
+
+architecture rtl of nghdl_ha is
+
+begin
+ 
+  o_sum   <= i_bit1 xor i_bit2;
+  o_carry <= i_bit1 and i_bit2;
+
+end rtl;
\ No newline at end of file
diff --git a/Example/struct_fa/full_adder_structural.vhdl b/Example/struct_fa/full_adder_structural.vhdl
new file mode 100644
index 0000000..91b2762
--- /dev/null
+++ b/Example/struct_fa/full_adder_structural.vhdl
@@ -0,0 +1,85 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity full_adder_structural is
+port(a: in std_logic;
+	b: in std_logic;
+     cin: in std_logic;
+     sum: out std_logic;
+     carry: out std_logic);
+end full_adder_structural;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity andgate is
+port(a: in std_logic;
+     b: in std_logic;
+     z: out std_logic);
+end andgate;
+
+architecture e1 of andgate is
+begin
+z <= a and b;
+end e1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xorgate is
+port(a: in std_logic;
+     b: in std_logic;
+     z: out std_logic);
+end xorgate;
+
+architecture e2 of xorgate is
+begin
+z <= a xor b;
+end e2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity orgate is
+port(a: in std_logic;
+     b: in std_logic;
+     z: out std_logic);
+end orgate;
+
+architecture e3 of orgate is
+begin
+z <= a or b;
+end e3;
+
+
+architecture structural of full_adder_structural is
+
+component andgate
+port(a: in std_logic;
+     b: in std_logic;
+     z: out std_logic);
+end component;
+
+component xorgate
+port(a: in std_logic;
+	 b: in std_logic;
+     z: out std_logic);
+end component;
+
+component orgate
+port(a: in std_logic;
+	 b: in std_logic;
+     z: out std_logic);
+end component;
+
+signal c1,c2,c3: std_logic;
+
+begin
+
+u1 : xorgate port map(a,b,c1);
+u2 : xorgate port map(c1,cin,sum);
+u3 : andgate port map(c1,cin,c2);
+u4 : andgate port map(a,b,c3);
+u5 : orgate port map(c2,c3,carry);
+
+end structural;
\ No newline at end of file
diff --git a/Example/trial_demux/t_demux.vhdl b/Example/trial_demux/t_demux.vhdl
new file mode 100644
index 0000000..1e1f0bd
--- /dev/null
+++ b/Example/trial_demux/t_demux.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity t_demux is
+ port(
+
+ F : in STD_LOGIC_vector(0 downto 0);
+ S0: in STD_LOGIC_vector(0 downto 0);
+ S1: in STD_LOGIC_vector(0 downto 0);
+ A: out STD_LOGIC_vector(0 downto 0);
+ B: out STD_LOGIC_vector(0 downto 0);
+ C: out STD_LOGIC_vector(0 downto 0);
+ D: out STD_LOGIC_vector(0 downto 0)
+ );
+end t_demux;
+
+architecture bhv of t_demux is
+begin
+process (F,S0,S1) is
+begin
+ if (S0 ="0" and S1 = "0") then
+ A <= F;
+ elsif (S0 ="1" and S1 = "0") then
+ B <= F;
+ elsif (S0 ="0" and S1 = "1") then
+ C <= F;
+ else
+ D <= F;
+ end if;
+
+end process;
+end bhv;
\ No newline at end of file
diff --git a/Example/trial_fa/trial_fa.vhdl b/Example/trial_fa/trial_fa.vhdl
new file mode 100644
index 0000000..6357aa2
--- /dev/null
+++ b/Example/trial_fa/trial_fa.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity trial_fa is
+  port (
+    i_bit1  : in std_logic_vector(0 downto 0);
+    i_bit2  : in std_logic_vector(0 downto 0);
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end trial_fa;
+ 
+architecture rtl of trial_fa is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
\ No newline at end of file
-- 
cgit 


From da90fa60b3ffa57a7a37bffeb821d8d93cb00dd7 Mon Sep 17 00:00:00 2001
From: rahul
Date: Tue, 15 Oct 2019 16:05:40 +0530
Subject: Support for Ngspice-31

---
 Example/counter/counter.o     | Bin 7512 -> 0 bytes
 Example/counter/counter.vhdl  |  30 +++++++++++++++++++-----------
 Example/counter/work-obj93.cf |   4 ----
 3 files changed, 19 insertions(+), 15 deletions(-)
 delete mode 100644 Example/counter/counter.o
 delete mode 100644 Example/counter/work-obj93.cf

(limited to 'Example')

diff --git a/Example/counter/counter.o b/Example/counter/counter.o
deleted file mode 100644
index 442cc73..0000000
Binary files a/Example/counter/counter.o and /dev/null differ
diff --git a/Example/counter/counter.vhdl b/Example/counter/counter.vhdl
index 6e16138..ba14df8 100644
--- a/Example/counter/counter.vhdl
+++ b/Example/counter/counter.vhdl
@@ -1,4 +1,5 @@
 library ieee;
+
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
@@ -7,16 +8,23 @@ port(C : in std_logic;
      CLR : in std_logic;
      Q : out std_logic_vector(3 downto 0));
 end counter;
+
 architecture bhv of counter is
-signal tmp: std_logic_vector(3 downto 0);
-begin
-process (C, CLR)
-begin
-if (CLR='1') then
-tmp <= "0000";
-elsif (C'event and C='1') then
-tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length));
-end if;
-end process;
-Q <= tmp;
+
+	signal tmp: std_logic_vector(3 downto 0);
+	begin
+	process (C, CLR)
+
+		begin
+			if (CLR='1') then
+			tmp <= "0000";
+
+			elsif (C'event and C='1') then
+			tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length));
+
+			end if;
+
+	end process;
+	Q <= tmp;
+
 end bhv;
\ No newline at end of file
diff --git a/Example/counter/work-obj93.cf b/Example/counter/work-obj93.cf
deleted file mode 100644
index 46d4772..0000000
--- a/Example/counter/work-obj93.cf
+++ /dev/null
@@ -1,4 +0,0 @@
-v 4
-file . "counter.vhdl" "849ecbdf1a2a5f5cd553b9ca6594e4a3ae1e214a" "20190710170933.911":
-  entity counter at 1( 0) + 0 on 13;
-  architecture bhv of counter at 11( 229) + 0 on 14;
-- 
cgit 


From 76241122c16990ee003df89391c85ee478ea0dca Mon Sep 17 00:00:00 2001
From: rahul
Date: Tue, 22 Oct 2019 11:27:47 +0530
Subject: Examples

---
 Example/2-bit-inverter/2-bit-inverter.cir    | 36 ------------
 Example/2-bit-inverter/inverter.vhdl         | 14 -----
 Example/bin_to_gray/bin_to_gray.vhdl         |  4 +-
 Example/counter/updown_counter.vhdl          | 32 +++++++++++
 Example/demux/demux.vhdl                     | 32 -----------
 Example/fa_SL/full_adder_sl.vhdl             | 19 -------
 Example/fa_SL_SLV/full_adder_sl_slv.vhdl     | 19 -------
 Example/logic_gates/inverter_gate.vhdl       | 14 +++++
 Example/logic_gates/xor_gate.vhdl            | 13 +++++
 Example/mux-demux/demux.vhdl                 | 32 +++++++++++
 Example/mux-demux/mux.vhdl                   | 30 ++++++++++
 Example/nghdl_half_adder/nghdl_ha.vhdl       | 22 -------
 Example/struct_fa/full_adder_structural.vhdl | 85 ----------------------------
 Example/trial_demux/t_demux.vhdl             | 32 -----------
 Example/trial_fa/trial_fa.vhdl               | 19 -------
 Example/xor/myxor.vhdl                       | 15 -----
 Example/xor/xor-test.cir                     | 45 ---------------
 17 files changed, 123 insertions(+), 340 deletions(-)
 delete mode 100644 Example/2-bit-inverter/2-bit-inverter.cir
 delete mode 100644 Example/2-bit-inverter/inverter.vhdl
 create mode 100644 Example/counter/updown_counter.vhdl
 delete mode 100644 Example/demux/demux.vhdl
 delete mode 100644 Example/fa_SL/full_adder_sl.vhdl
 delete mode 100644 Example/fa_SL_SLV/full_adder_sl_slv.vhdl
 create mode 100644 Example/logic_gates/inverter_gate.vhdl
 create mode 100644 Example/logic_gates/xor_gate.vhdl
 create mode 100644 Example/mux-demux/demux.vhdl
 create mode 100644 Example/mux-demux/mux.vhdl
 delete mode 100644 Example/nghdl_half_adder/nghdl_ha.vhdl
 delete mode 100644 Example/struct_fa/full_adder_structural.vhdl
 delete mode 100644 Example/trial_demux/t_demux.vhdl
 delete mode 100644 Example/trial_fa/trial_fa.vhdl
 delete mode 100644 Example/xor/myxor.vhdl
 delete mode 100644 Example/xor/xor-test.cir

(limited to 'Example')

diff --git a/Example/2-bit-inverter/2-bit-inverter.cir b/Example/2-bit-inverter/2-bit-inverter.cir
deleted file mode 100644
index 88580dd..0000000
--- a/Example/2-bit-inverter/2-bit-inverter.cir
+++ /dev/null
@@ -1,36 +0,0 @@
-* analysis type *
-.tran 1n 100n
-*
-* input sources *
-v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.1n 2.0 10n 0.0 10.1n 2.0 15n 2.0 15.1n 2.0 20n 0 20.1n 2.0 25n 2.0 25.1n 2.0 30n 2.0 30.1n 2.0
-               + 40n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 2.0)
-
-v2 200 0 DC PWL ( 0n 2.0 5n 2.0 5.1n 0.0 10n 0.0 10.1n 2.0 15n 2.0 15.1n 0.0 20n 0 20.1n 2.0 25n 2.0 25.1n 0.0 30n 2.0 30.1n 2.0
-               + 40n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 2.0)
-
-* resistors to ground *
-r1 100 0 1k
-r2 200 0 1k
-
-rload1 300 0 10k
-rload2 400 0 10k
-*
-* adc_bridge blocks *
-aconverter1 [100 200]  [1 2] adc_bridge1
-
-.model adc_bridge1 adc_bridge ( in_low =0.3 in_high =0.7
-+ rise_delay =1.0e-12 fall_delay =1.0e-12)
-
-ainverter [1 2] [10 20]  inv1
-
-.model inv1 inverter(instance_id = 101 rise_delay = 1.0e-12 fall_delay = 1.0e-12 stop_time=90e-9)
-
-
-aconverter2 [10 20] [30 40] dac_bridge1
-
-.model dac_bridge1 dac_bridge( out_low=0.25 out_high=5.0 
-+out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) 
-
-.end
- 
-
diff --git a/Example/2-bit-inverter/inverter.vhdl b/Example/2-bit-inverter/inverter.vhdl
deleted file mode 100644
index 7eb3c67..0000000
--- a/Example/2-bit-inverter/inverter.vhdl
+++ /dev/null
@@ -1,14 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity inverter is
-    port ( i: in std_logic_vector(0 downto 0);
-           o: out std_logic_vector(0 downto 0));
-end inverter;
-
-architecture inverter_beh of inverter is
-begin
-    o <= not i;
-end inverter_beh;
-
-
diff --git a/Example/bin_to_gray/bin_to_gray.vhdl b/Example/bin_to_gray/bin_to_gray.vhdl
index 542f7ec..d6045e8 100644
--- a/Example/bin_to_gray/bin_to_gray.vhdl
+++ b/Example/bin_to_gray/bin_to_gray.vhdl
@@ -3,8 +3,8 @@ USE ieee.std_logic_1164.ALL;
 
 entity bin_to_gray is
 port(   
-		bin : in std_logic_vector(3 downto 0);  -- binary input
-        G   : out std_logic_vector(3 downto 0)  -- gray code output
+		bin : in std_logic_vector(3 downto 0); 
+        G   : out std_logic_vector(3 downto 0)
     );
 end bin_to_gray;
 
diff --git a/Example/counter/updown_counter.vhdl b/Example/counter/updown_counter.vhdl
new file mode 100644
index 0000000..922ee67
--- /dev/null
+++ b/Example/counter/updown_counter.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+
+entity updown_counter is
+    Port ( clk: in std_logic;
+           reset: in std_logic;
+     up_down: in std_logic;
+           counter: out std_logic_vector(3 downto 0)
+     );
+end updown_counter;
+
+architecture Behavioral of updown_counter is
+signal tmp: std_logic_vector(3 downto 0);
+begin
+
+process(clk,reset)
+begin
+    if(reset='1') then
+         tmp <= "0000";
+    elsif(clk'event and clk='1') then
+         if(up_down='1') then
+           tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)-1), tmp'length));
+         else 
+           tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)+1), tmp'length));
+         end if;
+    end if;
+end process;
+ counter <= std_logic_vector(tmp);
+
+end Behavioral;
\ No newline at end of file
diff --git a/Example/demux/demux.vhdl b/Example/demux/demux.vhdl
deleted file mode 100644
index e73c196..0000000
--- a/Example/demux/demux.vhdl
+++ /dev/null
@@ -1,32 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity demux is
- port(
-
- F : in STD_LOGIC_vector(0 downto 0);
- S0: in STD_LOGIC_vector(0 downto 0);
- S1: in STD_LOGIC_vector(0 downto 0);
- A: out STD_LOGIC_vector(0 downto 0);
- B: out STD_LOGIC_vector(0 downto 0);
- C: out STD_LOGIC_vector(0 downto 0);
- D: out STD_LOGIC_vector(0 downto 0)
- );
-end demux;
-
-architecture bhv of demux is
-begin
-process (F,S0,S1) is
-begin
- if (S0 ="0" and S1 = "0") then
- A <= F;
- elsif (S0 ="1" and S1 = "0") then
- B <= F;
- elsif (S0 ="0" and S1 = "1") then
- C <= F;
- else
- D <= F;
- end if;
-
-end process;
-end bhv;
diff --git a/Example/fa_SL/full_adder_sl.vhdl b/Example/fa_SL/full_adder_sl.vhdl
deleted file mode 100644
index e830563..0000000
--- a/Example/fa_SL/full_adder_sl.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity full_adder_sl is
-  port (
-    i_bit1  : in std_logic;
-    i_bit2  : in std_logic;
-    i_bit3  : in std_logic;
-    o_sum   : out std_logic;
-    o_carry : out std_logic
-    );
-end full_adder_sl;
- 
-architecture rtl of full_adder_sl is
-begin
-  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
-  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
-end rtl;
\ No newline at end of file
diff --git a/Example/fa_SL_SLV/full_adder_sl_slv.vhdl b/Example/fa_SL_SLV/full_adder_sl_slv.vhdl
deleted file mode 100644
index 7de9c1b..0000000
--- a/Example/fa_SL_SLV/full_adder_sl_slv.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity full_adder_sl_slv is
-  port (
-    i_bit1  : in std_logic;
-    i_bit2  : in std_logic;
-    i_bit3  : in std_logic_vector(0 downto 0);
-    o_sum   : out std_logic;
-    o_carry : out std_logic_vector(0 downto 0)
-    );
-end full_adder_sl_slv;
- 
-architecture rtl of full_adder_sl_slv is
-begin
-  o_sum   <= i_bit1 xor i_bit2 xor i_bit3(0);
-  o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1);
-end rtl;
\ No newline at end of file
diff --git a/Example/logic_gates/inverter_gate.vhdl b/Example/logic_gates/inverter_gate.vhdl
new file mode 100644
index 0000000..9825917
--- /dev/null
+++ b/Example/logic_gates/inverter_gate.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity inverter_gate is
+    port ( i: in std_logic;
+           o: out std_logic);
+end inverter_gate;
+
+architecture beh of inverter_gate is
+begin
+    o <= not i;
+end beh;
+
+
diff --git a/Example/logic_gates/xor_gate.vhdl b/Example/logic_gates/xor_gate.vhdl
new file mode 100644
index 0000000..da0da23
--- /dev/null
+++ b/Example/logic_gates/xor_gate.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xor_gate is
+    port (a : in  std_logic;
+          b : in  std_logic;
+          c : out std_logic);
+end xor_gate;
+     
+architecture rtl of xor_gate is
+    begin
+		c <= a xor b;
+end rtl;
diff --git a/Example/mux-demux/demux.vhdl b/Example/mux-demux/demux.vhdl
new file mode 100644
index 0000000..e73c196
--- /dev/null
+++ b/Example/mux-demux/demux.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity demux is
+ port(
+
+ F : in STD_LOGIC_vector(0 downto 0);
+ S0: in STD_LOGIC_vector(0 downto 0);
+ S1: in STD_LOGIC_vector(0 downto 0);
+ A: out STD_LOGIC_vector(0 downto 0);
+ B: out STD_LOGIC_vector(0 downto 0);
+ C: out STD_LOGIC_vector(0 downto 0);
+ D: out STD_LOGIC_vector(0 downto 0)
+ );
+end demux;
+
+architecture bhv of demux is
+begin
+process (F,S0,S1) is
+begin
+ if (S0 ="0" and S1 = "0") then
+ A <= F;
+ elsif (S0 ="1" and S1 = "0") then
+ B <= F;
+ elsif (S0 ="0" and S1 = "1") then
+ C <= F;
+ else
+ D <= F;
+ end if;
+
+end process;
+end bhv;
diff --git a/Example/mux-demux/mux.vhdl b/Example/mux-demux/mux.vhdl
new file mode 100644
index 0000000..b72e287
--- /dev/null
+++ b/Example/mux-demux/mux.vhdl
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+ 
+entity mux is
+ port(A : in std_logic;
+      B : in std_logic;
+      C : in std_logic;
+      D : in std_logic;
+      S0 : in std_logic;
+      S1 : in std_logic;
+      Z: out std_logic);
+end mux;
+ 
+architecture bhv of mux is
+begin
+process (A,B,C,D,S0,S1) is
+begin
+  if (S0 ='0' and S1 = '0') then
+      Z <= A;
+  elsif (S0 ='0' and S1 = '1') then
+      Z <= B;
+  elsif (S0 ='1' and S1 = '0') then
+      Z <= C;
+  else
+      Z <= D;
+  end if;
+ 
+end process;
+end bhv;
+
diff --git a/Example/nghdl_half_adder/nghdl_ha.vhdl b/Example/nghdl_half_adder/nghdl_ha.vhdl
deleted file mode 100644
index f9f2e92..0000000
--- a/Example/nghdl_half_adder/nghdl_ha.vhdl
+++ /dev/null
@@ -1,22 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity nghdl_ha is
-port (
-    	i_bit1  : in std_logic_vector(0 downto 0);
-	    i_bit2  : in std_logic_vector(0 downto 0);
-    	o_sum   : out std_logic_vector(0 downto 0);
-    	o_carry : out std_logic_vector(0 downto 0)
-    );
-end nghdl_ha;
- 
-
-architecture rtl of nghdl_ha is
-
-begin
- 
-  o_sum   <= i_bit1 xor i_bit2;
-  o_carry <= i_bit1 and i_bit2;
-
-end rtl;
\ No newline at end of file
diff --git a/Example/struct_fa/full_adder_structural.vhdl b/Example/struct_fa/full_adder_structural.vhdl
deleted file mode 100644
index 91b2762..0000000
--- a/Example/struct_fa/full_adder_structural.vhdl
+++ /dev/null
@@ -1,85 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity full_adder_structural is
-port(a: in std_logic;
-	b: in std_logic;
-     cin: in std_logic;
-     sum: out std_logic;
-     carry: out std_logic);
-end full_adder_structural;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity andgate is
-port(a: in std_logic;
-     b: in std_logic;
-     z: out std_logic);
-end andgate;
-
-architecture e1 of andgate is
-begin
-z <= a and b;
-end e1;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity xorgate is
-port(a: in std_logic;
-     b: in std_logic;
-     z: out std_logic);
-end xorgate;
-
-architecture e2 of xorgate is
-begin
-z <= a xor b;
-end e2;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity orgate is
-port(a: in std_logic;
-     b: in std_logic;
-     z: out std_logic);
-end orgate;
-
-architecture e3 of orgate is
-begin
-z <= a or b;
-end e3;
-
-
-architecture structural of full_adder_structural is
-
-component andgate
-port(a: in std_logic;
-     b: in std_logic;
-     z: out std_logic);
-end component;
-
-component xorgate
-port(a: in std_logic;
-	 b: in std_logic;
-     z: out std_logic);
-end component;
-
-component orgate
-port(a: in std_logic;
-	 b: in std_logic;
-     z: out std_logic);
-end component;
-
-signal c1,c2,c3: std_logic;
-
-begin
-
-u1 : xorgate port map(a,b,c1);
-u2 : xorgate port map(c1,cin,sum);
-u3 : andgate port map(c1,cin,c2);
-u4 : andgate port map(a,b,c3);
-u5 : orgate port map(c2,c3,carry);
-
-end structural;
\ No newline at end of file
diff --git a/Example/trial_demux/t_demux.vhdl b/Example/trial_demux/t_demux.vhdl
deleted file mode 100644
index 1e1f0bd..0000000
--- a/Example/trial_demux/t_demux.vhdl
+++ /dev/null
@@ -1,32 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity t_demux is
- port(
-
- F : in STD_LOGIC_vector(0 downto 0);
- S0: in STD_LOGIC_vector(0 downto 0);
- S1: in STD_LOGIC_vector(0 downto 0);
- A: out STD_LOGIC_vector(0 downto 0);
- B: out STD_LOGIC_vector(0 downto 0);
- C: out STD_LOGIC_vector(0 downto 0);
- D: out STD_LOGIC_vector(0 downto 0)
- );
-end t_demux;
-
-architecture bhv of t_demux is
-begin
-process (F,S0,S1) is
-begin
- if (S0 ="0" and S1 = "0") then
- A <= F;
- elsif (S0 ="1" and S1 = "0") then
- B <= F;
- elsif (S0 ="0" and S1 = "1") then
- C <= F;
- else
- D <= F;
- end if;
-
-end process;
-end bhv;
\ No newline at end of file
diff --git a/Example/trial_fa/trial_fa.vhdl b/Example/trial_fa/trial_fa.vhdl
deleted file mode 100644
index 6357aa2..0000000
--- a/Example/trial_fa/trial_fa.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity trial_fa is
-  port (
-    i_bit1  : in std_logic_vector(0 downto 0);
-    i_bit2  : in std_logic_vector(0 downto 0);
-    i_bit3  : in std_logic_vector(0 downto 0);
-    o_sum   : out std_logic_vector(0 downto 0);
-    o_carry : out std_logic_vector(0 downto 0)
-    );
-end trial_fa;
- 
-architecture rtl of trial_fa is
-begin
-  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
-  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
-end rtl;
\ No newline at end of file
diff --git a/Example/xor/myxor.vhdl b/Example/xor/myxor.vhdl
deleted file mode 100644
index b49f3ca..0000000
--- a/Example/xor/myxor.vhdl
+++ /dev/null
@@ -1,15 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity myxor is
-       port (a : in  std_logic_vector(0 downto 0); 
-             b : in  std_logic_vector(0 downto 0);
-             c : out std_logic_vector(0 downto 0)); 
-     end myxor;
-     
-     architecture rtl of myxor is
-     begin
-        
-        c <= a xor b;
-        
-     end rtl;
diff --git a/Example/xor/xor-test.cir b/Example/xor/xor-test.cir
deleted file mode 100644
index 910839e..0000000
--- a/Example/xor/xor-test.cir
+++ /dev/null
@@ -1,45 +0,0 @@
-
-*** input sources ***
-
-v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.1n 2.0 10n 2.0 10.1n 2.0 15n 2.0 15.1n 0.0 20.0n 0.0 20.1n 2.0 25n 2.0 25.1n 0.0 30n 0.0 30.1n 2.0
-		+40.0 2.0 40.1n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 0.0)
-
-v2 200 0 DC PWL (0n 2.0 5n 2.0 10n 2.0 15n 2.0 15.1n 0.0 20n 0.0 25n 0.0 30n 0.0 30.1n 2.0 40n 2.0 40.1n 0.0 45n 0.0 45.1n 2.0 
-		+ 50n 2.0 50.1n 0.0 60.0n 0.0 70n 0.0 80n 0.0 90n 0.0 95n 0.0 95.1n 2.0 100n 2.0)
-
-Vvdd vdd 0 DC 2.0
-
-*** resistors to ground ***
-r1 100 0 1k
-r2 200 0 1k
-
-
-*
-*** adc_bridge blocks ***
-aconverter1 [100 200 ] [1 2] adc
-
-
-axor [1] [2]  [12] axors
-
-adac1 [12] [34]  dac
-*************model***********
-
-.model axors myxor(instance_id = 112 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
-
-.model adc adc_bridge ( in_low =0.5 in_high =1.0
-+                   rise_delay =1.0e-10 fall_delay =1.0e-10)
-.model dac dac_bridge(out_low = 0.0 out_high = 2.0 out_undef = 1.0
-+                      input_load = 5.0e-14 t_rise = 1.0e-10
-+                      t_fall = 1.0e-10)
-
-
-.end
-
-
-
-.CONTROL
-
-option noopalter
-tran .1n 100n
-.ENDC
-
-- 
cgit 


From 1782d61c433157397a21b61a30d4f478ea7eb623 Mon Sep 17 00:00:00 2001
From: rahul
Date: Thu, 24 Oct 2019 10:31:06 +0530
Subject: removed trial_xor example

---
 Example/esim_trial_xor/esim_trial_xor.vhdl | 15 ---------------
 1 file changed, 15 deletions(-)
 delete mode 100644 Example/esim_trial_xor/esim_trial_xor.vhdl

(limited to 'Example')

diff --git a/Example/esim_trial_xor/esim_trial_xor.vhdl b/Example/esim_trial_xor/esim_trial_xor.vhdl
deleted file mode 100644
index ff9190c..0000000
--- a/Example/esim_trial_xor/esim_trial_xor.vhdl
+++ /dev/null
@@ -1,15 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity esim_trial_xor is
-       port (a : in  std_logic_vector(0 downto 0); 
-             b : in  std_logic_vector(0 downto 0);
-             c : out std_logic_vector(0 downto 0)); 
-     end esim_trial_xor;
-     
-     architecture rtl of esim_trial_xor is
-     begin
-        
-        c <= a xor b;
-        
-     end rtl;
-- 
cgit