From ad36bcd34ffe111f2981936ac44cd007dbe483de Mon Sep 17 00:00:00 2001
From: fahim
Date: Thu, 5 Feb 2015 17:46:55 +0530
Subject: Subject: Added example

Description: Added two example xor and 2-bit inverter
---
 Example/xor/myxor.vhdl | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 Example/xor/myxor.vhdl

(limited to 'Example/xor/myxor.vhdl')

diff --git a/Example/xor/myxor.vhdl b/Example/xor/myxor.vhdl
new file mode 100644
index 0000000..b49f3ca
--- /dev/null
+++ b/Example/xor/myxor.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity myxor is
+       port (a : in  std_logic_vector(0 downto 0); 
+             b : in  std_logic_vector(0 downto 0);
+             c : out std_logic_vector(0 downto 0)); 
+     end myxor;
+     
+     architecture rtl of myxor is
+     begin
+        
+        c <= a xor b;
+        
+     end rtl;
-- 
cgit