From bfd56aecafe2cbc0693aaa2adf514f2270843969 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:48:12 +0530
Subject: Add files via upload

---
 Example/half_adder/trial_ha.vhdl | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Example/half_adder/trial_ha.vhdl

(limited to 'Example/half_adder')

diff --git a/Example/half_adder/trial_ha.vhdl b/Example/half_adder/trial_ha.vhdl
new file mode 100644
index 0000000..30e7938
--- /dev/null
+++ b/Example/half_adder/trial_ha.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity trial_ha is
+  port (
+    i_bit  : in std_logic_vector(1 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end trial_ha;
+ 
+architecture rtl of trial_ha is
+begin
+  o_sum   <= i_bit(0) xor i_bit(1);
+  o_carry <= i_bit(0) and i_bit(1);
+end rtl;
\ No newline at end of file
-- 
cgit