From d239a1c81f01e8a76344b9ee20ab30fc49615672 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:46:27 +0530
Subject: Create readme.md

---
 Example/half_adder/readme.md | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 Example/half_adder/readme.md

(limited to 'Example/half_adder')

diff --git a/Example/half_adder/readme.md b/Example/half_adder/readme.md
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/Example/half_adder/readme.md
@@ -0,0 +1 @@
+
-- 
cgit 


From bfd56aecafe2cbc0693aaa2adf514f2270843969 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:48:12 +0530
Subject: Add files via upload

---
 Example/half_adder/trial_ha.vhdl | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Example/half_adder/trial_ha.vhdl

(limited to 'Example/half_adder')

diff --git a/Example/half_adder/trial_ha.vhdl b/Example/half_adder/trial_ha.vhdl
new file mode 100644
index 0000000..30e7938
--- /dev/null
+++ b/Example/half_adder/trial_ha.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity trial_ha is
+  port (
+    i_bit  : in std_logic_vector(1 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end trial_ha;
+ 
+architecture rtl of trial_ha is
+begin
+  o_sum   <= i_bit(0) xor i_bit(1);
+  o_carry <= i_bit(0) and i_bit(1);
+end rtl;
\ No newline at end of file
-- 
cgit 


From b4168eaf495fdfb1d36df115f5f2d0ae74b7fbaa Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:48:47 +0530
Subject: Delete readme.md

---
 Example/half_adder/readme.md | 1 -
 1 file changed, 1 deletion(-)
 delete mode 100644 Example/half_adder/readme.md

(limited to 'Example/half_adder')

diff --git a/Example/half_adder/readme.md b/Example/half_adder/readme.md
deleted file mode 100644
index 8b13789..0000000
--- a/Example/half_adder/readme.md
+++ /dev/null
@@ -1 +0,0 @@
-
-- 
cgit 


From e3076fbf6c6eb5f1aab8eef8ceaa3870ec1ea6a9 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Tue, 25 Jun 2019 09:50:26 +0530
Subject: Update and rename trial_ha.vhdl to half_adder.vhdl

---
 Example/half_adder/half_adder.vhdl | 18 ++++++++++++++++++
 Example/half_adder/trial_ha.vhdl   | 17 -----------------
 2 files changed, 18 insertions(+), 17 deletions(-)
 create mode 100644 Example/half_adder/half_adder.vhdl
 delete mode 100644 Example/half_adder/trial_ha.vhdl

(limited to 'Example/half_adder')

diff --git a/Example/half_adder/half_adder.vhdl b/Example/half_adder/half_adder.vhdl
new file mode 100644
index 0000000..71ef1cc
--- /dev/null
+++ b/Example/half_adder/half_adder.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity half_adder is
+  port (
+    i_bit0  : in std_logic_vector(0 downto 0);
+    i_bit1  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end half_adder;
+ 
+architecture rtl of half_adder is
+begin
+  o_sum   <= i_bit0 xor i_bit1;
+  o_carry <= i_bit0 and i_bit1;
+end rtl;
diff --git a/Example/half_adder/trial_ha.vhdl b/Example/half_adder/trial_ha.vhdl
deleted file mode 100644
index 30e7938..0000000
--- a/Example/half_adder/trial_ha.vhdl
+++ /dev/null
@@ -1,17 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity trial_ha is
-  port (
-    i_bit  : in std_logic_vector(1 downto 0);
-    o_sum   : out std_logic_vector(0 downto 0);
-    o_carry : out std_logic_vector(0 downto 0)
-    );
-end trial_ha;
- 
-architecture rtl of trial_ha is
-begin
-  o_sum   <= i_bit(0) xor i_bit(1);
-  o_carry <= i_bit(0) and i_bit(1);
-end rtl;
\ No newline at end of file
-- 
cgit