From c3ef8e2a074372ddb0fe4686b51f446117b0fd29 Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Tue, 25 Jun 2019 09:46:49 +0530 Subject: Create readme.md --- Example/full_adder/readme.md | 1 + 1 file changed, 1 insertion(+) create mode 100644 Example/full_adder/readme.md (limited to 'Example/full_adder') diff --git a/Example/full_adder/readme.md b/Example/full_adder/readme.md new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Example/full_adder/readme.md @@ -0,0 +1 @@ + -- cgit From 3bc50a214b4dbac28cbe980f631ec9ac4c6735fc Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Tue, 25 Jun 2019 09:47:45 +0530 Subject: Add files via upload --- Example/full_adder/trial_ha.vhdl | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Example/full_adder/trial_ha.vhdl (limited to 'Example/full_adder') diff --git a/Example/full_adder/trial_ha.vhdl b/Example/full_adder/trial_ha.vhdl new file mode 100644 index 0000000..30e7938 --- /dev/null +++ b/Example/full_adder/trial_ha.vhdl @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity trial_ha is + port ( + i_bit : in std_logic_vector(1 downto 0); + o_sum : out std_logic_vector(0 downto 0); + o_carry : out std_logic_vector(0 downto 0) + ); +end trial_ha; + +architecture rtl of trial_ha is +begin + o_sum <= i_bit(0) xor i_bit(1); + o_carry <= i_bit(0) and i_bit(1); +end rtl; \ No newline at end of file -- cgit From 9300750cc60402eb73595173af696cea6345b9ca Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Tue, 25 Jun 2019 09:50:46 +0530 Subject: Delete readme.md --- Example/full_adder/readme.md | 1 - 1 file changed, 1 deletion(-) delete mode 100644 Example/full_adder/readme.md (limited to 'Example/full_adder') diff --git a/Example/full_adder/readme.md b/Example/full_adder/readme.md deleted file mode 100644 index 8b13789..0000000 --- a/Example/full_adder/readme.md +++ /dev/null @@ -1 +0,0 @@ - -- cgit From aa538a95b5ff747ad9fa3455ac2a6c88dcb0becb Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Tue, 25 Jun 2019 09:51:11 +0530 Subject: Add files via upload --- Example/full_adder/trial_fa.vhdl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Example/full_adder/trial_fa.vhdl (limited to 'Example/full_adder') diff --git a/Example/full_adder/trial_fa.vhdl b/Example/full_adder/trial_fa.vhdl new file mode 100644 index 0000000..6357aa2 --- /dev/null +++ b/Example/full_adder/trial_fa.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity trial_fa is + port ( + i_bit1 : in std_logic_vector(0 downto 0); + i_bit2 : in std_logic_vector(0 downto 0); + i_bit3 : in std_logic_vector(0 downto 0); + o_sum : out std_logic_vector(0 downto 0); + o_carry : out std_logic_vector(0 downto 0) + ); +end trial_fa; + +architecture rtl of trial_fa is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3; + o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); +end rtl; \ No newline at end of file -- cgit From 26543fb77ba71c77292547f64b24d1fb0658ec72 Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Tue, 25 Jun 2019 09:51:28 +0530 Subject: Delete trial_ha.vhdl --- Example/full_adder/trial_ha.vhdl | 17 ----------------- 1 file changed, 17 deletions(-) delete mode 100644 Example/full_adder/trial_ha.vhdl (limited to 'Example/full_adder') diff --git a/Example/full_adder/trial_ha.vhdl b/Example/full_adder/trial_ha.vhdl deleted file mode 100644 index 30e7938..0000000 --- a/Example/full_adder/trial_ha.vhdl +++ /dev/null @@ -1,17 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity trial_ha is - port ( - i_bit : in std_logic_vector(1 downto 0); - o_sum : out std_logic_vector(0 downto 0); - o_carry : out std_logic_vector(0 downto 0) - ); -end trial_ha; - -architecture rtl of trial_ha is -begin - o_sum <= i_bit(0) xor i_bit(1); - o_carry <= i_bit(0) and i_bit(1); -end rtl; \ No newline at end of file -- cgit From a81c4ecb38dc18f36688113c6fa1b28a84802183 Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Tue, 25 Jun 2019 09:52:11 +0530 Subject: Update and rename trial_fa.vhdl to full_adder.vhdl --- Example/full_adder/full_adder.vhdl | 19 +++++++++++++++++++ Example/full_adder/trial_fa.vhdl | 19 ------------------- 2 files changed, 19 insertions(+), 19 deletions(-) create mode 100644 Example/full_adder/full_adder.vhdl delete mode 100644 Example/full_adder/trial_fa.vhdl (limited to 'Example/full_adder') diff --git a/Example/full_adder/full_adder.vhdl b/Example/full_adder/full_adder.vhdl new file mode 100644 index 0000000..745fac3 --- /dev/null +++ b/Example/full_adder/full_adder.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity full_adder is + port ( + i_bit1 : in std_logic_vector(0 downto 0); + i_bit2 : in std_logic_vector(0 downto 0); + i_bit3 : in std_logic_vector(0 downto 0); + o_sum : out std_logic_vector(0 downto 0); + o_carry : out std_logic_vector(0 downto 0) + ); +end full_adder; + +architecture rtl of full_adder is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3; + o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); +end rtl; diff --git a/Example/full_adder/trial_fa.vhdl b/Example/full_adder/trial_fa.vhdl deleted file mode 100644 index 6357aa2..0000000 --- a/Example/full_adder/trial_fa.vhdl +++ /dev/null @@ -1,19 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity trial_fa is - port ( - i_bit1 : in std_logic_vector(0 downto 0); - i_bit2 : in std_logic_vector(0 downto 0); - i_bit3 : in std_logic_vector(0 downto 0); - o_sum : out std_logic_vector(0 downto 0); - o_carry : out std_logic_vector(0 downto 0) - ); -end trial_fa; - -architecture rtl of trial_fa is -begin - o_sum <= i_bit1 xor i_bit2 xor i_bit3; - o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); -end rtl; \ No newline at end of file -- cgit From a6394b20adf8176755d6f16e86550a8ffb14b5a7 Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Sun, 7 Jul 2019 18:39:16 +0530 Subject: Update and rename full_adder.vhdl to full_adder_slv.vhdl --- Example/full_adder/full_adder.vhdl | 19 ------------------- Example/full_adder/full_adder_slv.vhdl | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 19 deletions(-) delete mode 100644 Example/full_adder/full_adder.vhdl create mode 100644 Example/full_adder/full_adder_slv.vhdl (limited to 'Example/full_adder') diff --git a/Example/full_adder/full_adder.vhdl b/Example/full_adder/full_adder.vhdl deleted file mode 100644 index 745fac3..0000000 --- a/Example/full_adder/full_adder.vhdl +++ /dev/null @@ -1,19 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity full_adder is - port ( - i_bit1 : in std_logic_vector(0 downto 0); - i_bit2 : in std_logic_vector(0 downto 0); - i_bit3 : in std_logic_vector(0 downto 0); - o_sum : out std_logic_vector(0 downto 0); - o_carry : out std_logic_vector(0 downto 0) - ); -end full_adder; - -architecture rtl of full_adder is -begin - o_sum <= i_bit1 xor i_bit2 xor i_bit3; - o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); -end rtl; diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/full_adder/full_adder_slv.vhdl new file mode 100644 index 0000000..a0495f0 --- /dev/null +++ b/Example/full_adder/full_adder_slv.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity full_adder_slv is + port ( + i_bit1 : in std_logic_vector(0 downto 0); + i_bit2 : in std_logic_vector(0 downto 0); + i_bit3 : in std_logic_vector(0 downto 0); + o_sum : out std_logic_vector(0 downto 0); + o_carry : out std_logic_vector(0 downto 0) + ); +end full_adder_slv; + +architecture rtl of full_adder_slv is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3; + o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); +end rtl; -- cgit From 7193220d6958627f268aec77efb9f6baf6ee4a9c Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Sun, 7 Jul 2019 18:47:08 +0530 Subject: std_logic with std_logic_vector --- Example/full_adder/full_adder_sl_slv.vhdl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Example/full_adder/full_adder_sl_slv.vhdl (limited to 'Example/full_adder') diff --git a/Example/full_adder/full_adder_sl_slv.vhdl b/Example/full_adder/full_adder_sl_slv.vhdl new file mode 100644 index 0000000..7de9c1b --- /dev/null +++ b/Example/full_adder/full_adder_sl_slv.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity full_adder_sl_slv is + port ( + i_bit1 : in std_logic; + i_bit2 : in std_logic; + i_bit3 : in std_logic_vector(0 downto 0); + o_sum : out std_logic; + o_carry : out std_logic_vector(0 downto 0) + ); +end full_adder_sl_slv; + +architecture rtl of full_adder_sl_slv is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3(0); + o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1); +end rtl; \ No newline at end of file -- cgit From 45f2669e5ba6760c6adaacb564c0799d54a11052 Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Sun, 7 Jul 2019 18:48:17 +0530 Subject: std_logic_vector --- Example/full_adder/full_adder_sl.vhdl | 19 +++++++++++++++++++ Example/full_adder/full_adder_slv.vhdl | 19 ------------------- 2 files changed, 19 insertions(+), 19 deletions(-) create mode 100644 Example/full_adder/full_adder_sl.vhdl delete mode 100644 Example/full_adder/full_adder_slv.vhdl (limited to 'Example/full_adder') diff --git a/Example/full_adder/full_adder_sl.vhdl b/Example/full_adder/full_adder_sl.vhdl new file mode 100644 index 0000000..a0495f0 --- /dev/null +++ b/Example/full_adder/full_adder_sl.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity full_adder_slv is + port ( + i_bit1 : in std_logic_vector(0 downto 0); + i_bit2 : in std_logic_vector(0 downto 0); + i_bit3 : in std_logic_vector(0 downto 0); + o_sum : out std_logic_vector(0 downto 0); + o_carry : out std_logic_vector(0 downto 0) + ); +end full_adder_slv; + +architecture rtl of full_adder_slv is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3; + o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); +end rtl; diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/full_adder/full_adder_slv.vhdl deleted file mode 100644 index a0495f0..0000000 --- a/Example/full_adder/full_adder_slv.vhdl +++ /dev/null @@ -1,19 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity full_adder_slv is - port ( - i_bit1 : in std_logic_vector(0 downto 0); - i_bit2 : in std_logic_vector(0 downto 0); - i_bit3 : in std_logic_vector(0 downto 0); - o_sum : out std_logic_vector(0 downto 0); - o_carry : out std_logic_vector(0 downto 0) - ); -end full_adder_slv; - -architecture rtl of full_adder_slv is -begin - o_sum <= i_bit1 xor i_bit2 xor i_bit3; - o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); -end rtl; -- cgit From 385d1b79fa4d4a4c9fe39f72cd87d53b247704d4 Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Sun, 7 Jul 2019 18:48:39 +0530 Subject: std_logic_vector --- Example/full_adder/full_adder_sl.vhdl | 19 ------------------- Example/full_adder/full_adder_slv.vhdl | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 19 deletions(-) delete mode 100644 Example/full_adder/full_adder_sl.vhdl create mode 100644 Example/full_adder/full_adder_slv.vhdl (limited to 'Example/full_adder') diff --git a/Example/full_adder/full_adder_sl.vhdl b/Example/full_adder/full_adder_sl.vhdl deleted file mode 100644 index a0495f0..0000000 --- a/Example/full_adder/full_adder_sl.vhdl +++ /dev/null @@ -1,19 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity full_adder_slv is - port ( - i_bit1 : in std_logic_vector(0 downto 0); - i_bit2 : in std_logic_vector(0 downto 0); - i_bit3 : in std_logic_vector(0 downto 0); - o_sum : out std_logic_vector(0 downto 0); - o_carry : out std_logic_vector(0 downto 0) - ); -end full_adder_slv; - -architecture rtl of full_adder_slv is -begin - o_sum <= i_bit1 xor i_bit2 xor i_bit3; - o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); -end rtl; diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/full_adder/full_adder_slv.vhdl new file mode 100644 index 0000000..a0495f0 --- /dev/null +++ b/Example/full_adder/full_adder_slv.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity full_adder_slv is + port ( + i_bit1 : in std_logic_vector(0 downto 0); + i_bit2 : in std_logic_vector(0 downto 0); + i_bit3 : in std_logic_vector(0 downto 0); + o_sum : out std_logic_vector(0 downto 0); + o_carry : out std_logic_vector(0 downto 0) + ); +end full_adder_slv; + +architecture rtl of full_adder_slv is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3; + o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); +end rtl; -- cgit From 0f8995a96904608b5e7a596d30547225f92e83be Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Sun, 7 Jul 2019 18:51:12 +0530 Subject: std_logic --- Example/full_adder/full_adder_sl.vhdl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Example/full_adder/full_adder_sl.vhdl (limited to 'Example/full_adder') diff --git a/Example/full_adder/full_adder_sl.vhdl b/Example/full_adder/full_adder_sl.vhdl new file mode 100644 index 0000000..e830563 --- /dev/null +++ b/Example/full_adder/full_adder_sl.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity full_adder_sl is + port ( + i_bit1 : in std_logic; + i_bit2 : in std_logic; + i_bit3 : in std_logic; + o_sum : out std_logic; + o_carry : out std_logic + ); +end full_adder_sl; + +architecture rtl of full_adder_sl is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3; + o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); +end rtl; \ No newline at end of file -- cgit From a9586e8be49a37bbf4bd20580ab6ad4763544c12 Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Wed, 10 Jul 2019 21:51:10 +0530 Subject: structural style --- Example/full_adder/full_adder_structural.vhdl | 87 +++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Example/full_adder/full_adder_structural.vhdl (limited to 'Example/full_adder') diff --git a/Example/full_adder/full_adder_structural.vhdl b/Example/full_adder/full_adder_structural.vhdl new file mode 100644 index 0000000..eb06a3d --- /dev/null +++ b/Example/full_adder/full_adder_structural.vhdl @@ -0,0 +1,87 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity full_adder_structural is +port(a: in std_logic; + b: in std_logic; + cin: in std_logic; + sum: out std_logic; + carry: out std_logic); +end full_adder_structural; + +library ieee; +use ieee.std_logic_1164.all; + +entity andgate is +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end andgate; + +architecture e1 of andgate is +begin +z <= a and b; +end e1; + +library ieee; +use ieee.std_logic_1164.all; + +entity xorgate is +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end xorgate; + +architecture e2 of xorgate is +begin +z <= a xor b; +end e2; + +library ieee; +use ieee.std_logic_1164.all; + +entity orgate is +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end orgate; + +architecture e3 of orgate is +begin +z <= a or b; +end e3; + + + +architecture structural of full_adder_structural is + +component andgate +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end component; + +component xorgate +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end component; + +component orgate +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end component; + +signal c1,c2,c3: std_logic; + +begin + +u1 : xorgate port map(a,b,c1); +u2 : xorgate port map(c1,cin,sum); +u3 : andgate port map(c1,cin,c2); +u4 : andgate port map(a,b,c3); +u5 : orgate port map(c2,c3,carry); + + +end structural; \ No newline at end of file -- cgit