From a6394b20adf8176755d6f16e86550a8ffb14b5a7 Mon Sep 17 00:00:00 2001 From: Rahul Paknikar Date: Sun, 7 Jul 2019 18:39:16 +0530 Subject: Update and rename full_adder.vhdl to full_adder_slv.vhdl --- Example/full_adder/full_adder.vhdl | 19 ------------------- Example/full_adder/full_adder_slv.vhdl | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 19 deletions(-) delete mode 100644 Example/full_adder/full_adder.vhdl create mode 100644 Example/full_adder/full_adder_slv.vhdl (limited to 'Example/full_adder') diff --git a/Example/full_adder/full_adder.vhdl b/Example/full_adder/full_adder.vhdl deleted file mode 100644 index 745fac3..0000000 --- a/Example/full_adder/full_adder.vhdl +++ /dev/null @@ -1,19 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity full_adder is - port ( - i_bit1 : in std_logic_vector(0 downto 0); - i_bit2 : in std_logic_vector(0 downto 0); - i_bit3 : in std_logic_vector(0 downto 0); - o_sum : out std_logic_vector(0 downto 0); - o_carry : out std_logic_vector(0 downto 0) - ); -end full_adder; - -architecture rtl of full_adder is -begin - o_sum <= i_bit1 xor i_bit2 xor i_bit3; - o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); -end rtl; diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/full_adder/full_adder_slv.vhdl new file mode 100644 index 0000000..a0495f0 --- /dev/null +++ b/Example/full_adder/full_adder_slv.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity full_adder_slv is + port ( + i_bit1 : in std_logic_vector(0 downto 0); + i_bit2 : in std_logic_vector(0 downto 0); + i_bit3 : in std_logic_vector(0 downto 0); + o_sum : out std_logic_vector(0 downto 0); + o_carry : out std_logic_vector(0 downto 0) + ); +end full_adder_slv; + +architecture rtl of full_adder_slv is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3; + o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); +end rtl; -- cgit