From a6394b20adf8176755d6f16e86550a8ffb14b5a7 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Sun, 7 Jul 2019 18:39:16 +0530
Subject: Update and rename full_adder.vhdl to full_adder_slv.vhdl

---
 Example/full_adder/full_adder_slv.vhdl | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Example/full_adder/full_adder_slv.vhdl

(limited to 'Example/full_adder/full_adder_slv.vhdl')

diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/full_adder/full_adder_slv.vhdl
new file mode 100644
index 0000000..a0495f0
--- /dev/null
+++ b/Example/full_adder/full_adder_slv.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_slv is
+  port (
+    i_bit1  : in std_logic_vector(0 downto 0);
+    i_bit2  : in std_logic_vector(0 downto 0);
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end full_adder_slv;
+ 
+architecture rtl of full_adder_slv is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
-- 
cgit 


From 45f2669e5ba6760c6adaacb564c0799d54a11052 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Sun, 7 Jul 2019 18:48:17 +0530
Subject: std_logic_vector

---
 Example/full_adder/full_adder_slv.vhdl | 19 -------------------
 1 file changed, 19 deletions(-)
 delete mode 100644 Example/full_adder/full_adder_slv.vhdl

(limited to 'Example/full_adder/full_adder_slv.vhdl')

diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/full_adder/full_adder_slv.vhdl
deleted file mode 100644
index a0495f0..0000000
--- a/Example/full_adder/full_adder_slv.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity full_adder_slv is
-  port (
-    i_bit1  : in std_logic_vector(0 downto 0);
-    i_bit2  : in std_logic_vector(0 downto 0);
-    i_bit3  : in std_logic_vector(0 downto 0);
-    o_sum   : out std_logic_vector(0 downto 0);
-    o_carry : out std_logic_vector(0 downto 0)
-    );
-end full_adder_slv;
- 
-architecture rtl of full_adder_slv is
-begin
-  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
-  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
-end rtl;
-- 
cgit 


From 385d1b79fa4d4a4c9fe39f72cd87d53b247704d4 Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Sun, 7 Jul 2019 18:48:39 +0530
Subject: std_logic_vector

---
 Example/full_adder/full_adder_slv.vhdl | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Example/full_adder/full_adder_slv.vhdl

(limited to 'Example/full_adder/full_adder_slv.vhdl')

diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/full_adder/full_adder_slv.vhdl
new file mode 100644
index 0000000..a0495f0
--- /dev/null
+++ b/Example/full_adder/full_adder_slv.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_slv is
+  port (
+    i_bit1  : in std_logic_vector(0 downto 0);
+    i_bit2  : in std_logic_vector(0 downto 0);
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end full_adder_slv;
+ 
+architecture rtl of full_adder_slv is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
-- 
cgit