From eb95026ab9007631eb8e2a1c54dcd38fabcb60ad Mon Sep 17 00:00:00 2001
From: saurabhb17
Date: Wed, 18 Dec 2019 15:13:23 +0530
Subject: Examples Restructered

---
 Example/combinational_logic/half_adder/half_adder.vhdl | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 Example/combinational_logic/half_adder/half_adder.vhdl

(limited to 'Example/combinational_logic/half_adder/half_adder.vhdl')

diff --git a/Example/combinational_logic/half_adder/half_adder.vhdl b/Example/combinational_logic/half_adder/half_adder.vhdl
new file mode 100644
index 0000000..71ef1cc
--- /dev/null
+++ b/Example/combinational_logic/half_adder/half_adder.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity half_adder is
+  port (
+    i_bit0  : in std_logic_vector(0 downto 0);
+    i_bit1  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end half_adder;
+ 
+architecture rtl of half_adder is
+begin
+  o_sum   <= i_bit0 xor i_bit1;
+  o_carry <= i_bit0 and i_bit1;
+end rtl;
-- 
cgit