From 09181d02231704f6d691eccfa380eea77503383d Mon Sep 17 00:00:00 2001
From: saurabhb17
Date: Mon, 30 Dec 2019 12:33:07 +0530
Subject: Examples modified

---
 .../combinational_logic/counter/decadecounter.vhdl | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Example/combinational_logic/counter/decadecounter.vhdl

(limited to 'Example/combinational_logic/counter/decadecounter.vhdl')

diff --git a/Example/combinational_logic/counter/decadecounter.vhdl b/Example/combinational_logic/counter/decadecounter.vhdl
new file mode 100644
index 0000000..6d84280
--- /dev/null
+++ b/Example/combinational_logic/counter/decadecounter.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity decadecounter is
+	port(CLK : in std_logic;
+	     RST : in std_logic;
+	     Count : out std_logic_vector(9 downto 0));
+end decadecounter;
+
+architecture beh of decadecounter is
+	signal a: std_logic_vector(9 downto 0) := "0000000001";
+begin
+	process(CLK, RST)
+	begin
+		if RST = '1' then
+			a <= "0000000001";
+		elsif rising_edge(CLK) then
+			a <= a(0) & a(9 downto 1);  -- rotating left
+		end if;
+	end process;
+	Count <= std_logic_vector (a);
+end beh;
-- 
cgit