From 0f8995a96904608b5e7a596d30547225f92e83be Mon Sep 17 00:00:00 2001
From: Rahul Paknikar
Date: Sun, 7 Jul 2019 18:51:12 +0530
Subject: std_logic

---
 Example/full_adder/full_adder_sl.vhdl | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Example/full_adder/full_adder_sl.vhdl

diff --git a/Example/full_adder/full_adder_sl.vhdl b/Example/full_adder/full_adder_sl.vhdl
new file mode 100644
index 0000000..e830563
--- /dev/null
+++ b/Example/full_adder/full_adder_sl.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_sl is
+  port (
+    i_bit1  : in std_logic;
+    i_bit2  : in std_logic;
+    i_bit3  : in std_logic;
+    o_sum   : out std_logic;
+    o_carry : out std_logic
+    );
+end full_adder_sl;
+ 
+architecture rtl of full_adder_sl is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
\ No newline at end of file
-- 
cgit