From 09181d02231704f6d691eccfa380eea77503383d Mon Sep 17 00:00:00 2001 From: saurabhb17 Date: Mon, 30 Dec 2019 12:33:07 +0530 Subject: Examples modified --- Example/combinational_logic/counter/counter.vhdl | 30 ------------------- .../combinational_logic/counter/decadecounter.vhdl | 23 +++++++++++++++ .../combinational_logic/counter/up_counter.vhdl | 34 ++++++++++++++++++++++ .../counter/up_counter_slv.vhdl | 32 ++++++++++++++++++++ .../full_adder/full_adder_sl.vhdl | 3 +- .../full_adder/full_adder_sl_slv.vhdl | 3 +- .../full_adder/full_adder_slv.vhdl | 1 + .../full_adder/full_adder_structural.vhdl | 3 +- 8 files changed, 96 insertions(+), 33 deletions(-) delete mode 100644 Example/combinational_logic/counter/counter.vhdl create mode 100644 Example/combinational_logic/counter/decadecounter.vhdl create mode 100644 Example/combinational_logic/counter/up_counter.vhdl create mode 100644 Example/combinational_logic/counter/up_counter_slv.vhdl diff --git a/Example/combinational_logic/counter/counter.vhdl b/Example/combinational_logic/counter/counter.vhdl deleted file mode 100644 index ba14df8..0000000 --- a/Example/combinational_logic/counter/counter.vhdl +++ /dev/null @@ -1,30 +0,0 @@ -library ieee; - -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity counter is -port(C : in std_logic; - CLR : in std_logic; - Q : out std_logic_vector(3 downto 0)); -end counter; - -architecture bhv of counter is - - signal tmp: std_logic_vector(3 downto 0); - begin - process (C, CLR) - - begin - if (CLR='1') then - tmp <= "0000"; - - elsif (C'event and C='1') then - tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length)); - - end if; - - end process; - Q <= tmp; - -end bhv; \ No newline at end of file diff --git a/Example/combinational_logic/counter/decadecounter.vhdl b/Example/combinational_logic/counter/decadecounter.vhdl new file mode 100644 index 0000000..6d84280 --- /dev/null +++ b/Example/combinational_logic/counter/decadecounter.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity decadecounter is + port(CLK : in std_logic; + RST : in std_logic; + Count : out std_logic_vector(9 downto 0)); +end decadecounter; + +architecture beh of decadecounter is + signal a: std_logic_vector(9 downto 0) := "0000000001"; +begin + process(CLK, RST) + begin + if RST = '1' then + a <= "0000000001"; + elsif rising_edge(CLK) then + a <= a(0) & a(9 downto 1); -- rotating left + end if; + end process; + Count <= std_logic_vector (a); +end beh; diff --git a/Example/combinational_logic/counter/up_counter.vhdl b/Example/combinational_logic/counter/up_counter.vhdl new file mode 100644 index 0000000..80e9783 --- /dev/null +++ b/Example/combinational_logic/counter/up_counter.vhdl @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity up_counter is + port(Clock : in std_logic; + CLR : in std_logic; + Q : out std_logic_vector(3 downto 0)); +end up_counter; + +architecture beh of up_counter is + signal tmp: unsigned(3 downto 0) := "0000"; + + --------------- Other ways to initialize -------------- + -- signal tmp: unsigned(3 downto 0) := x"0"; + -- signal tmp: unsigned(3 downto 0) := (others => '0'); + ------------------------------------------------------- + + begin + process (Clock, CLR) + begin + if (CLR='1') then + tmp <= "0000"; + elsif (Clock'event and Clock='1') then + if tmp="1111" then + tmp <= x"0"; + else + tmp <= tmp +1; + end if; + end if; + end process; + + Q <= std_logic_vector (tmp); +end beh; diff --git a/Example/combinational_logic/counter/up_counter_slv.vhdl b/Example/combinational_logic/counter/up_counter_slv.vhdl new file mode 100644 index 0000000..ec8a558 --- /dev/null +++ b/Example/combinational_logic/counter/up_counter_slv.vhdl @@ -0,0 +1,32 @@ +-- This logic is implemented in up_counter.vhdl example as well, but there tmp variable is declared as unsigned +--whereas here it is declared as std_logic_vector; which requires type conversion. +--slv stands for std_logic_vector +library ieee; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity up_counter_slv is +port(C : in std_logic; + CLR : in std_logic; + Q : out std_logic_vector(3 downto 0)); +end up_counter_slv; + +architecture bhv of up_counter_slv is + + signal tmp: std_logic_vector(3 downto 0); + begin + process (C, CLR) + begin + if (CLR='1') then + tmp <= "0000"; + + elsif (C'event and C='1') then + tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length)); + + end if; + + end process; + Q <= tmp; + +end bhv; diff --git a/Example/combinational_logic/full_adder/full_adder_sl.vhdl b/Example/combinational_logic/full_adder/full_adder_sl.vhdl index e830563..99976ba 100644 --- a/Example/combinational_logic/full_adder/full_adder_sl.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_sl.vhdl @@ -1,3 +1,4 @@ +-- This file uses only std_logic(sl) variable types library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; @@ -16,4 +17,4 @@ architecture rtl of full_adder_sl is begin o_sum <= i_bit1 xor i_bit2 xor i_bit3; o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); -end rtl; \ No newline at end of file +end rtl; diff --git a/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl index 7de9c1b..cd7b5f3 100644 --- a/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl @@ -1,3 +1,4 @@ +--This file uses combination of std_logic(sl) and std_logic_vector(slv) variable types library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; @@ -16,4 +17,4 @@ architecture rtl of full_adder_sl_slv is begin o_sum <= i_bit1 xor i_bit2 xor i_bit3(0); o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1); -end rtl; \ No newline at end of file +end rtl; diff --git a/Example/combinational_logic/full_adder/full_adder_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_slv.vhdl index a0495f0..8dccce9 100644 --- a/Example/combinational_logic/full_adder/full_adder_slv.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_slv.vhdl @@ -1,3 +1,4 @@ +--This file uses only std_logic_vector(slv) variable type library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/Example/combinational_logic/full_adder/full_adder_structural.vhdl b/Example/combinational_logic/full_adder/full_adder_structural.vhdl index eb06a3d..ad13a2d 100644 --- a/Example/combinational_logic/full_adder/full_adder_structural.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_structural.vhdl @@ -1,3 +1,4 @@ +--This file uses structural style and uses only std_logic variable type library ieee; use ieee.std_logic_1164.all; @@ -84,4 +85,4 @@ u4 : andgate port map(a,b,c3); u5 : orgate port map(c2,c3,carry); -end structural; \ No newline at end of file +end structural; -- cgit