diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/createKicadLibrary.py | 11 | ||||
| -rw-r--r-- | src/model_generation.py | 7 |
2 files changed, 14 insertions, 4 deletions
diff --git a/src/createKicadLibrary.py b/src/createKicadLibrary.py index bf520d1..d229066 100644 --- a/src/createKicadLibrary.py +++ b/src/createKicadLibrary.py @@ -21,11 +21,12 @@ class AutoSchematic(QtGui.QWidget): for root, dirs, files in os.walk(self.xml_loc): if (str(self.modelname) + '.xml') in files: xmlFound = root + print(xmlFound) if (xmlFound == None): self.getPortInformation() self.createXML() self.createLib() - elif (xmlFound == self.xml_loc + 'Nghdl'): + elif (xmlFound == self.xml_loc + '/Nghdl'): print 'Library already exists...' ret = QtGui.QMessageBox.critical(self, "Critical",'''<b>The Libraries of this model already exist.Do you want to overwrite it?</b><br/> <b>If yes press ok else cancel it and change the name of your vhdl file</b>''', QtGui.QMessageBox.Ok, QtGui.QMessageBox.Cancel) @@ -43,7 +44,7 @@ class AutoSchematic(QtGui.QWidget): ret = QtGui.QMessageBox.critical(self, "Error",'''<b>A standard library already exists in this name.</b><br/> <b>Please change the name of your vhdl file and upload it again</b>''', QtGui.QMessageBox.Ok) - quit() + # quit() def getPortInformation(self): portInformation = PortInfo(self) @@ -164,8 +165,14 @@ class AutoSchematic(QtGui.QWidget): output_port = output_port.split() inputs = self.portInfo[0: self.input_length] outputs = self.portInfo[self.input_length:] + + print "INPUTS AND OUTPUTS " + print inputs + print outputs + inputs = self.char_sum(inputs) outputs= self.char_sum(outputs) + total = inputs+outputs port_list = [] diff --git a/src/model_generation.py b/src/model_generation.py index 15dc3e6..9a1aec8 100644 --- a/src/model_generation.py +++ b/src/model_generation.py @@ -92,7 +92,9 @@ data=read_file.readlines() read_file.close() #Extracting input and output port list from data +print "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" for line in data: + print line if re.match(r'^\s*$', line): pass #print "Blank Line" @@ -216,9 +218,9 @@ init_else=''' ''' els_evt_ptr=[] -els_evt_count1=[] +els_evt_count1=0 +els_evt_count2=0 for item in output_port: - els_evt_count2=0 els_evt_ptr.append("_op_"+item.split(":")[0]+" = cm_event_get_ptr("+str(els_evt_count1)+","+str(els_evt_count2)+");") els_evt_count2=els_evt_count2+1 els_evt_ptr.append("_op_"+item.split(":")[0]+"_old"+" = cm_event_get_ptr("+str(els_evt_count1)+","+str(els_evt_count2)+");") @@ -612,6 +614,7 @@ ifspec.close() print "Starting with testbench file" testbench=open(fname.split('.')[0]+'_tb.vhdl','w') +print fname.split('.')[0] + '_tb.vhdl' #comment comment_vhdl="--------------------------------------------------------------------------------\n--This testbench has been created by Ambikeshwar Srivastava, FOSSEE, IIT Bombay\n-------------------------------------------------------------------------------" #Adding header, entity and architecture statement |