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-rw-r--r--Example/full_adder/trial_ha.vhdl17
1 files changed, 17 insertions, 0 deletions
diff --git a/Example/full_adder/trial_ha.vhdl b/Example/full_adder/trial_ha.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity trial_ha is
+ port (
+ i_bit : in std_logic_vector(1 downto 0);
+ o_sum : out std_logic_vector(0 downto 0);
+ o_carry : out std_logic_vector(0 downto 0)
+ );
+end trial_ha;
+
+architecture rtl of trial_ha is
+begin
+ o_sum <= i_bit(0) xor i_bit(1);
+ o_carry <= i_bit(0) and i_bit(1);
+end rtl; \ No newline at end of file