diff options
Diffstat (limited to 'Example')
| -rw-r--r-- | Example/counter/up_counter.vhdl | 34 | ||||
| -rw-r--r-- | Example/counter/up_counter_slv.vhdl | 24 |
2 files changed, 58 insertions, 0 deletions
diff --git a/Example/counter/up_counter.vhdl b/Example/counter/up_counter.vhdl new file mode 100644 index 0000000..bd27fcf --- /dev/null +++ b/Example/counter/up_counter.vhdl @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity up_counter is + port(Clock : in std_logic; + CLR : in std_logic; + Q : out std_logic_vector(3 downto 0)); +end up_counter; + +architecture beh of up_counter is + signal tmp: unsigned(3 downto 0) := "0000"; + + --------------- Other ways to initialize -------------- + -- signal tmp: unsigned(3 downto 0) := x"0"; + -- signal tmp: unsigned(3 downto 0) := (others => '0'); + ------------------------------------------------------- + + begin + process (Clock, CLR) + begin + if (CLR='1') then + tmp <= "0000"; + elsif (Clock'event and Clock='1') then + if tmp="1111" then + tmp <= x"0"; + else + tmp <= tmp +1; + end if; + end if; + end process; + + Q <= std_logic_vector (tmp); +end beh;
\ No newline at end of file diff --git a/Example/counter/up_counter_slv.vhdl b/Example/counter/up_counter_slv.vhdl new file mode 100644 index 0000000..afef463 --- /dev/null +++ b/Example/counter/up_counter_slv.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity up_counter_slv is +port(C : in std_logic; + CLR : in std_logic; + Q : out std_logic_vector(3 downto 0)); +end up_counter_slv; + +architecture bhv of up_counter_slv is + signal tmp: std_logic_vector(3 downto 0); + begin + process (C, CLR) + begin + if (CLR='1') then + tmp <= "0000"; + elsif (C'event and C='1') then + tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length)); + end if; + end process; + Q <= tmp; + +end bhv;
\ No newline at end of file |