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-rw-r--r--Example/mux-demux/demux.vhdl32
-rw-r--r--Example/mux-demux/mux.vhdl30
2 files changed, 0 insertions, 62 deletions
diff --git a/Example/mux-demux/demux.vhdl b/Example/mux-demux/demux.vhdl
deleted file mode 100644
index e73c196..0000000
--- a/Example/mux-demux/demux.vhdl
+++ /dev/null
@@ -1,32 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity demux is
- port(
-
- F : in STD_LOGIC_vector(0 downto 0);
- S0: in STD_LOGIC_vector(0 downto 0);
- S1: in STD_LOGIC_vector(0 downto 0);
- A: out STD_LOGIC_vector(0 downto 0);
- B: out STD_LOGIC_vector(0 downto 0);
- C: out STD_LOGIC_vector(0 downto 0);
- D: out STD_LOGIC_vector(0 downto 0)
- );
-end demux;
-
-architecture bhv of demux is
-begin
-process (F,S0,S1) is
-begin
- if (S0 ="0" and S1 = "0") then
- A <= F;
- elsif (S0 ="1" and S1 = "0") then
- B <= F;
- elsif (S0 ="0" and S1 = "1") then
- C <= F;
- else
- D <= F;
- end if;
-
-end process;
-end bhv;
diff --git a/Example/mux-demux/mux.vhdl b/Example/mux-demux/mux.vhdl
deleted file mode 100644
index b72e287..0000000
--- a/Example/mux-demux/mux.vhdl
+++ /dev/null
@@ -1,30 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity mux is
- port(A : in std_logic;
- B : in std_logic;
- C : in std_logic;
- D : in std_logic;
- S0 : in std_logic;
- S1 : in std_logic;
- Z: out std_logic);
-end mux;
-
-architecture bhv of mux is
-begin
-process (A,B,C,D,S0,S1) is
-begin
- if (S0 ='0' and S1 = '0') then
- Z <= A;
- elsif (S0 ='0' and S1 = '1') then
- Z <= B;
- elsif (S0 ='1' and S1 = '0') then
- Z <= C;
- else
- Z <= D;
- end if;
-
-end process;
-end bhv;
-