2 files changed, 18 insertions, 17 deletions
diff --git a/Example/half_adder/half_adder.vhdl b/Example/half_adder/half_adder.vhdl
new file mode 100644
index 0000000..71ef1cc
--- /dev/null
+++ b/Example/half_adder/half_adder.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity half_adder is
+  port (
+    i_bit0  : in std_logic_vector(0 downto 0);
+    i_bit1  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end half_adder;
+ 
+architecture rtl of half_adder is
+begin
+  o_sum   <= i_bit0 xor i_bit1;
+  o_carry <= i_bit0 and i_bit1;
+end rtl;
diff --git a/Example/half_adder/trial_ha.vhdl b/Example/half_adder/trial_ha.vhdl
deleted file mode 100644
index 30e7938..0000000
--- a/Example/half_adder/trial_ha.vhdl
+++ /dev/null
@@ -1,17 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity trial_ha is
-  port (
-    i_bit  : in std_logic_vector(1 downto 0);
-    o_sum   : out std_logic_vector(0 downto 0);
-    o_carry : out std_logic_vector(0 downto 0)
-    );
-end trial_ha;
- 
-architecture rtl of trial_ha is
-begin
-  o_sum   <= i_bit(0) xor i_bit(1);
-  o_carry <= i_bit(0) and i_bit(1);
-end rtl;
-\ No newline at end of file