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-rw-r--r--Example/esim_trial_xor/esim_trial_xor.vhdl15
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diff --git a/Example/esim_trial_xor/esim_trial_xor.vhdl b/Example/esim_trial_xor/esim_trial_xor.vhdl
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+++ b/Example/esim_trial_xor/esim_trial_xor.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity esim_trial_xor is
+ port (a : in std_logic_vector(0 downto 0);
+ b : in std_logic_vector(0 downto 0);
+ c : out std_logic_vector(0 downto 0));
+ end esim_trial_xor;
+
+ architecture rtl of esim_trial_xor is
+ begin
+
+ c <= a xor b;
+
+ end rtl;