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-rw-r--r--Example/combinational_logic/bin_to_gray/bin_to_gray.vhdl21
-rw-r--r--Example/combinational_logic/counter/decadecounter.vhdl23
-rw-r--r--Example/combinational_logic/counter/up_counter.vhdl34
-rw-r--r--Example/combinational_logic/counter/up_counter_slv.vhdl32
-rw-r--r--Example/combinational_logic/counter/updown_counter.vhdl32
-rw-r--r--Example/combinational_logic/decoder/decoder.vhdl50
-rw-r--r--Example/combinational_logic/full_adder/full_adder_sl.vhdl20
-rw-r--r--Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl20
-rw-r--r--Example/combinational_logic/full_adder/full_adder_slv.vhdl20
-rw-r--r--Example/combinational_logic/full_adder/full_adder_structural.vhdl88
-rw-r--r--Example/combinational_logic/half_adder/half_adder.vhdl18
-rw-r--r--Example/combinational_logic/mux-demux/demux.vhdl32
-rw-r--r--Example/combinational_logic/mux-demux/mux.vhdl30
13 files changed, 420 insertions, 0 deletions
diff --git a/Example/combinational_logic/bin_to_gray/bin_to_gray.vhdl b/Example/combinational_logic/bin_to_gray/bin_to_gray.vhdl
new file mode 100644
index 0000000..d6045e8
--- /dev/null
+++ b/Example/combinational_logic/bin_to_gray/bin_to_gray.vhdl
@@ -0,0 +1,21 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+entity bin_to_gray is
+port(
+ bin : in std_logic_vector(3 downto 0);
+ G : out std_logic_vector(3 downto 0)
+ );
+end bin_to_gray;
+
+
+architecture gate_level of bin_to_gray is
+
+begin
+
+G(3) <= bin(3);
+G(2) <= bin(3) xor bin(2);
+G(1) <= bin(2) xor bin(1);
+G(0) <= bin(1) xor bin(0);
+
+end gate_level; \ No newline at end of file
diff --git a/Example/combinational_logic/counter/decadecounter.vhdl b/Example/combinational_logic/counter/decadecounter.vhdl
new file mode 100644
index 0000000..6d84280
--- /dev/null
+++ b/Example/combinational_logic/counter/decadecounter.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity decadecounter is
+ port(CLK : in std_logic;
+ RST : in std_logic;
+ Count : out std_logic_vector(9 downto 0));
+end decadecounter;
+
+architecture beh of decadecounter is
+ signal a: std_logic_vector(9 downto 0) := "0000000001";
+begin
+ process(CLK, RST)
+ begin
+ if RST = '1' then
+ a <= "0000000001";
+ elsif rising_edge(CLK) then
+ a <= a(0) & a(9 downto 1); -- rotating left
+ end if;
+ end process;
+ Count <= std_logic_vector (a);
+end beh;
diff --git a/Example/combinational_logic/counter/up_counter.vhdl b/Example/combinational_logic/counter/up_counter.vhdl
new file mode 100644
index 0000000..80e9783
--- /dev/null
+++ b/Example/combinational_logic/counter/up_counter.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity up_counter is
+ port(Clock : in std_logic;
+ CLR : in std_logic;
+ Q : out std_logic_vector(3 downto 0));
+end up_counter;
+
+architecture beh of up_counter is
+ signal tmp: unsigned(3 downto 0) := "0000";
+
+ --------------- Other ways to initialize --------------
+ -- signal tmp: unsigned(3 downto 0) := x"0";
+ -- signal tmp: unsigned(3 downto 0) := (others => '0');
+ -------------------------------------------------------
+
+ begin
+ process (Clock, CLR)
+ begin
+ if (CLR='1') then
+ tmp <= "0000";
+ elsif (Clock'event and Clock='1') then
+ if tmp="1111" then
+ tmp <= x"0";
+ else
+ tmp <= tmp +1;
+ end if;
+ end if;
+ end process;
+
+ Q <= std_logic_vector (tmp);
+end beh;
diff --git a/Example/combinational_logic/counter/up_counter_slv.vhdl b/Example/combinational_logic/counter/up_counter_slv.vhdl
new file mode 100644
index 0000000..ec8a558
--- /dev/null
+++ b/Example/combinational_logic/counter/up_counter_slv.vhdl
@@ -0,0 +1,32 @@
+-- This logic is implemented in up_counter.vhdl example as well, but there tmp variable is declared as unsigned
+--whereas here it is declared as std_logic_vector; which requires type conversion.
+--slv stands for std_logic_vector
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity up_counter_slv is
+port(C : in std_logic;
+ CLR : in std_logic;
+ Q : out std_logic_vector(3 downto 0));
+end up_counter_slv;
+
+architecture bhv of up_counter_slv is
+
+ signal tmp: std_logic_vector(3 downto 0);
+ begin
+ process (C, CLR)
+ begin
+ if (CLR='1') then
+ tmp <= "0000";
+
+ elsif (C'event and C='1') then
+ tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length));
+
+ end if;
+
+ end process;
+ Q <= tmp;
+
+end bhv;
diff --git a/Example/combinational_logic/counter/updown_counter.vhdl b/Example/combinational_logic/counter/updown_counter.vhdl
new file mode 100644
index 0000000..922ee67
--- /dev/null
+++ b/Example/combinational_logic/counter/updown_counter.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+
+entity updown_counter is
+ Port ( clk: in std_logic;
+ reset: in std_logic;
+ up_down: in std_logic;
+ counter: out std_logic_vector(3 downto 0)
+ );
+end updown_counter;
+
+architecture Behavioral of updown_counter is
+signal tmp: std_logic_vector(3 downto 0);
+begin
+
+process(clk,reset)
+begin
+ if(reset='1') then
+ tmp <= "0000";
+ elsif(clk'event and clk='1') then
+ if(up_down='1') then
+ tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)-1), tmp'length));
+ else
+ tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)+1), tmp'length));
+ end if;
+ end if;
+end process;
+ counter <= std_logic_vector(tmp);
+
+end Behavioral; \ No newline at end of file
diff --git a/Example/combinational_logic/decoder/decoder.vhdl b/Example/combinational_logic/decoder/decoder.vhdl
new file mode 100644
index 0000000..e429ec9
--- /dev/null
+++ b/Example/combinational_logic/decoder/decoder.vhdl
@@ -0,0 +1,50 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity decoder is
+port (
+ p : in std_logic_vector(4 downto 0);
+ d : out std_logic_vector(31 downto 0)
+ );
+end decoder;
+
+architecture behav of decoder is
+
+begin
+
+with p select
+d<="00000000000000000000000000000001" when "00000",
+"00000000000000000000000000000010" when "00001",
+"00000000000000000000000000000100" when "00010",
+"00000000000000000000000000001000" when "00011",
+"00000000000000000000000000010000" when "00100",
+"00000000000000000000000000100000" when "00101",
+"00000000000000000000000001000000" when "00110",
+"00000000000000000000000010000000" when "00111",
+"00000000000000000000000100000000" when "01000",
+"00000000000000000000001000000000" when "01001",
+"00000000000000000000010000000000" when "01010",
+"00000000000000000000100000000000" when "01011",
+"00000000000000000001000000000000" when "01100",
+"00000000000000000010000000000000" when "01101",
+"00000000000000000100000000000000" when "01110",
+"00000000000000001000000000000000" when "01111",
+"00000000000000010000000000000000" when "10000",
+"00000000000000100000000000000000" when "10001",
+"00000000000001000000000000000000" when "10010",
+"00000000000010000000000000000000" when "10011",
+"00000000000100000000000000000000" when "10100",
+"00000000001000000000000000000000" when "10101",
+"00000000010000000000000000000000" when "10110",
+"00000000100000000000000000000000" when "10111",
+"00000001000000000000000000000000" when "11000",
+"00000010000000000000000000000000" when "11001",
+"00000100000000000000000000000000" when "11010",
+"00001000000000000000000000000000" when "11011",
+"00010000000000000000000000000000" when "11100",
+"00100000000000000000000000000000" when "11101",
+"01000000000000000000000000000000" when "11110",
+"10000000000000000000000000000000" when "11111",
+"00000000000000000000000000000000" when others;
+
+end behav;
diff --git a/Example/combinational_logic/full_adder/full_adder_sl.vhdl b/Example/combinational_logic/full_adder/full_adder_sl.vhdl
new file mode 100644
index 0000000..99976ba
--- /dev/null
+++ b/Example/combinational_logic/full_adder/full_adder_sl.vhdl
@@ -0,0 +1,20 @@
+-- This file uses only std_logic(sl) variable types
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity full_adder_sl is
+ port (
+ i_bit1 : in std_logic;
+ i_bit2 : in std_logic;
+ i_bit3 : in std_logic;
+ o_sum : out std_logic;
+ o_carry : out std_logic
+ );
+end full_adder_sl;
+
+architecture rtl of full_adder_sl is
+begin
+ o_sum <= i_bit1 xor i_bit2 xor i_bit3;
+ o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
diff --git a/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl
new file mode 100644
index 0000000..cd7b5f3
--- /dev/null
+++ b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl
@@ -0,0 +1,20 @@
+--This file uses combination of std_logic(sl) and std_logic_vector(slv) variable types
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity full_adder_sl_slv is
+ port (
+ i_bit1 : in std_logic;
+ i_bit2 : in std_logic;
+ i_bit3 : in std_logic_vector(0 downto 0);
+ o_sum : out std_logic;
+ o_carry : out std_logic_vector(0 downto 0)
+ );
+end full_adder_sl_slv;
+
+architecture rtl of full_adder_sl_slv is
+begin
+ o_sum <= i_bit1 xor i_bit2 xor i_bit3(0);
+ o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1);
+end rtl;
diff --git a/Example/combinational_logic/full_adder/full_adder_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_slv.vhdl
new file mode 100644
index 0000000..8dccce9
--- /dev/null
+++ b/Example/combinational_logic/full_adder/full_adder_slv.vhdl
@@ -0,0 +1,20 @@
+--This file uses only std_logic_vector(slv) variable type
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity full_adder_slv is
+ port (
+ i_bit1 : in std_logic_vector(0 downto 0);
+ i_bit2 : in std_logic_vector(0 downto 0);
+ i_bit3 : in std_logic_vector(0 downto 0);
+ o_sum : out std_logic_vector(0 downto 0);
+ o_carry : out std_logic_vector(0 downto 0)
+ );
+end full_adder_slv;
+
+architecture rtl of full_adder_slv is
+begin
+ o_sum <= i_bit1 xor i_bit2 xor i_bit3;
+ o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
diff --git a/Example/combinational_logic/full_adder/full_adder_structural.vhdl b/Example/combinational_logic/full_adder/full_adder_structural.vhdl
new file mode 100644
index 0000000..ad13a2d
--- /dev/null
+++ b/Example/combinational_logic/full_adder/full_adder_structural.vhdl
@@ -0,0 +1,88 @@
+--This file uses structural style and uses only std_logic variable type
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity full_adder_structural is
+port(a: in std_logic;
+ b: in std_logic;
+ cin: in std_logic;
+ sum: out std_logic;
+ carry: out std_logic);
+end full_adder_structural;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity andgate is
+port(a: in std_logic;
+ b: in std_logic;
+ z: out std_logic);
+end andgate;
+
+architecture e1 of andgate is
+begin
+z <= a and b;
+end e1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xorgate is
+port(a: in std_logic;
+ b: in std_logic;
+ z: out std_logic);
+end xorgate;
+
+architecture e2 of xorgate is
+begin
+z <= a xor b;
+end e2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity orgate is
+port(a: in std_logic;
+ b: in std_logic;
+ z: out std_logic);
+end orgate;
+
+architecture e3 of orgate is
+begin
+z <= a or b;
+end e3;
+
+
+
+architecture structural of full_adder_structural is
+
+component andgate
+port(a: in std_logic;
+ b: in std_logic;
+ z: out std_logic);
+end component;
+
+component xorgate
+port(a: in std_logic;
+ b: in std_logic;
+ z: out std_logic);
+end component;
+
+component orgate
+port(a: in std_logic;
+ b: in std_logic;
+ z: out std_logic);
+end component;
+
+signal c1,c2,c3: std_logic;
+
+begin
+
+u1 : xorgate port map(a,b,c1);
+u2 : xorgate port map(c1,cin,sum);
+u3 : andgate port map(c1,cin,c2);
+u4 : andgate port map(a,b,c3);
+u5 : orgate port map(c2,c3,carry);
+
+
+end structural;
diff --git a/Example/combinational_logic/half_adder/half_adder.vhdl b/Example/combinational_logic/half_adder/half_adder.vhdl
new file mode 100644
index 0000000..71ef1cc
--- /dev/null
+++ b/Example/combinational_logic/half_adder/half_adder.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity half_adder is
+ port (
+ i_bit0 : in std_logic_vector(0 downto 0);
+ i_bit1 : in std_logic_vector(0 downto 0);
+ o_sum : out std_logic_vector(0 downto 0);
+ o_carry : out std_logic_vector(0 downto 0)
+ );
+end half_adder;
+
+architecture rtl of half_adder is
+begin
+ o_sum <= i_bit0 xor i_bit1;
+ o_carry <= i_bit0 and i_bit1;
+end rtl;
diff --git a/Example/combinational_logic/mux-demux/demux.vhdl b/Example/combinational_logic/mux-demux/demux.vhdl
new file mode 100644
index 0000000..e73c196
--- /dev/null
+++ b/Example/combinational_logic/mux-demux/demux.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity demux is
+ port(
+
+ F : in STD_LOGIC_vector(0 downto 0);
+ S0: in STD_LOGIC_vector(0 downto 0);
+ S1: in STD_LOGIC_vector(0 downto 0);
+ A: out STD_LOGIC_vector(0 downto 0);
+ B: out STD_LOGIC_vector(0 downto 0);
+ C: out STD_LOGIC_vector(0 downto 0);
+ D: out STD_LOGIC_vector(0 downto 0)
+ );
+end demux;
+
+architecture bhv of demux is
+begin
+process (F,S0,S1) is
+begin
+ if (S0 ="0" and S1 = "0") then
+ A <= F;
+ elsif (S0 ="1" and S1 = "0") then
+ B <= F;
+ elsif (S0 ="0" and S1 = "1") then
+ C <= F;
+ else
+ D <= F;
+ end if;
+
+end process;
+end bhv;
diff --git a/Example/combinational_logic/mux-demux/mux.vhdl b/Example/combinational_logic/mux-demux/mux.vhdl
new file mode 100644
index 0000000..b72e287
--- /dev/null
+++ b/Example/combinational_logic/mux-demux/mux.vhdl
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity mux is
+ port(A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ S0 : in std_logic;
+ S1 : in std_logic;
+ Z: out std_logic);
+end mux;
+
+architecture bhv of mux is
+begin
+process (A,B,C,D,S0,S1) is
+begin
+ if (S0 ='0' and S1 = '0') then
+ Z <= A;
+ elsif (S0 ='0' and S1 = '1') then
+ Z <= B;
+ elsif (S0 ='1' and S1 = '0') then
+ Z <= C;
+ else
+ Z <= D;
+ end if;
+
+end process;
+end bhv;
+
generated by cgit (git 2.34.1) at 2025-01-12 11:57:17 +0000