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Diffstat (limited to 'Example/combinational_logic/counter')
4 files changed, 121 insertions, 0 deletions
diff --git a/Example/combinational_logic/counter/decadecounter.vhdl b/Example/combinational_logic/counter/decadecounter.vhdl new file mode 100644 index 0000000..6d84280 --- /dev/null +++ b/Example/combinational_logic/counter/decadecounter.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity decadecounter is + port(CLK : in std_logic; + RST : in std_logic; + Count : out std_logic_vector(9 downto 0)); +end decadecounter; + +architecture beh of decadecounter is + signal a: std_logic_vector(9 downto 0) := "0000000001"; +begin + process(CLK, RST) + begin + if RST = '1' then + a <= "0000000001"; + elsif rising_edge(CLK) then + a <= a(0) & a(9 downto 1); -- rotating left + end if; + end process; + Count <= std_logic_vector (a); +end beh; diff --git a/Example/combinational_logic/counter/up_counter.vhdl b/Example/combinational_logic/counter/up_counter.vhdl new file mode 100644 index 0000000..80e9783 --- /dev/null +++ b/Example/combinational_logic/counter/up_counter.vhdl @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity up_counter is + port(Clock : in std_logic; + CLR : in std_logic; + Q : out std_logic_vector(3 downto 0)); +end up_counter; + +architecture beh of up_counter is + signal tmp: unsigned(3 downto 0) := "0000"; + + --------------- Other ways to initialize -------------- + -- signal tmp: unsigned(3 downto 0) := x"0"; + -- signal tmp: unsigned(3 downto 0) := (others => '0'); + ------------------------------------------------------- + + begin + process (Clock, CLR) + begin + if (CLR='1') then + tmp <= "0000"; + elsif (Clock'event and Clock='1') then + if tmp="1111" then + tmp <= x"0"; + else + tmp <= tmp +1; + end if; + end if; + end process; + + Q <= std_logic_vector (tmp); +end beh; diff --git a/Example/combinational_logic/counter/up_counter_slv.vhdl b/Example/combinational_logic/counter/up_counter_slv.vhdl new file mode 100644 index 0000000..ec8a558 --- /dev/null +++ b/Example/combinational_logic/counter/up_counter_slv.vhdl @@ -0,0 +1,32 @@ +-- This logic is implemented in up_counter.vhdl example as well, but there tmp variable is declared as unsigned +--whereas here it is declared as std_logic_vector; which requires type conversion. +--slv stands for std_logic_vector +library ieee; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity up_counter_slv is +port(C : in std_logic; + CLR : in std_logic; + Q : out std_logic_vector(3 downto 0)); +end up_counter_slv; + +architecture bhv of up_counter_slv is + + signal tmp: std_logic_vector(3 downto 0); + begin + process (C, CLR) + begin + if (CLR='1') then + tmp <= "0000"; + + elsif (C'event and C='1') then + tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length)); + + end if; + + end process; + Q <= tmp; + +end bhv; diff --git a/Example/combinational_logic/counter/updown_counter.vhdl b/Example/combinational_logic/counter/updown_counter.vhdl new file mode 100644 index 0000000..922ee67 --- /dev/null +++ b/Example/combinational_logic/counter/updown_counter.vhdl @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + + +entity updown_counter is + Port ( clk: in std_logic; + reset: in std_logic; + up_down: in std_logic; + counter: out std_logic_vector(3 downto 0) + ); +end updown_counter; + +architecture Behavioral of updown_counter is +signal tmp: std_logic_vector(3 downto 0); +begin + +process(clk,reset) +begin + if(reset='1') then + tmp <= "0000"; + elsif(clk'event and clk='1') then + if(up_down='1') then + tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)-1), tmp'length)); + else + tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)+1), tmp'length)); + end if; + end if; +end process; + counter <= std_logic_vector(tmp); + +end Behavioral;
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