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-rw-r--r--Example/2-bit-inverter/inverter.vhdl14
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diff --git a/Example/2-bit-inverter/inverter.vhdl b/Example/2-bit-inverter/inverter.vhdl
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--- a/Example/2-bit-inverter/inverter.vhdl
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@@ -1,14 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity inverter is
- port ( i: in std_logic_vector(0 downto 0);
- o: out std_logic_vector(0 downto 0));
-end inverter;
-
-architecture inverter_beh of inverter is
-begin
- o <= not i;
-end inverter_beh;
-
-