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-rw-r--r--Example/2-bit-inverter/inverter.vhdl6
-rw-r--r--Example/bin_to_gray/bin_to_gray.vhdl21
-rw-r--r--Example/counter/counter.obin0 -> 7512 bytes
-rw-r--r--Example/counter/counter.vhdl22
-rw-r--r--Example/counter/work-obj93.cf4
-rw-r--r--Example/decoder/decoder.vhdl50
-rw-r--r--Example/esim_trial_xor/esim_trial_xor.vhdl15
-rw-r--r--Example/fa_SL/full_adder_sl.vhdl19
-rw-r--r--Example/fa_SL_SLV/full_adder_sl_slv.vhdl19
-rw-r--r--Example/nghdl_half_adder/nghdl_ha.vhdl22
-rw-r--r--Example/struct_fa/full_adder_structural.vhdl85
-rw-r--r--Example/trial_demux/t_demux.vhdl32
-rw-r--r--Example/trial_fa/trial_fa.vhdl19
-rw-r--r--doc/readme.md51
-rwxr-xr-xinstall-nghdl.sh89
-rw-r--r--src/ghdlserver/ghdlserver.c15
16 files changed, 388 insertions, 81 deletions
diff --git a/Example/2-bit-inverter/inverter.vhdl b/Example/2-bit-inverter/inverter.vhdl
index 9d65b8d..7eb3c67 100644
--- a/Example/2-bit-inverter/inverter.vhdl
+++ b/Example/2-bit-inverter/inverter.vhdl
@@ -2,13 +2,13 @@ library ieee;
use ieee.std_logic_1164.all;
entity inverter is
- port ( i: in std_logic_vector(1 downto 0);
- o: out std_logic_vector(1 downto 0));
+ port ( i: in std_logic_vector(0 downto 0);
+ o: out std_logic_vector(0 downto 0));
end inverter;
architecture inverter_beh of inverter is
begin
o <= not i;
-end architecture;
+end inverter_beh;
diff --git a/Example/bin_to_gray/bin_to_gray.vhdl b/Example/bin_to_gray/bin_to_gray.vhdl
new file mode 100644
index 0000000..542f7ec
--- /dev/null
+++ b/Example/bin_to_gray/bin_to_gray.vhdl
@@ -0,0 +1,21 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+entity bin_to_gray is
+port(
+ bin : in std_logic_vector(3 downto 0); -- binary input
+ G : out std_logic_vector(3 downto 0) -- gray code output
+ );
+end bin_to_gray;
+
+
+architecture gate_level of bin_to_gray is
+
+begin
+
+G(3) <= bin(3);
+G(2) <= bin(3) xor bin(2);
+G(1) <= bin(2) xor bin(1);
+G(0) <= bin(1) xor bin(0);
+
+end gate_level; \ No newline at end of file
diff --git a/Example/counter/counter.o b/Example/counter/counter.o
new file mode 100644
index 0000000..442cc73
--- /dev/null
+++ b/Example/counter/counter.o
Binary files differ
diff --git a/Example/counter/counter.vhdl b/Example/counter/counter.vhdl
new file mode 100644
index 0000000..6e16138
--- /dev/null
+++ b/Example/counter/counter.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter is
+port(C : in std_logic;
+ CLR : in std_logic;
+ Q : out std_logic_vector(3 downto 0));
+end counter;
+architecture bhv of counter is
+signal tmp: std_logic_vector(3 downto 0);
+begin
+process (C, CLR)
+begin
+if (CLR='1') then
+tmp <= "0000";
+elsif (C'event and C='1') then
+tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length));
+end if;
+end process;
+Q <= tmp;
+end bhv; \ No newline at end of file
diff --git a/Example/counter/work-obj93.cf b/Example/counter/work-obj93.cf
new file mode 100644
index 0000000..46d4772
--- /dev/null
+++ b/Example/counter/work-obj93.cf
@@ -0,0 +1,4 @@
+v 4
+file . "counter.vhdl" "849ecbdf1a2a5f5cd553b9ca6594e4a3ae1e214a" "20190710170933.911":
+ entity counter at 1( 0) + 0 on 13;
+ architecture bhv of counter at 11( 229) + 0 on 14;
diff --git a/Example/decoder/decoder.vhdl b/Example/decoder/decoder.vhdl
new file mode 100644
index 0000000..e429ec9
--- /dev/null
+++ b/Example/decoder/decoder.vhdl
@@ -0,0 +1,50 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity decoder is
+port (
+ p : in std_logic_vector(4 downto 0);
+ d : out std_logic_vector(31 downto 0)
+ );
+end decoder;
+
+architecture behav of decoder is
+
+begin
+
+with p select
+d<="00000000000000000000000000000001" when "00000",
+"00000000000000000000000000000010" when "00001",
+"00000000000000000000000000000100" when "00010",
+"00000000000000000000000000001000" when "00011",
+"00000000000000000000000000010000" when "00100",
+"00000000000000000000000000100000" when "00101",
+"00000000000000000000000001000000" when "00110",
+"00000000000000000000000010000000" when "00111",
+"00000000000000000000000100000000" when "01000",
+"00000000000000000000001000000000" when "01001",
+"00000000000000000000010000000000" when "01010",
+"00000000000000000000100000000000" when "01011",
+"00000000000000000001000000000000" when "01100",
+"00000000000000000010000000000000" when "01101",
+"00000000000000000100000000000000" when "01110",
+"00000000000000001000000000000000" when "01111",
+"00000000000000010000000000000000" when "10000",
+"00000000000000100000000000000000" when "10001",
+"00000000000001000000000000000000" when "10010",
+"00000000000010000000000000000000" when "10011",
+"00000000000100000000000000000000" when "10100",
+"00000000001000000000000000000000" when "10101",
+"00000000010000000000000000000000" when "10110",
+"00000000100000000000000000000000" when "10111",
+"00000001000000000000000000000000" when "11000",
+"00000010000000000000000000000000" when "11001",
+"00000100000000000000000000000000" when "11010",
+"00001000000000000000000000000000" when "11011",
+"00010000000000000000000000000000" when "11100",
+"00100000000000000000000000000000" when "11101",
+"01000000000000000000000000000000" when "11110",
+"10000000000000000000000000000000" when "11111",
+"00000000000000000000000000000000" when others;
+
+end behav;
diff --git a/Example/esim_trial_xor/esim_trial_xor.vhdl b/Example/esim_trial_xor/esim_trial_xor.vhdl
new file mode 100644
index 0000000..ff9190c
--- /dev/null
+++ b/Example/esim_trial_xor/esim_trial_xor.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity esim_trial_xor is
+ port (a : in std_logic_vector(0 downto 0);
+ b : in std_logic_vector(0 downto 0);
+ c : out std_logic_vector(0 downto 0));
+ end esim_trial_xor;
+
+ architecture rtl of esim_trial_xor is
+ begin
+
+ c <= a xor b;
+
+ end rtl;
diff --git a/Example/fa_SL/full_adder_sl.vhdl b/Example/fa_SL/full_adder_sl.vhdl
new file mode 100644
index 0000000..e830563
--- /dev/null
+++ b/Example/fa_SL/full_adder_sl.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity full_adder_sl is
+ port (
+ i_bit1 : in std_logic;
+ i_bit2 : in std_logic;
+ i_bit3 : in std_logic;
+ o_sum : out std_logic;
+ o_carry : out std_logic
+ );
+end full_adder_sl;
+
+architecture rtl of full_adder_sl is
+begin
+ o_sum <= i_bit1 xor i_bit2 xor i_bit3;
+ o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl; \ No newline at end of file
diff --git a/Example/fa_SL_SLV/full_adder_sl_slv.vhdl b/Example/fa_SL_SLV/full_adder_sl_slv.vhdl
new file mode 100644
index 0000000..7de9c1b
--- /dev/null
+++ b/Example/fa_SL_SLV/full_adder_sl_slv.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity full_adder_sl_slv is
+ port (
+ i_bit1 : in std_logic;
+ i_bit2 : in std_logic;
+ i_bit3 : in std_logic_vector(0 downto 0);
+ o_sum : out std_logic;
+ o_carry : out std_logic_vector(0 downto 0)
+ );
+end full_adder_sl_slv;
+
+architecture rtl of full_adder_sl_slv is
+begin
+ o_sum <= i_bit1 xor i_bit2 xor i_bit3(0);
+ o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1);
+end rtl; \ No newline at end of file
diff --git a/Example/nghdl_half_adder/nghdl_ha.vhdl b/Example/nghdl_half_adder/nghdl_ha.vhdl
new file mode 100644
index 0000000..f9f2e92
--- /dev/null
+++ b/Example/nghdl_half_adder/nghdl_ha.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity nghdl_ha is
+port (
+ i_bit1 : in std_logic_vector(0 downto 0);
+ i_bit2 : in std_logic_vector(0 downto 0);
+ o_sum : out std_logic_vector(0 downto 0);
+ o_carry : out std_logic_vector(0 downto 0)
+ );
+end nghdl_ha;
+
+
+architecture rtl of nghdl_ha is
+
+begin
+
+ o_sum <= i_bit1 xor i_bit2;
+ o_carry <= i_bit1 and i_bit2;
+
+end rtl; \ No newline at end of file
diff --git a/Example/struct_fa/full_adder_structural.vhdl b/Example/struct_fa/full_adder_structural.vhdl
new file mode 100644
index 0000000..91b2762
--- /dev/null
+++ b/Example/struct_fa/full_adder_structural.vhdl
@@ -0,0 +1,85 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity full_adder_structural is
+port(a: in std_logic;
+ b: in std_logic;
+ cin: in std_logic;
+ sum: out std_logic;
+ carry: out std_logic);
+end full_adder_structural;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity andgate is
+port(a: in std_logic;
+ b: in std_logic;
+ z: out std_logic);
+end andgate;
+
+architecture e1 of andgate is
+begin
+z <= a and b;
+end e1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xorgate is
+port(a: in std_logic;
+ b: in std_logic;
+ z: out std_logic);
+end xorgate;
+
+architecture e2 of xorgate is
+begin
+z <= a xor b;
+end e2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity orgate is
+port(a: in std_logic;
+ b: in std_logic;
+ z: out std_logic);
+end orgate;
+
+architecture e3 of orgate is
+begin
+z <= a or b;
+end e3;
+
+
+architecture structural of full_adder_structural is
+
+component andgate
+port(a: in std_logic;
+ b: in std_logic;
+ z: out std_logic);
+end component;
+
+component xorgate
+port(a: in std_logic;
+ b: in std_logic;
+ z: out std_logic);
+end component;
+
+component orgate
+port(a: in std_logic;
+ b: in std_logic;
+ z: out std_logic);
+end component;
+
+signal c1,c2,c3: std_logic;
+
+begin
+
+u1 : xorgate port map(a,b,c1);
+u2 : xorgate port map(c1,cin,sum);
+u3 : andgate port map(c1,cin,c2);
+u4 : andgate port map(a,b,c3);
+u5 : orgate port map(c2,c3,carry);
+
+end structural; \ No newline at end of file
diff --git a/Example/trial_demux/t_demux.vhdl b/Example/trial_demux/t_demux.vhdl
new file mode 100644
index 0000000..1e1f0bd
--- /dev/null
+++ b/Example/trial_demux/t_demux.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity t_demux is
+ port(
+
+ F : in STD_LOGIC_vector(0 downto 0);
+ S0: in STD_LOGIC_vector(0 downto 0);
+ S1: in STD_LOGIC_vector(0 downto 0);
+ A: out STD_LOGIC_vector(0 downto 0);
+ B: out STD_LOGIC_vector(0 downto 0);
+ C: out STD_LOGIC_vector(0 downto 0);
+ D: out STD_LOGIC_vector(0 downto 0)
+ );
+end t_demux;
+
+architecture bhv of t_demux is
+begin
+process (F,S0,S1) is
+begin
+ if (S0 ="0" and S1 = "0") then
+ A <= F;
+ elsif (S0 ="1" and S1 = "0") then
+ B <= F;
+ elsif (S0 ="0" and S1 = "1") then
+ C <= F;
+ else
+ D <= F;
+ end if;
+
+end process;
+end bhv; \ No newline at end of file
diff --git a/Example/trial_fa/trial_fa.vhdl b/Example/trial_fa/trial_fa.vhdl
new file mode 100644
index 0000000..6357aa2
--- /dev/null
+++ b/Example/trial_fa/trial_fa.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity trial_fa is
+ port (
+ i_bit1 : in std_logic_vector(0 downto 0);
+ i_bit2 : in std_logic_vector(0 downto 0);
+ i_bit3 : in std_logic_vector(0 downto 0);
+ o_sum : out std_logic_vector(0 downto 0);
+ o_carry : out std_logic_vector(0 downto 0)
+ );
+end trial_fa;
+
+architecture rtl of trial_fa is
+begin
+ o_sum <= i_bit1 xor i_bit2 xor i_bit3;
+ o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl; \ No newline at end of file
diff --git a/doc/readme.md b/doc/readme.md
deleted file mode 100644
index 7aa0c6e..0000000
--- a/doc/readme.md
+++ /dev/null
@@ -1,51 +0,0 @@
-Ngspice Ghdl Interfacing Documentation
-====
-
-It contains all the documenation for Ngspice and Ghdl related work.
-
-Note: This project is still in alpha version and has been tested for basic digital components.
-====
-
-## What exactly interfacing of ngspice ghdl do?
-Ngspice support mixed mode simulation. It can simulate both digital and analog component.
-
-Ngspice has something called model which define the functionality of your circuit,which can be used in the netlist. For example you can create adder model in ngspice and use it in any circuit netlist of ngspice.
-
-Now the question is if we already have digital model in ngspice why this interfacing ?
-Well in ngspice it is little tediouse to write your digital model. But many people are familiar with ghdl and can easily write the vhdl code.
-So the idea of interfacing is just to write ghdl code for a model and install it as dummy model in ngspice. So whenever ngspice look
-for that model it will actually call the ghdl to get the result.
-
-
-##Pre-requisites
-1. Ubuntu 12.04 (You can try it on other version and let us know)
-2. Python 2.7
-3. PyQt4
-4. ghdl
-
-##How to install?
-1. Clone this repository.
-2. Run `./install-nghdl.sh` It will install ngspice from source code and put it in $HOME.
-
-
-##Few words about installed code structure.
-1. Ngspice will be installed in home directory $HOME. If you already have ngspice-26 directory there it will take its backup.
-2. Source code for all other file will be present in ~/.esim-nghdl
-3. symlink nghdl is stored in /usr/local/bin
-
-##How to use?
-1. Run nghdl in command terminal.
-2. Upload your vhdl file.
-3. Model will be created with your name of your vhdl file.
-4. You can use this model in your netlist.
-
-##LIMITATION:
-1. You can use only one output port in your file.
-2. All the port should be std_logic_vector only.
-3. We can use only one code model of such type in our netlist.
-
-##FUTURE WORK
-1. Make changes to have more than one output.
-2. Making changes to include use of more than one code models.
-3. Interfacing it with esim formely known as Oscad so that we can use it in our schematic.
-
diff --git a/install-nghdl.sh b/install-nghdl.sh
index eade469..0831468 100755
--- a/install-nghdl.sh
+++ b/install-nghdl.sh
@@ -18,6 +18,7 @@
#===============================================================================
ngspice="ngspice-nghdl"
+ghdl="ghdl-0.36"
config_dir="$HOME/.nghdl"
config_file="config.ini"
src_dir=`pwd`
@@ -43,14 +44,63 @@ function addghdlPPA
fi
}
+# make
+# gnat
+# llvm
+# clang
+# zlib1g-dev
function installDependency
{
- echo "Installing ghdl.................................."
- sudo apt-get install -y ghdl
- echo "Installing flex.................................."
- sudo apt-get install -y flex
- echo "Installing bison................................."
- sudo apt-get install -y bison
+
+ # echo "Updating indexes to install latest versions......"
+ # sudo apt-get update
+
+ # echo "Installing dependencies for ghdl-0.36 LLVM......."
+ # echo "Installing make.................................."
+ # sudo apt-get install -y make
+ # echo "Installing gnat-5.................................."
+ # sudo apt-get install -y gnat-5
+ # echo "Installing llvm.................................."
+ # sudo apt-get install -y llvm
+ # echo "Installing clang.................................."
+ # sudo apt-get install -y clang
+ # echo "Installing zlib1g-dev.................................."
+ # sudo apt-get install -y zlib1g-dev
+
+ # if [ -d $HOME/$ghdl ]; then
+ # echo "$ghdl directory already exists at $HOME"
+ # echo "Leaving ghdl-0.36 LLVM installation"
+ # else
+ # tar -xzvf $ghdl.tar.gz -C $HOME
+ # if [ "$?" == 0 ];then
+ # echo "ghdl-0.36 LLVM successfully extracted to $HOME......"
+ # echo "Changing directory to ghdl-0.36 LLVM installation..."
+ # cd $HOME/$ghdl
+ # echo "Configuring ghdl-0.36 build as per requirements....."
+ # #Other configure flags can be found at - https://github.com/ghdl/ghdl/blob/master/configure
+ # sudo ./configure --with-llvm-config
+ # echo "Building the install file for ghdl-0.36 LLVM....."
+ # sudo make
+ # echo "Installing ghdl-0.36 LLVM....."
+ # sudo make install
+ # else
+ # echo "Unable to extract ghdl-0.36 LLVM"
+ # echo "Exiting installation"
+ # exit 1
+ # fi
+ # fi
+
+ echo "Installing flex.................................."
+ sudo apt-get install -y flex
+ echo "Installing bison................................."
+ sudo apt-get install -y bison
+
+ # Specific dependency for nvidia graphic cards
+ echo "Installing graphics dependency for ngspice souce build"
+ echo "Installing libxaw7................................"
+ sudo apt-get install libxaw7
+ echo "Installing libxaw7-dev............................"
+ sudo apt-get install libxaw7-dev
}
@@ -59,15 +109,12 @@ function installNgspice
echo "Installing ngspice..................................."
#Checking if ngspice-nghdl directory is already present in Home directory
if [ -d $HOME/$ngspice ];then
- echo "$ngspice directory already exist"
+ echo "$ngspice directory already exists at $HOME"
echo "Leaving ngspice installation"
-
-
else
-
#Extracting Ngspice to Home Directory
+ cd $src_dir
tar -xzvf $ngspice.tar.gz -C $HOME
-
if [ "$?" == 0 ];then
echo "Ngspice extracted sucessfuly to $HOME "
#change to ngspice-nghdl directory
@@ -82,18 +129,30 @@ function installNgspice
echo "------------------------------------"
sleep 5
../configure --enable-xspice --disable-debug --prefix=$HOME/$ngspice/install_dir/ --exec-prefix=$HOME/$ngspice/install_dir/
-
- #dirty fix for adding patch to ngspice base code
- cp $src_dir/src/outitf.c $HOME/$ngspice/src/frontend
+
+ #dirty fix for adding patch to ngspice base code
+ cp $src_dir/src/outitf.c $HOME/$ngspice/src/frontend
make
make install
if [ "$?" == 0 ];then
- echo "Ngspice Installed sucessfully"
+ echo "Ngspice Installed sucessfully......"
+ echo "Adding softlink for the installed ngspice......"
+
+ sudo ln -s $HOME/$ngspice/install_dir/bin/ngspice /usr/bin/ngspice
+ if [ "$?" == 0 ];then
+ echo "failed to add softlink"
+ echo "ngspice already installed at /usr/bin/ngspice..."
+ echo "Remove earlier installations and try again..."
+ else
+ echo "Added softlink for ngspce"
+ fi
+
else
echo "There was some error in installing ngspice"
fi
+
else
echo "Unable to extract ngspice tar file"
exit 1;
diff --git a/src/ghdlserver/ghdlserver.c b/src/ghdlserver/ghdlserver.c
index ac34a87..5bf2e99 100644
--- a/src/ghdlserver/ghdlserver.c
+++ b/src/ghdlserver/ghdlserver.c
@@ -77,7 +77,7 @@ static int get_ngspice_pid(void)
FILE* fp = NULL;
struct dirent* dir_entry;
char path[1024], rd_buff[1024];
- pid_t pid[32];
+ pid_t pid = -1;
if ((dirp = opendir("/proc/")) == NULL)
{
@@ -85,11 +85,6 @@ static int get_ngspice_pid(void)
exit(-1);
}
- for(int i=0; i<31; i++)
- pid[i] = -1;
-
- int i=0;
-
while ((dir_entry = readdir(dirp)) != NULL)
{
char* nptr;
@@ -113,19 +108,15 @@ static int get_ngspice_pid(void)
fscanf(fp, "%s", rd_buff);
if (strcmp(rd_buff, NGSPICE) == 0)
{
- pid[i++] = (pid_t)tmp;
- // break;
+ pid = (pid_t)tmp;
}
}
}
}
- for(int j=0; j<i; j++)
- printf("Pid : %d\n", pid[j]);
-
if (fp) fclose(fp);
- return(pid[i-1]);
+ return(pid);
}
/* 23.Mar.2017 - RM - Pass the sock_port argument. We need this if a netlist
generated by cgit (git 2.34.1) at 2024-12-22 13:43:36 +0000