summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Example/2-bit-inverter/2-bit-inverter.cir36
-rw-r--r--Example/2-bit-inverter/inverter.vhdl14
-rw-r--r--Example/bin_to_gray/bin_to_gray.vhdl4
-rw-r--r--Example/counter/updown_counter.vhdl32
-rw-r--r--Example/fa_SL/full_adder_sl.vhdl19
-rw-r--r--Example/fa_SL_SLV/full_adder_sl_slv.vhdl19
-rw-r--r--Example/logic_gates/inverter_gate.vhdl14
-rw-r--r--Example/logic_gates/xor_gate.vhdl13
-rw-r--r--Example/mux-demux/demux.vhdl (renamed from Example/demux/demux.vhdl)0
-rw-r--r--Example/mux-demux/mux.vhdl30
-rw-r--r--Example/nghdl_half_adder/nghdl_ha.vhdl22
-rw-r--r--Example/struct_fa/full_adder_structural.vhdl85
-rw-r--r--Example/trial_demux/t_demux.vhdl32
-rw-r--r--Example/trial_fa/trial_fa.vhdl19
-rw-r--r--Example/xor/myxor.vhdl15
-rw-r--r--Example/xor/xor-test.cir45
16 files changed, 91 insertions, 308 deletions
diff --git a/Example/2-bit-inverter/2-bit-inverter.cir b/Example/2-bit-inverter/2-bit-inverter.cir
deleted file mode 100644
index 88580dd..0000000
--- a/Example/2-bit-inverter/2-bit-inverter.cir
+++ /dev/null
@@ -1,36 +0,0 @@
-* analysis type *
-.tran 1n 100n
-*
-* input sources *
-v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.1n 2.0 10n 0.0 10.1n 2.0 15n 2.0 15.1n 2.0 20n 0 20.1n 2.0 25n 2.0 25.1n 2.0 30n 2.0 30.1n 2.0
- + 40n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 2.0)
-
-v2 200 0 DC PWL ( 0n 2.0 5n 2.0 5.1n 0.0 10n 0.0 10.1n 2.0 15n 2.0 15.1n 0.0 20n 0 20.1n 2.0 25n 2.0 25.1n 0.0 30n 2.0 30.1n 2.0
- + 40n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 2.0)
-
-* resistors to ground *
-r1 100 0 1k
-r2 200 0 1k
-
-rload1 300 0 10k
-rload2 400 0 10k
-*
-* adc_bridge blocks *
-aconverter1 [100 200] [1 2] adc_bridge1
-
-.model adc_bridge1 adc_bridge ( in_low =0.3 in_high =0.7
-+ rise_delay =1.0e-12 fall_delay =1.0e-12)
-
-ainverter [1 2] [10 20] inv1
-
-.model inv1 inverter(instance_id = 101 rise_delay = 1.0e-12 fall_delay = 1.0e-12 stop_time=90e-9)
-
-
-aconverter2 [10 20] [30 40] dac_bridge1
-
-.model dac_bridge1 dac_bridge( out_low=0.25 out_high=5.0
-+out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
-
-.end
-
-
diff --git a/Example/2-bit-inverter/inverter.vhdl b/Example/2-bit-inverter/inverter.vhdl
deleted file mode 100644
index 7eb3c67..0000000
--- a/Example/2-bit-inverter/inverter.vhdl
+++ /dev/null
@@ -1,14 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity inverter is
- port ( i: in std_logic_vector(0 downto 0);
- o: out std_logic_vector(0 downto 0));
-end inverter;
-
-architecture inverter_beh of inverter is
-begin
- o <= not i;
-end inverter_beh;
-
-
diff --git a/Example/bin_to_gray/bin_to_gray.vhdl b/Example/bin_to_gray/bin_to_gray.vhdl
index 542f7ec..d6045e8 100644
--- a/Example/bin_to_gray/bin_to_gray.vhdl
+++ b/Example/bin_to_gray/bin_to_gray.vhdl
@@ -3,8 +3,8 @@ USE ieee.std_logic_1164.ALL;
entity bin_to_gray is
port(
- bin : in std_logic_vector(3 downto 0); -- binary input
- G : out std_logic_vector(3 downto 0) -- gray code output
+ bin : in std_logic_vector(3 downto 0);
+ G : out std_logic_vector(3 downto 0)
);
end bin_to_gray;
diff --git a/Example/counter/updown_counter.vhdl b/Example/counter/updown_counter.vhdl
new file mode 100644
index 0000000..922ee67
--- /dev/null
+++ b/Example/counter/updown_counter.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+
+entity updown_counter is
+ Port ( clk: in std_logic;
+ reset: in std_logic;
+ up_down: in std_logic;
+ counter: out std_logic_vector(3 downto 0)
+ );
+end updown_counter;
+
+architecture Behavioral of updown_counter is
+signal tmp: std_logic_vector(3 downto 0);
+begin
+
+process(clk,reset)
+begin
+ if(reset='1') then
+ tmp <= "0000";
+ elsif(clk'event and clk='1') then
+ if(up_down='1') then
+ tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)-1), tmp'length));
+ else
+ tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)+1), tmp'length));
+ end if;
+ end if;
+end process;
+ counter <= std_logic_vector(tmp);
+
+end Behavioral; \ No newline at end of file
diff --git a/Example/fa_SL/full_adder_sl.vhdl b/Example/fa_SL/full_adder_sl.vhdl
deleted file mode 100644
index e830563..0000000
--- a/Example/fa_SL/full_adder_sl.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity full_adder_sl is
- port (
- i_bit1 : in std_logic;
- i_bit2 : in std_logic;
- i_bit3 : in std_logic;
- o_sum : out std_logic;
- o_carry : out std_logic
- );
-end full_adder_sl;
-
-architecture rtl of full_adder_sl is
-begin
- o_sum <= i_bit1 xor i_bit2 xor i_bit3;
- o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
-end rtl; \ No newline at end of file
diff --git a/Example/fa_SL_SLV/full_adder_sl_slv.vhdl b/Example/fa_SL_SLV/full_adder_sl_slv.vhdl
deleted file mode 100644
index 7de9c1b..0000000
--- a/Example/fa_SL_SLV/full_adder_sl_slv.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity full_adder_sl_slv is
- port (
- i_bit1 : in std_logic;
- i_bit2 : in std_logic;
- i_bit3 : in std_logic_vector(0 downto 0);
- o_sum : out std_logic;
- o_carry : out std_logic_vector(0 downto 0)
- );
-end full_adder_sl_slv;
-
-architecture rtl of full_adder_sl_slv is
-begin
- o_sum <= i_bit1 xor i_bit2 xor i_bit3(0);
- o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1);
-end rtl; \ No newline at end of file
diff --git a/Example/logic_gates/inverter_gate.vhdl b/Example/logic_gates/inverter_gate.vhdl
new file mode 100644
index 0000000..9825917
--- /dev/null
+++ b/Example/logic_gates/inverter_gate.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity inverter_gate is
+ port ( i: in std_logic;
+ o: out std_logic);
+end inverter_gate;
+
+architecture beh of inverter_gate is
+begin
+ o <= not i;
+end beh;
+
+
diff --git a/Example/logic_gates/xor_gate.vhdl b/Example/logic_gates/xor_gate.vhdl
new file mode 100644
index 0000000..da0da23
--- /dev/null
+++ b/Example/logic_gates/xor_gate.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xor_gate is
+ port (a : in std_logic;
+ b : in std_logic;
+ c : out std_logic);
+end xor_gate;
+
+architecture rtl of xor_gate is
+ begin
+ c <= a xor b;
+end rtl;
diff --git a/Example/demux/demux.vhdl b/Example/mux-demux/demux.vhdl
index e73c196..e73c196 100644
--- a/Example/demux/demux.vhdl
+++ b/Example/mux-demux/demux.vhdl
diff --git a/Example/mux-demux/mux.vhdl b/Example/mux-demux/mux.vhdl
new file mode 100644
index 0000000..b72e287
--- /dev/null
+++ b/Example/mux-demux/mux.vhdl
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity mux is
+ port(A : in std_logic;
+ B : in std_logic;
+ C : in std_logic;
+ D : in std_logic;
+ S0 : in std_logic;
+ S1 : in std_logic;
+ Z: out std_logic);
+end mux;
+
+architecture bhv of mux is
+begin
+process (A,B,C,D,S0,S1) is
+begin
+ if (S0 ='0' and S1 = '0') then
+ Z <= A;
+ elsif (S0 ='0' and S1 = '1') then
+ Z <= B;
+ elsif (S0 ='1' and S1 = '0') then
+ Z <= C;
+ else
+ Z <= D;
+ end if;
+
+end process;
+end bhv;
+
diff --git a/Example/nghdl_half_adder/nghdl_ha.vhdl b/Example/nghdl_half_adder/nghdl_ha.vhdl
deleted file mode 100644
index f9f2e92..0000000
--- a/Example/nghdl_half_adder/nghdl_ha.vhdl
+++ /dev/null
@@ -1,22 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity nghdl_ha is
-port (
- i_bit1 : in std_logic_vector(0 downto 0);
- i_bit2 : in std_logic_vector(0 downto 0);
- o_sum : out std_logic_vector(0 downto 0);
- o_carry : out std_logic_vector(0 downto 0)
- );
-end nghdl_ha;
-
-
-architecture rtl of nghdl_ha is
-
-begin
-
- o_sum <= i_bit1 xor i_bit2;
- o_carry <= i_bit1 and i_bit2;
-
-end rtl; \ No newline at end of file
diff --git a/Example/struct_fa/full_adder_structural.vhdl b/Example/struct_fa/full_adder_structural.vhdl
deleted file mode 100644
index 91b2762..0000000
--- a/Example/struct_fa/full_adder_structural.vhdl
+++ /dev/null
@@ -1,85 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity full_adder_structural is
-port(a: in std_logic;
- b: in std_logic;
- cin: in std_logic;
- sum: out std_logic;
- carry: out std_logic);
-end full_adder_structural;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity andgate is
-port(a: in std_logic;
- b: in std_logic;
- z: out std_logic);
-end andgate;
-
-architecture e1 of andgate is
-begin
-z <= a and b;
-end e1;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity xorgate is
-port(a: in std_logic;
- b: in std_logic;
- z: out std_logic);
-end xorgate;
-
-architecture e2 of xorgate is
-begin
-z <= a xor b;
-end e2;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity orgate is
-port(a: in std_logic;
- b: in std_logic;
- z: out std_logic);
-end orgate;
-
-architecture e3 of orgate is
-begin
-z <= a or b;
-end e3;
-
-
-architecture structural of full_adder_structural is
-
-component andgate
-port(a: in std_logic;
- b: in std_logic;
- z: out std_logic);
-end component;
-
-component xorgate
-port(a: in std_logic;
- b: in std_logic;
- z: out std_logic);
-end component;
-
-component orgate
-port(a: in std_logic;
- b: in std_logic;
- z: out std_logic);
-end component;
-
-signal c1,c2,c3: std_logic;
-
-begin
-
-u1 : xorgate port map(a,b,c1);
-u2 : xorgate port map(c1,cin,sum);
-u3 : andgate port map(c1,cin,c2);
-u4 : andgate port map(a,b,c3);
-u5 : orgate port map(c2,c3,carry);
-
-end structural; \ No newline at end of file
diff --git a/Example/trial_demux/t_demux.vhdl b/Example/trial_demux/t_demux.vhdl
deleted file mode 100644
index 1e1f0bd..0000000
--- a/Example/trial_demux/t_demux.vhdl
+++ /dev/null
@@ -1,32 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity t_demux is
- port(
-
- F : in STD_LOGIC_vector(0 downto 0);
- S0: in STD_LOGIC_vector(0 downto 0);
- S1: in STD_LOGIC_vector(0 downto 0);
- A: out STD_LOGIC_vector(0 downto 0);
- B: out STD_LOGIC_vector(0 downto 0);
- C: out STD_LOGIC_vector(0 downto 0);
- D: out STD_LOGIC_vector(0 downto 0)
- );
-end t_demux;
-
-architecture bhv of t_demux is
-begin
-process (F,S0,S1) is
-begin
- if (S0 ="0" and S1 = "0") then
- A <= F;
- elsif (S0 ="1" and S1 = "0") then
- B <= F;
- elsif (S0 ="0" and S1 = "1") then
- C <= F;
- else
- D <= F;
- end if;
-
-end process;
-end bhv; \ No newline at end of file
diff --git a/Example/trial_fa/trial_fa.vhdl b/Example/trial_fa/trial_fa.vhdl
deleted file mode 100644
index 6357aa2..0000000
--- a/Example/trial_fa/trial_fa.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity trial_fa is
- port (
- i_bit1 : in std_logic_vector(0 downto 0);
- i_bit2 : in std_logic_vector(0 downto 0);
- i_bit3 : in std_logic_vector(0 downto 0);
- o_sum : out std_logic_vector(0 downto 0);
- o_carry : out std_logic_vector(0 downto 0)
- );
-end trial_fa;
-
-architecture rtl of trial_fa is
-begin
- o_sum <= i_bit1 xor i_bit2 xor i_bit3;
- o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
-end rtl; \ No newline at end of file
diff --git a/Example/xor/myxor.vhdl b/Example/xor/myxor.vhdl
deleted file mode 100644
index b49f3ca..0000000
--- a/Example/xor/myxor.vhdl
+++ /dev/null
@@ -1,15 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity myxor is
- port (a : in std_logic_vector(0 downto 0);
- b : in std_logic_vector(0 downto 0);
- c : out std_logic_vector(0 downto 0));
- end myxor;
-
- architecture rtl of myxor is
- begin
-
- c <= a xor b;
-
- end rtl;
diff --git a/Example/xor/xor-test.cir b/Example/xor/xor-test.cir
deleted file mode 100644
index 910839e..0000000
--- a/Example/xor/xor-test.cir
+++ /dev/null
@@ -1,45 +0,0 @@
-
-*** input sources ***
-
-v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.1n 2.0 10n 2.0 10.1n 2.0 15n 2.0 15.1n 0.0 20.0n 0.0 20.1n 2.0 25n 2.0 25.1n 0.0 30n 0.0 30.1n 2.0
- +40.0 2.0 40.1n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 0.0)
-
-v2 200 0 DC PWL (0n 2.0 5n 2.0 10n 2.0 15n 2.0 15.1n 0.0 20n 0.0 25n 0.0 30n 0.0 30.1n 2.0 40n 2.0 40.1n 0.0 45n 0.0 45.1n 2.0
- + 50n 2.0 50.1n 0.0 60.0n 0.0 70n 0.0 80n 0.0 90n 0.0 95n 0.0 95.1n 2.0 100n 2.0)
-
-Vvdd vdd 0 DC 2.0
-
-*** resistors to ground ***
-r1 100 0 1k
-r2 200 0 1k
-
-
-*
-*** adc_bridge blocks ***
-aconverter1 [100 200 ] [1 2] adc
-
-
-axor [1] [2] [12] axors
-
-adac1 [12] [34] dac
-*************model***********
-
-.model axors myxor(instance_id = 112 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
-
-.model adc adc_bridge ( in_low =0.5 in_high =1.0
-+ rise_delay =1.0e-10 fall_delay =1.0e-10)
-.model dac dac_bridge(out_low = 0.0 out_high = 2.0 out_undef = 1.0
-+ input_load = 5.0e-14 t_rise = 1.0e-10
-+ t_fall = 1.0e-10)
-
-
-.end
-
-
-
-.CONTROL
-
-option noopalter
-tran .1n 100n
-.ENDC
-
generated by cgit (git 2.34.1) at 2024-12-21 09:38:30 +0000