diff options
20 files changed, 179 insertions, 27 deletions
diff --git a/Example/README.md b/Example/README.md deleted file mode 100644 index e3eb0cf..0000000 --- a/Example/README.md +++ /dev/null @@ -1,9 +0,0 @@ -Instructions on how to use the examples provided here: -1. Go to eSim main window -> Click on NGHDL icon from the left toolbar, click on the 'browse' button, go to ../nghdl/Example/ and locate which example you wish to simulate. -2. After opening the directory of desired example, locate the vhdl file , click on the "Open" button at the bottom of "Open File" window. -3. Click on 'upload' button in the NGHDL pop-up window. File will be processed in the backend for few seconds. Now exit the NGHDL window. -4. Open the desired example in eSim using the Open Project button, double click on it when the project is loaded in the "Projects" window. -5. Click on the "Simulation" button on eSim Main window. - -NGHDL feature is still under development. More examples will be added by eSim team along the way. -If you have a good command on VHDL and electronics, please feel free to contribute. diff --git a/Example/bin_to_gray/bin_to_gray.vhdl b/Example/combinational_logic/bin_to_gray/bin_to_gray.vhdl index d6045e8..d6045e8 100644 --- a/Example/bin_to_gray/bin_to_gray.vhdl +++ b/Example/combinational_logic/bin_to_gray/bin_to_gray.vhdl diff --git a/Example/combinational_logic/counter/decadecounter.vhdl b/Example/combinational_logic/counter/decadecounter.vhdl new file mode 100644 index 0000000..6d84280 --- /dev/null +++ b/Example/combinational_logic/counter/decadecounter.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity decadecounter is + port(CLK : in std_logic; + RST : in std_logic; + Count : out std_logic_vector(9 downto 0)); +end decadecounter; + +architecture beh of decadecounter is + signal a: std_logic_vector(9 downto 0) := "0000000001"; +begin + process(CLK, RST) + begin + if RST = '1' then + a <= "0000000001"; + elsif rising_edge(CLK) then + a <= a(0) & a(9 downto 1); -- rotating left + end if; + end process; + Count <= std_logic_vector (a); +end beh; diff --git a/Example/counter/up_counter.vhdl b/Example/combinational_logic/counter/up_counter.vhdl index bd27fcf..80e9783 100644 --- a/Example/counter/up_counter.vhdl +++ b/Example/combinational_logic/counter/up_counter.vhdl @@ -31,4 +31,4 @@ architecture beh of up_counter is end process; Q <= std_logic_vector (tmp); -end beh;
\ No newline at end of file +end beh; diff --git a/Example/counter/up_counter_slv.vhdl b/Example/combinational_logic/counter/up_counter_slv.vhdl index afef463..ec8a558 100644 --- a/Example/counter/up_counter_slv.vhdl +++ b/Example/combinational_logic/counter/up_counter_slv.vhdl @@ -1,4 +1,8 @@ +-- This logic is implemented in up_counter.vhdl example as well, but there tmp variable is declared as unsigned +--whereas here it is declared as std_logic_vector; which requires type conversion. +--slv stands for std_logic_vector library ieee; + use ieee.std_logic_1164.all; use ieee.numeric_std.all; @@ -9,16 +13,20 @@ port(C : in std_logic; end up_counter_slv; architecture bhv of up_counter_slv is + signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then - tmp <= "0000"; + tmp <= "0000"; + elsif (C'event and C='1') then - tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length)); + tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length)); + end if; + end process; Q <= tmp; -end bhv;
\ No newline at end of file +end bhv; diff --git a/Example/combinational_logic/counter/updown_counter.vhdl b/Example/combinational_logic/counter/updown_counter.vhdl new file mode 100644 index 0000000..922ee67 --- /dev/null +++ b/Example/combinational_logic/counter/updown_counter.vhdl @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + + +entity updown_counter is + Port ( clk: in std_logic; + reset: in std_logic; + up_down: in std_logic; + counter: out std_logic_vector(3 downto 0) + ); +end updown_counter; + +architecture Behavioral of updown_counter is +signal tmp: std_logic_vector(3 downto 0); +begin + +process(clk,reset) +begin + if(reset='1') then + tmp <= "0000"; + elsif(clk'event and clk='1') then + if(up_down='1') then + tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)-1), tmp'length)); + else + tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)+1), tmp'length)); + end if; + end if; +end process; + counter <= std_logic_vector(tmp); + +end Behavioral;
\ No newline at end of file diff --git a/Example/decoder/decoder.vhdl b/Example/combinational_logic/decoder/decoder.vhdl index e429ec9..e429ec9 100644 --- a/Example/decoder/decoder.vhdl +++ b/Example/combinational_logic/decoder/decoder.vhdl diff --git a/Example/full_adder/full_adder_sl.vhdl b/Example/combinational_logic/full_adder/full_adder_sl.vhdl index e830563..99976ba 100644 --- a/Example/full_adder/full_adder_sl.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_sl.vhdl @@ -1,3 +1,4 @@ +-- This file uses only std_logic(sl) variable types library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; @@ -16,4 +17,4 @@ architecture rtl of full_adder_sl is begin o_sum <= i_bit1 xor i_bit2 xor i_bit3; o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); -end rtl;
\ No newline at end of file +end rtl; diff --git a/Example/full_adder/full_adder_sl_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl index 7de9c1b..cd7b5f3 100644 --- a/Example/full_adder/full_adder_sl_slv.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl @@ -1,3 +1,4 @@ +--This file uses combination of std_logic(sl) and std_logic_vector(slv) variable types library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; @@ -16,4 +17,4 @@ architecture rtl of full_adder_sl_slv is begin o_sum <= i_bit1 xor i_bit2 xor i_bit3(0); o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1); -end rtl;
\ No newline at end of file +end rtl; diff --git a/Example/full_adder/full_adder_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_slv.vhdl index a0495f0..8dccce9 100644 --- a/Example/full_adder/full_adder_slv.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_slv.vhdl @@ -1,3 +1,4 @@ +--This file uses only std_logic_vector(slv) variable type library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/Example/full_adder/full_adder_structural.vhdl b/Example/combinational_logic/full_adder/full_adder_structural.vhdl index eb06a3d..ad13a2d 100644 --- a/Example/full_adder/full_adder_structural.vhdl +++ b/Example/combinational_logic/full_adder/full_adder_structural.vhdl @@ -1,3 +1,4 @@ +--This file uses structural style and uses only std_logic variable type library ieee; use ieee.std_logic_1164.all; @@ -84,4 +85,4 @@ u4 : andgate port map(a,b,c3); u5 : orgate port map(c2,c3,carry); -end structural;
\ No newline at end of file +end structural; diff --git a/Example/half_adder/half_adder.vhdl b/Example/combinational_logic/half_adder/half_adder.vhdl index 71ef1cc..71ef1cc 100644 --- a/Example/half_adder/half_adder.vhdl +++ b/Example/combinational_logic/half_adder/half_adder.vhdl diff --git a/Example/mux-demux/demux.vhdl b/Example/combinational_logic/mux-demux/demux.vhdl index e73c196..e73c196 100644 --- a/Example/mux-demux/demux.vhdl +++ b/Example/combinational_logic/mux-demux/demux.vhdl diff --git a/Example/mux-demux/mux.vhdl b/Example/combinational_logic/mux-demux/mux.vhdl index b72e287..b72e287 100644 --- a/Example/mux-demux/mux.vhdl +++ b/Example/combinational_logic/mux-demux/mux.vhdl diff --git a/Example/logic_gates/and_gate.vhdl b/Example/logic_gates/and_gate.vhdl new file mode 100644 index 0000000..689bcba --- /dev/null +++ b/Example/logic_gates/and_gate.vhdl @@ -0,0 +1,33 @@ +library ieee; + +use ieee.std_logic_1164.all; + +entity and_gate is + +port( a: in std_logic; + b: in std_logic; + c: out std_logic +); + +end and_gate; + +architecture beh of and_gate is + + begin + + process(a, b) + + begin + + if (a='1' and b='1') then + c <= '1'; + + else + + c <= '0'; + + end if; + + end process; + +end beh; diff --git a/Example/logic_gates/inverter_gate.vhdl b/Example/logic_gates/inverter.vhdl index 9825917..ee2d830 100644 --- a/Example/logic_gates/inverter_gate.vhdl +++ b/Example/logic_gates/inverter.vhdl @@ -1,12 +1,12 @@ library ieee; use ieee.std_logic_1164.all; -entity inverter_gate is +entity inverter is port ( i: in std_logic; o: out std_logic); -end inverter_gate; +end inverter; -architecture beh of inverter_gate is +architecture beh of inverter is begin o <= not i; end beh; diff --git a/Example/logic_gates/nand_gate.vhdl b/Example/logic_gates/nand_gate.vhdl new file mode 100644 index 0000000..3736285 --- /dev/null +++ b/Example/logic_gates/nand_gate.vhdl @@ -0,0 +1,33 @@ +library ieee; + +use ieee.std_logic_1164.all; + +entity nand_gate is + +port( a: in std_logic; + b: in std_logic; + c: out std_logic +); + +end nand_gate; + +architecture beh of nand_gate is + + begin + + process(a, b) + + begin + + if (a='1' and b='1') then + c <= '0'; + + else + + c <= '1'; + + end if; + + end process; + +end beh; diff --git a/Example/logic_gates/nor_gate.vhdl b/Example/logic_gates/nor_gate.vhdl new file mode 100644 index 0000000..0dcdab0 --- /dev/null +++ b/Example/logic_gates/nor_gate.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity nor_gate is + port (a : in std_logic; + b : in std_logic; + c : out std_logic); +end nor_gate; + +architecture rtl of nor_gate is + begin + c <= a nor b; +end rtl; diff --git a/Example/logic_gates/or_gate.vhdl b/Example/logic_gates/or_gate.vhdl new file mode 100644 index 0000000..d470c3d --- /dev/null +++ b/Example/logic_gates/or_gate.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity or_gate is + Port ( a : in STD_LOGIC; + b : in STD_LOGIC; + c : out STD_LOGIC); +end or_gate; + +architecture behavioral of or_gate is +begin +c <= a or b; +end behavioral; @@ -30,19 +30,21 @@ for that model it will actually call the ghdl to get the result. ##Few words about installed code structure. -1. Ngspice will be installed in home directory $HOME. If you already have ngspice-31 directory there it will take its backup. +1. Ngspice will be installed in home directory $HOME. 2. Source code for all other file will be present in ~/.esim-nghdl 3. symlink nghdl is stored in /usr/local/bin -##How to use? -1. Run nghdl in command terminal. -2. Upload your vhdl file. -3. Model will be created with name of your vhdl file. It can be seen under (~/ngspice-nghdl/src/xspice/icm/ghdl/) -4. You can use this model in your netlist. - - ##FEATURES: 1. Support for 512 digital models. 2. Support for digital models upto 64 output ports/pins. 3. Multiple instances of same digital model. + + +##How to use the Examples provided with NGHDL? +1. Launch eSim-> go to eSim main window -> Click on NGHDL icon from the left toolbar, click on the 'browse' button, go to ../nghdl/Example/ and locate which example you wish to simulate. +2. After opening the directory of desired example, locate the vhdl file , click on the "Open" button at the bottom of "Open File" window. +3. Click on 'upload' button in the NGHDL pop-up window. File will be processed in the backend for few seconds. Now exit the NGHDL window. +4. Open the desired example under eSim/Examples/NGHDL_Examples/ using the Open Project button, double click on the project when the project is loaded in the "Projects" window. +5. Click on the "Simulation" button on eSim Main window. + |