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| author | fahim | 2015-02-05 17:46:55 +0530 |
|---|---|---|
| committer | fahim | 2015-02-05 17:46:55 +0530 |
| commit | ad36bcd34ffe111f2981936ac44cd007dbe483de (patch) | |
| tree | 0565d9e40eb7992063465aeed415bce23c558540 /Example/xor/xor-test.cir | |
| parent | 15e75633d9d30330f7d74a3c6e639458ad09dd0b (diff) | |
| download | nghdl-ad36bcd34ffe111f2981936ac44cd007dbe483de.tar.gz nghdl-ad36bcd34ffe111f2981936ac44cd007dbe483de.tar.bz2 nghdl-ad36bcd34ffe111f2981936ac44cd007dbe483de.zip | |
Subject: Added example
Description: Added two example xor and 2-bit inverter
Diffstat (limited to 'Example/xor/xor-test.cir')
| -rw-r--r-- | Example/xor/xor-test.cir | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/Example/xor/xor-test.cir b/Example/xor/xor-test.cir new file mode 100644 index 0000000..7d13e58 --- /dev/null +++ b/Example/xor/xor-test.cir @@ -0,0 +1,45 @@ + +*** input sources *** + +v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.1n 2.0 10n 2.0 10.1n 2.0 15n 2.0 15.1n 0.0 20.0n 0.0 20.1n 2.0 25n 2.0 25.1n 0.0 30n 0.0 30.1n 2.0 + +40.0 2.0 40.1n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 0.0) + +v2 200 0 DC PWL (0n 2.0 5n 2.0 10n 2.0 15n 2.0 15.1n 0.0 20n 0.0 25n 0.0 30n 0.0 30.1n 2.0 40n 2.0 40.1n 0.0 45n 0.0 45.1n 2.0 + + 50n 2.0 50.1n 0.0 60.0n 0.0 70n 0.0 80n 0.0 90n 0.0 95n 0.0 95.1n 2.0 100n 2.0) + +Vvdd vdd 0 DC 2.0 + +*** resistors to ground *** +r1 100 0 1k +r2 200 0 1k + + +* +*** adc_bridge blocks *** +aconverter1 [100 200 ] [1 2] adc + + +axor [1] [2] [12] axors + +adac1 [12] [34] dac +*************model*********** + +.model axors myxor(rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n) + +.model adc adc_bridge ( in_low =0.5 in_high =1.0 ++ rise_delay =1.0e-10 fall_delay =1.0e-10) +.model dac dac_bridge(out_low = 0.0 out_high = 2.0 out_undef = 1.0 ++ input_load = 5.0e-14 t_rise = 1.0e-10 ++ t_fall = 1.0e-10) + + +.end + + + +.CONTROL + +option noopalter +tran .1n 100n +.ENDC + |