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author | rahul | 2019-10-22 11:27:47 +0530 |
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committer | rahul | 2019-10-22 11:27:47 +0530 |
commit | 76241122c16990ee003df89391c85ee478ea0dca (patch) | |
tree | 8055abb97cb298fa4dde4e11a3759ff2ea7358f0 /Example/xor/myxor.vhdl | |
parent | 0b2a123b6ea6c3d09fae9fb054849432373794cf (diff) | |
download | nghdl-76241122c16990ee003df89391c85ee478ea0dca.tar.gz nghdl-76241122c16990ee003df89391c85ee478ea0dca.tar.bz2 nghdl-76241122c16990ee003df89391c85ee478ea0dca.zip |
Examples
Diffstat (limited to 'Example/xor/myxor.vhdl')
-rw-r--r-- | Example/xor/myxor.vhdl | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/Example/xor/myxor.vhdl b/Example/xor/myxor.vhdl deleted file mode 100644 index b49f3ca..0000000 --- a/Example/xor/myxor.vhdl +++ /dev/null @@ -1,15 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity myxor is - port (a : in std_logic_vector(0 downto 0); - b : in std_logic_vector(0 downto 0); - c : out std_logic_vector(0 downto 0)); - end myxor; - - architecture rtl of myxor is - begin - - c <= a xor b; - - end rtl; |