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authorrahul2019-10-22 11:27:47 +0530
committerrahul2019-10-22 11:27:47 +0530
commit76241122c16990ee003df89391c85ee478ea0dca (patch)
tree8055abb97cb298fa4dde4e11a3759ff2ea7358f0 /Example/xor/myxor.vhdl
parent0b2a123b6ea6c3d09fae9fb054849432373794cf (diff)
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Examples
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-library ieee;
-use ieee.std_logic_1164.all;
-
-entity myxor is
- port (a : in std_logic_vector(0 downto 0);
- b : in std_logic_vector(0 downto 0);
- c : out std_logic_vector(0 downto 0));
- end myxor;
-
- architecture rtl of myxor is
- begin
-
- c <= a xor b;
-
- end rtl;