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author | fossee | 2019-09-03 11:07:32 +0530 |
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committer | fossee | 2019-09-03 11:07:32 +0530 |
commit | f8d3dbc8c0f1c59a0546998cb9365e5c291dca07 (patch) | |
tree | 28f0d2fe7f00f1ee854e411b82689eae861a9c52 /Example/nghdl_half_adder | |
parent | 491e95ad13764229c3e27dfb625c5dbef9ddec59 (diff) | |
download | nghdl-f8d3dbc8c0f1c59a0546998cb9365e5c291dca07.tar.gz nghdl-f8d3dbc8c0f1c59a0546998cb9365e5c291dca07.tar.bz2 nghdl-f8d3dbc8c0f1c59a0546998cb9365e5c291dca07.zip |
added examples and modified server
Diffstat (limited to 'Example/nghdl_half_adder')
-rw-r--r-- | Example/nghdl_half_adder/nghdl_ha.vhdl | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Example/nghdl_half_adder/nghdl_ha.vhdl b/Example/nghdl_half_adder/nghdl_ha.vhdl new file mode 100644 index 0000000..f9f2e92 --- /dev/null +++ b/Example/nghdl_half_adder/nghdl_ha.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity nghdl_ha is +port ( + i_bit1 : in std_logic_vector(0 downto 0); + i_bit2 : in std_logic_vector(0 downto 0); + o_sum : out std_logic_vector(0 downto 0); + o_carry : out std_logic_vector(0 downto 0) + ); +end nghdl_ha; + + +architecture rtl of nghdl_ha is + +begin + + o_sum <= i_bit1 xor i_bit2; + o_carry <= i_bit1 and i_bit2; + +end rtl;
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