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authorrahul2019-10-22 11:27:47 +0530
committerrahul2019-10-22 11:27:47 +0530
commit76241122c16990ee003df89391c85ee478ea0dca (patch)
tree8055abb97cb298fa4dde4e11a3759ff2ea7358f0 /Example/logic_gates
parent0b2a123b6ea6c3d09fae9fb054849432373794cf (diff)
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Examples
Diffstat (limited to 'Example/logic_gates')
-rw-r--r--Example/logic_gates/inverter_gate.vhdl14
-rw-r--r--Example/logic_gates/xor_gate.vhdl13
2 files changed, 27 insertions, 0 deletions
diff --git a/Example/logic_gates/inverter_gate.vhdl b/Example/logic_gates/inverter_gate.vhdl
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+++ b/Example/logic_gates/inverter_gate.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity inverter_gate is
+ port ( i: in std_logic;
+ o: out std_logic);
+end inverter_gate;
+
+architecture beh of inverter_gate is
+begin
+ o <= not i;
+end beh;
+
+
diff --git a/Example/logic_gates/xor_gate.vhdl b/Example/logic_gates/xor_gate.vhdl
new file mode 100644
index 0000000..da0da23
--- /dev/null
+++ b/Example/logic_gates/xor_gate.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xor_gate is
+ port (a : in std_logic;
+ b : in std_logic;
+ c : out std_logic);
+end xor_gate;
+
+architecture rtl of xor_gate is
+ begin
+ c <= a xor b;
+end rtl;