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authorrahul2019-10-22 11:27:47 +0530
committerrahul2019-10-22 11:27:47 +0530
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parent0b2a123b6ea6c3d09fae9fb054849432373794cf (diff)
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Examples
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xor_gate is
+ port (a : in std_logic;
+ b : in std_logic;
+ c : out std_logic);
+end xor_gate;
+
+architecture rtl of xor_gate is
+ begin
+ c <= a xor b;
+end rtl;