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authorsaurabhb172019-12-18 15:13:23 +0530
committersaurabhb172019-12-18 15:13:23 +0530
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity or_gate is
+ Port ( a : in STD_LOGIC;
+ b : in STD_LOGIC;
+ c : out STD_LOGIC);
+end or_gate;
+
+architecture behavioral of or_gate is
+begin
+c <= a or b;
+end behavioral;