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author | saurabhb17 | 2019-12-18 15:13:23 +0530 |
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committer | saurabhb17 | 2019-12-18 15:13:23 +0530 |
commit | eb95026ab9007631eb8e2a1c54dcd38fabcb60ad (patch) | |
tree | 8695e410cfe16a3b2e37600cd64b3f0b9a5673e2 /Example/logic_gates/or_gate.vhdl | |
parent | 04d9c666b4bb19936dfa469f536fb38107e631eb (diff) | |
download | nghdl-eb95026ab9007631eb8e2a1c54dcd38fabcb60ad.tar.gz nghdl-eb95026ab9007631eb8e2a1c54dcd38fabcb60ad.tar.bz2 nghdl-eb95026ab9007631eb8e2a1c54dcd38fabcb60ad.zip |
Examples Restructered
Diffstat (limited to 'Example/logic_gates/or_gate.vhdl')
-rw-r--r-- | Example/logic_gates/or_gate.vhdl | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/Example/logic_gates/or_gate.vhdl b/Example/logic_gates/or_gate.vhdl new file mode 100644 index 0000000..d470c3d --- /dev/null +++ b/Example/logic_gates/or_gate.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity or_gate is + Port ( a : in STD_LOGIC; + b : in STD_LOGIC; + c : out STD_LOGIC); +end or_gate; + +architecture behavioral of or_gate is +begin +c <= a or b; +end behavioral; |