Merge pull request #35 from saurabhb17/master

Changes for 1.1.3 version release

1 files changed, 13 insertions, 0 deletions

diff --git a/Example/logic_gates/or_gate.vhdl b/Example/logic_gates/or_gate.vhdl
new file mode 100644
index 0000000..d470c3d
--- /dev/null
+++ b/Example/logic_gates/or_gate.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity or_gate is
+    Port ( a : in  STD_LOGIC;    
+           b : in  STD_LOGIC;    
+           c : out  STD_LOGIC);    
+end or_gate;
+
+architecture behavioral of or_gate is
+begin
+c <= a or b;    
+end behavioral;