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authorsaurabhb172019-12-18 15:13:23 +0530
committersaurabhb172019-12-18 15:13:23 +0530
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Examples Restructered
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-rw-r--r--Example/half_adder/half_adder.vhdl18
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diff --git a/Example/half_adder/half_adder.vhdl b/Example/half_adder/half_adder.vhdl
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-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity half_adder is
- port (
- i_bit0 : in std_logic_vector(0 downto 0);
- i_bit1 : in std_logic_vector(0 downto 0);
- o_sum : out std_logic_vector(0 downto 0);
- o_carry : out std_logic_vector(0 downto 0)
- );
-end half_adder;
-
-architecture rtl of half_adder is
-begin
- o_sum <= i_bit0 xor i_bit1;
- o_carry <= i_bit0 and i_bit1;
-end rtl;