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authorRahul Paknikar2019-07-07 18:48:39 +0530
committerGitHub2019-07-07 18:48:39 +0530
commit385d1b79fa4d4a4c9fe39f72cd87d53b247704d4 (patch)
treec8b2e50a414bdcf528a1ecdafc235705b8f6675b /Example/full_adder
parent45f2669e5ba6760c6adaacb564c0799d54a11052 (diff)
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std_logic_vector
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-rw-r--r--Example/full_adder/full_adder_slv.vhdl (renamed from Example/full_adder/full_adder_sl.vhdl)0
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diff --git a/Example/full_adder/full_adder_sl.vhdl b/Example/full_adder/full_adder_slv.vhdl
index a0495f0..a0495f0 100644
--- a/Example/full_adder/full_adder_sl.vhdl
+++ b/Example/full_adder/full_adder_slv.vhdl