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authorsaurabhb172019-12-18 15:13:23 +0530
committersaurabhb172019-12-18 15:13:23 +0530
commiteb95026ab9007631eb8e2a1c54dcd38fabcb60ad (patch)
tree8695e410cfe16a3b2e37600cd64b3f0b9a5673e2 /Example/full_adder/full_adder_sl_slv.vhdl
parent04d9c666b4bb19936dfa469f536fb38107e631eb (diff)
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Examples Restructered
Diffstat (limited to 'Example/full_adder/full_adder_sl_slv.vhdl')
-rw-r--r--Example/full_adder/full_adder_sl_slv.vhdl19
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diff --git a/Example/full_adder/full_adder_sl_slv.vhdl b/Example/full_adder/full_adder_sl_slv.vhdl
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--- a/Example/full_adder/full_adder_sl_slv.vhdl
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-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity full_adder_sl_slv is
- port (
- i_bit1 : in std_logic;
- i_bit2 : in std_logic;
- i_bit3 : in std_logic_vector(0 downto 0);
- o_sum : out std_logic;
- o_carry : out std_logic_vector(0 downto 0)
- );
-end full_adder_sl_slv;
-
-architecture rtl of full_adder_sl_slv is
-begin
- o_sum <= i_bit1 xor i_bit2 xor i_bit3(0);
- o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1);
-end rtl; \ No newline at end of file