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author | saurabhb17 | 2019-12-18 15:13:23 +0530 |
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committer | saurabhb17 | 2019-12-18 15:13:23 +0530 |
commit | eb95026ab9007631eb8e2a1c54dcd38fabcb60ad (patch) | |
tree | 8695e410cfe16a3b2e37600cd64b3f0b9a5673e2 /Example/counter | |
parent | 04d9c666b4bb19936dfa469f536fb38107e631eb (diff) | |
download | nghdl-eb95026ab9007631eb8e2a1c54dcd38fabcb60ad.tar.gz nghdl-eb95026ab9007631eb8e2a1c54dcd38fabcb60ad.tar.bz2 nghdl-eb95026ab9007631eb8e2a1c54dcd38fabcb60ad.zip |
Examples Restructered
Diffstat (limited to 'Example/counter')
-rw-r--r-- | Example/counter/up_counter.vhdl | 34 | ||||
-rw-r--r-- | Example/counter/up_counter_slv.vhdl | 24 |
2 files changed, 0 insertions, 58 deletions
diff --git a/Example/counter/up_counter.vhdl b/Example/counter/up_counter.vhdl deleted file mode 100644 index bd27fcf..0000000 --- a/Example/counter/up_counter.vhdl +++ /dev/null @@ -1,34 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity up_counter is - port(Clock : in std_logic; - CLR : in std_logic; - Q : out std_logic_vector(3 downto 0)); -end up_counter; - -architecture beh of up_counter is - signal tmp: unsigned(3 downto 0) := "0000"; - - --------------- Other ways to initialize -------------- - -- signal tmp: unsigned(3 downto 0) := x"0"; - -- signal tmp: unsigned(3 downto 0) := (others => '0'); - ------------------------------------------------------- - - begin - process (Clock, CLR) - begin - if (CLR='1') then - tmp <= "0000"; - elsif (Clock'event and Clock='1') then - if tmp="1111" then - tmp <= x"0"; - else - tmp <= tmp +1; - end if; - end if; - end process; - - Q <= std_logic_vector (tmp); -end beh;
\ No newline at end of file diff --git a/Example/counter/up_counter_slv.vhdl b/Example/counter/up_counter_slv.vhdl deleted file mode 100644 index afef463..0000000 --- a/Example/counter/up_counter_slv.vhdl +++ /dev/null @@ -1,24 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity up_counter_slv is -port(C : in std_logic; - CLR : in std_logic; - Q : out std_logic_vector(3 downto 0)); -end up_counter_slv; - -architecture bhv of up_counter_slv is - signal tmp: std_logic_vector(3 downto 0); - begin - process (C, CLR) - begin - if (CLR='1') then - tmp <= "0000"; - elsif (C'event and C='1') then - tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length)); - end if; - end process; - Q <= tmp; - -end bhv;
\ No newline at end of file |