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author | saurabhb17 | 2019-12-18 15:13:23 +0530 |
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committer | saurabhb17 | 2019-12-18 15:13:23 +0530 |
commit | eb95026ab9007631eb8e2a1c54dcd38fabcb60ad (patch) | |
tree | 8695e410cfe16a3b2e37600cd64b3f0b9a5673e2 /Example/combinational_logic/mux-demux/demux.vhdl | |
parent | 04d9c666b4bb19936dfa469f536fb38107e631eb (diff) | |
download | nghdl-eb95026ab9007631eb8e2a1c54dcd38fabcb60ad.tar.gz nghdl-eb95026ab9007631eb8e2a1c54dcd38fabcb60ad.tar.bz2 nghdl-eb95026ab9007631eb8e2a1c54dcd38fabcb60ad.zip |
Examples Restructered
Diffstat (limited to 'Example/combinational_logic/mux-demux/demux.vhdl')
-rw-r--r-- | Example/combinational_logic/mux-demux/demux.vhdl | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/Example/combinational_logic/mux-demux/demux.vhdl b/Example/combinational_logic/mux-demux/demux.vhdl new file mode 100644 index 0000000..e73c196 --- /dev/null +++ b/Example/combinational_logic/mux-demux/demux.vhdl @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity demux is + port( + + F : in STD_LOGIC_vector(0 downto 0); + S0: in STD_LOGIC_vector(0 downto 0); + S1: in STD_LOGIC_vector(0 downto 0); + A: out STD_LOGIC_vector(0 downto 0); + B: out STD_LOGIC_vector(0 downto 0); + C: out STD_LOGIC_vector(0 downto 0); + D: out STD_LOGIC_vector(0 downto 0) + ); +end demux; + +architecture bhv of demux is +begin +process (F,S0,S1) is +begin + if (S0 ="0" and S1 = "0") then + A <= F; + elsif (S0 ="1" and S1 = "0") then + B <= F; + elsif (S0 ="0" and S1 = "1") then + C <= F; + else + D <= F; + end if; + +end process; +end bhv; |