Merge pull request #35 from saurabhb17/master

Changes for 1.1.3 version release

1 files changed, 18 insertions, 0 deletions

diff --git a/Example/combinational_logic/half_adder/half_adder.vhdl b/Example/combinational_logic/half_adder/half_adder.vhdl
new file mode 100644
index 0000000..71ef1cc
--- /dev/null
+++ b/Example/combinational_logic/half_adder/half_adder.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity half_adder is
+  port (
+    i_bit0  : in std_logic_vector(0 downto 0);
+    i_bit1  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end half_adder;
+ 
+architecture rtl of half_adder is
+begin
+  o_sum   <= i_bit0 xor i_bit1;
+  o_carry <= i_bit0 and i_bit1;
+end rtl;