Merge pull request #35 from saurabhb17/master

Changes for 1.1.3 version release

4 files changed, 148 insertions, 0 deletions

diff --git a/Example/combinational_logic/full_adder/full_adder_sl.vhdl b/Example/combinational_logic/full_adder/full_adder_sl.vhdl
new file mode 100644
index 0000000..99976ba
--- /dev/null
+++ b/Example/combinational_logic/full_adder/full_adder_sl.vhdl
@@ -0,0 +1,20 @@
+-- This file uses only std_logic(sl) variable types
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_sl is
+  port (
+    i_bit1  : in std_logic;
+    i_bit2  : in std_logic;
+    i_bit3  : in std_logic;
+    o_sum   : out std_logic;
+    o_carry : out std_logic
+    );
+end full_adder_sl;
+ 
+architecture rtl of full_adder_sl is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
diff --git a/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl
new file mode 100644
index 0000000..cd7b5f3
--- /dev/null
+++ b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl
@@ -0,0 +1,20 @@
+--This file uses combination of std_logic(sl) and std_logic_vector(slv) variable types
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_sl_slv is
+  port (
+    i_bit1  : in std_logic;
+    i_bit2  : in std_logic;
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic;
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end full_adder_sl_slv;
+ 
+architecture rtl of full_adder_sl_slv is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3(0);
+  o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1);
+end rtl;
diff --git a/Example/combinational_logic/full_adder/full_adder_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_slv.vhdl
new file mode 100644
index 0000000..8dccce9
--- /dev/null
+++ b/Example/combinational_logic/full_adder/full_adder_slv.vhdl
@@ -0,0 +1,20 @@
+--This file uses only std_logic_vector(slv) variable type
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity full_adder_slv is
+  port (
+    i_bit1  : in std_logic_vector(0 downto 0);
+    i_bit2  : in std_logic_vector(0 downto 0);
+    i_bit3  : in std_logic_vector(0 downto 0);
+    o_sum   : out std_logic_vector(0 downto 0);
+    o_carry : out std_logic_vector(0 downto 0)
+    );
+end full_adder_slv;
+ 
+architecture rtl of full_adder_slv is
+begin
+  o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
+  o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
+end rtl;
diff --git a/Example/combinational_logic/full_adder/full_adder_structural.vhdl b/Example/combinational_logic/full_adder/full_adder_structural.vhdl
new file mode 100644
index 0000000..ad13a2d
--- /dev/null
+++ b/Example/combinational_logic/full_adder/full_adder_structural.vhdl
@@ -0,0 +1,88 @@
+--This file uses structural style and uses only std_logic variable type
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity full_adder_structural is
+port(a: in std_logic;
+	 b: in std_logic;
+     cin: in std_logic;
+     sum: out std_logic;
+     carry: out std_logic);
+end full_adder_structural;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity andgate is
+port(a: in std_logic;
+     b: in std_logic;
+     z: out std_logic);
+end andgate;
+
+architecture e1 of andgate is
+begin
+z <= a and b;
+end e1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xorgate is
+port(a: in std_logic;
+     b: in std_logic;
+     z: out std_logic);
+end xorgate;
+
+architecture e2 of xorgate is
+begin
+z <= a xor b;
+end e2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity orgate is
+port(a: in std_logic;
+     b: in std_logic;
+     z: out std_logic);
+end orgate;
+
+architecture e3 of orgate is
+begin
+z <= a or b;
+end e3;
+
+
+
+architecture structural of full_adder_structural is
+
+component andgate
+port(a: in std_logic;
+     b: in std_logic;
+     z: out std_logic);
+end component;
+
+component xorgate
+port(a: in std_logic;
+	 b: in std_logic;
+     z: out std_logic);
+end component;
+
+component orgate
+port(a: in std_logic;
+	 b: in std_logic;
+     z: out std_logic);
+end component;
+
+signal c1,c2,c3: std_logic;
+
+begin
+
+u1 : xorgate port map(a,b,c1);
+u2 : xorgate port map(c1,cin,sum);
+u3 : andgate port map(c1,cin,c2);
+u4 : andgate port map(a,b,c3);
+u5 : orgate port map(c2,c3,carry);
+
+
+end structural;